diff --git a/chisel/playground/src/pipeline/execute/fu/Lsu.scala b/chisel/playground/src/pipeline/execute/fu/Lsu.scala
index 4e0ee48..73009df 100644
--- a/chisel/playground/src/pipeline/execute/fu/Lsu.scala
+++ b/chisel/playground/src/pipeline/execute/fu/Lsu.scala
@@ -14,6 +14,9 @@ class Lsu extends Module {
     val dataSram = new DataSram()
   })
 
+  val allow_to_go = Wire(Bool())
+  BoringUtils.addSink(allow_to_go, "exe_allow_to_go")
+
   def genWmask(addr: UInt, sizeEncode: UInt): UInt = {
     LookupTree(
       sizeEncode,
@@ -58,7 +61,7 @@ class Lsu extends Module {
     )
   }
 
-  val valid        = io.info.valid && io.info.fusel === FuType.lsu // && 无异常
+  val valid        = io.info.valid && io.info.fusel === FuType.lsu && allow_to_go// && 无异常
   val op           = io.info.op
   val is_load      = valid && LSUOpType.isLoad(op)
   val is_store     = valid && LSUOpType.isStore(op)
@@ -114,10 +117,6 @@ class Lsu extends Module {
       "b11".U -> (addr(2, 0) === 0.U) //d
     )
   )
-
-  val allow_to_go = Wire(Bool())
-  BoringUtils.addSink(allow_to_go, "exe_allow_to_go")
-
   val addr_last = RegEnable(addr, allow_to_go)
 
   io.dataSram.en    := valid && addr_aligned