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refactor: 修改异常变量名称

This commit is contained in:
Liphen 2024-03-11 20:03:33 +08:00
parent 32005bb3e2
commit b782293dac
4 changed files with 24 additions and 24 deletions
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16
chisel/playground/src/defines/isa/Instructions.scala
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@ -271,9 +271,9 @@ trait HasCSRConst {
} }
trait HasExceptionNO { trait HasExceptionNO {
def instrAddrMisaligned = 0 def instAddrMisaligned = 0
def instrAccessFault = 1 def instAccessFault = 1
def illegalInstr = 2 def illegalInst = 2
def breakPoint = 3 def breakPoint = 3
def loadAddrMisaligned = 4 def loadAddrMisaligned = 4
def loadAccessFault = 5 def loadAccessFault = 5
@ -282,16 +282,16 @@ trait HasExceptionNO {
def ecallU = 8 def ecallU = 8
def ecallS = 9 def ecallS = 9
def ecallM = 11 def ecallM = 11
def instrPageFault = 12 def instPageFault = 12
def loadPageFault = 13 def loadPageFault = 13
def storePageFault = 15 def storePageFault = 15
val ExcPriority = Seq( val ExcPriority = Seq(
breakPoint, // TODO: different BP has different priority breakPoint, // TODO: different BP has different priority
instrPageFault, instPageFault,
instrAccessFault, instAccessFault,
illegalInstr, illegalInst,
instrAddrMisaligned, instAddrMisaligned,
ecallM, ecallM,
ecallS, ecallS,
ecallU, ecallU,

16
chisel/playground/src/pipeline/decode/DecodeUnit.scala
View File

@ -126,10 +126,10 @@ class DecodeUnit(implicit val cpuConfig: CpuConfig) extends Module with HasExcep
) )
(0 until (INT_WID)).foreach(j => io.executeStage.inst(i).ex.interrupt(j) := io.csr.interrupt(j)) (0 until (INT_WID)).foreach(j => io.executeStage.inst(i).ex.interrupt(j) := io.csr.interrupt(j))
io.executeStage.inst(i).ex.exception.map(_ := false.B) io.executeStage.inst(i).ex.exception.map(_ := false.B)
io.executeStage.inst(i).ex.exception(illegalInstr) := !info(i).inst_legal io.executeStage.inst(i).ex.exception(illegalInst) := !info(i).inst_legal
io.executeStage.inst(i).ex.exception(instrAccessFault) := io.instFifo.inst(i).access_fault io.executeStage.inst(i).ex.exception(instAccessFault) := io.instFifo.inst(i).access_fault
io.executeStage.inst(i).ex.exception(instrPageFault) := io.instFifo.inst(i).page_fault io.executeStage.inst(i).ex.exception(instPageFault) := io.instFifo.inst(i).page_fault
io.executeStage.inst(i).ex.exception(instrAddrMisaligned) := io.instFifo.inst(i).addr_misaligned || io.executeStage.inst(i).ex.exception(instAddrMisaligned) := io.instFifo.inst(i).addr_misaligned ||
io.fetchUnit.target(log2Ceil(INST_WID / 8) - 1, 0).orR && io.fetchUnit.branch io.fetchUnit.target(log2Ceil(INST_WID / 8) - 1, 0).orR && io.fetchUnit.branch
io.executeStage.inst(i).ex.exception(breakPoint) := io.executeStage.inst(i).ex.exception(breakPoint) :=
info(i).op === CSROpType.ebreak && info(i).fusel === FuType.csr info(i).op === CSROpType.ebreak && info(i).fusel === FuType.csr
@ -140,10 +140,10 @@ class DecodeUnit(implicit val cpuConfig: CpuConfig) extends Module with HasExcep
io.executeStage.inst(i).ex.exception(ecallU) := io.executeStage.inst(i).ex.exception(ecallU) :=
info(i).op === CSROpType.ecall && mode === ModeU && info(i).fusel === FuType.csr info(i).op === CSROpType.ecall && mode === ModeU && info(i).fusel === FuType.csr
io.executeStage.inst(i).ex.tval.map(_ := DontCare) io.executeStage.inst(i).ex.tval.map(_ := DontCare)
io.executeStage.inst(i).ex.tval(instrPageFault) := pc(i) io.executeStage.inst(i).ex.tval(instPageFault) := pc(i)
io.executeStage.inst(i).ex.tval(instrAccessFault) := pc(i) io.executeStage.inst(i).ex.tval(instAccessFault) := pc(i)
io.executeStage.inst(i).ex.tval(illegalInstr) := info(i).inst io.executeStage.inst(i).ex.tval(illegalInst) := info(i).inst
io.executeStage.inst(i).ex.tval(instrAddrMisaligned) := Mux( io.executeStage.inst(i).ex.tval(instAddrMisaligned) := Mux(
io.fetchUnit.target(log2Ceil(INST_WID / 8) - 1, 0).orR && io.fetchUnit.branch, io.fetchUnit.target(log2Ceil(INST_WID / 8) - 1, 0).orR && io.fetchUnit.branch,
io.fetchUnit.target, io.fetchUnit.target,
pc(i) pc(i)

10
chisel/playground/src/pipeline/execute/ExecuteUnit.scala
View File

@ -103,12 +103,12 @@ class ExecuteUnit(implicit val cpuConfig: CpuConfig) extends Module {
) )
) )
) )
io.memoryStage.inst(i).ex.exception(instrAddrMisaligned) := io.memoryStage.inst(i).ex.exception(instAddrMisaligned) :=
io.executeStage.inst(i).ex.exception(instrAddrMisaligned) || io.executeStage.inst(i).ex.exception(instAddrMisaligned) ||
io.fetchUnit.flush && io.fetchUnit.target(log2Ceil(INST_WID / 8) - 1, 0).orR io.fetchUnit.flush && io.fetchUnit.target(log2Ceil(INST_WID / 8) - 1, 0).orR
io.memoryStage.inst(i).ex.tval(instrAddrMisaligned) := Mux( io.memoryStage.inst(i).ex.tval(instAddrMisaligned) := Mux(
io.executeStage.inst(i).ex.exception(instrAddrMisaligned), io.executeStage.inst(i).ex.exception(instAddrMisaligned),
io.executeStage.inst(i).ex.tval(instrAddrMisaligned), io.executeStage.inst(i).ex.tval(instAddrMisaligned),
io.fetchUnit.target io.fetchUnit.target
) )

6
chisel/playground/src/pipeline/execute/fu/Csr.scala
View File

@ -403,9 +403,9 @@ class Csr(implicit val cpuConfig: CpuConfig) extends Module with HasCSRConst {
io.tlb.mstatus := mstatus io.tlb.mstatus := mstatus
io.decodeUnit.mode := mode io.decodeUnit.mode := mode
io.executeUnit.out.ex := io.executeUnit.in.ex io.executeUnit.out.ex := io.executeUnit.in.ex
io.executeUnit.out.ex.exception(illegalInstr) := io.executeUnit.out.ex.exception(illegalInst) :=
(illegal_addr || illegal_access) && write | io.executeUnit.in.ex.exception(illegalInstr) (illegal_addr || illegal_access) && write | io.executeUnit.in.ex.exception(illegalInst)
io.executeUnit.out.ex.tval(illegalInstr) := io.executeUnit.in.info.inst io.executeUnit.out.ex.tval(illegalInst) := io.executeUnit.in.info.inst
io.executeUnit.out.rdata := rdata io.executeUnit.out.rdata := rdata
io.executeUnit.out.flush := write_satp io.executeUnit.out.flush := write_satp
io.executeUnit.out.target := io.executeUnit.in.pc + 4.U io.executeUnit.out.target := io.executeUnit.in.pc + 4.U