From b782293dac9608bfc62d6da0439d583d531e2d6b Mon Sep 17 00:00:00 2001 From: Liphen Date: Mon, 11 Mar 2024 20:03:33 +0800 Subject: [PATCH] =?UTF-8?q?refactor:=20=E4=BF=AE=E6=94=B9=E5=BC=82?= =?UTF-8?q?=E5=B8=B8=E5=8F=98=E9=87=8F=E5=90=8D=E7=A7=B0?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- .../src/defines/isa/Instructions.scala | 16 ++++++++-------- .../src/pipeline/decode/DecodeUnit.scala | 16 ++++++++-------- .../src/pipeline/execute/ExecuteUnit.scala | 10 +++++----- .../playground/src/pipeline/execute/fu/Csr.scala | 6 +++--- 4 files changed, 24 insertions(+), 24 deletions(-) diff --git a/chisel/playground/src/defines/isa/Instructions.scala b/chisel/playground/src/defines/isa/Instructions.scala index 0b08d17..02fcf00 100644 --- a/chisel/playground/src/defines/isa/Instructions.scala +++ b/chisel/playground/src/defines/isa/Instructions.scala @@ -271,9 +271,9 @@ trait HasCSRConst { } trait HasExceptionNO { - def instrAddrMisaligned = 0 - def instrAccessFault = 1 - def illegalInstr = 2 + def instAddrMisaligned = 0 + def instAccessFault = 1 + def illegalInst = 2 def breakPoint = 3 def loadAddrMisaligned = 4 def loadAccessFault = 5 @@ -282,16 +282,16 @@ trait HasExceptionNO { def ecallU = 8 def ecallS = 9 def ecallM = 11 - def instrPageFault = 12 + def instPageFault = 12 def loadPageFault = 13 def storePageFault = 15 val ExcPriority = Seq( breakPoint, // TODO: different BP has different priority - instrPageFault, - instrAccessFault, - illegalInstr, - instrAddrMisaligned, + instPageFault, + instAccessFault, + illegalInst, + instAddrMisaligned, ecallM, ecallS, ecallU, diff --git a/chisel/playground/src/pipeline/decode/DecodeUnit.scala b/chisel/playground/src/pipeline/decode/DecodeUnit.scala index da64b24..daa08c7 100644 --- a/chisel/playground/src/pipeline/decode/DecodeUnit.scala +++ b/chisel/playground/src/pipeline/decode/DecodeUnit.scala @@ -126,10 +126,10 @@ class DecodeUnit(implicit val cpuConfig: CpuConfig) extends Module with HasExcep ) (0 until (INT_WID)).foreach(j => io.executeStage.inst(i).ex.interrupt(j) := io.csr.interrupt(j)) io.executeStage.inst(i).ex.exception.map(_ := false.B) - io.executeStage.inst(i).ex.exception(illegalInstr) := !info(i).inst_legal - io.executeStage.inst(i).ex.exception(instrAccessFault) := io.instFifo.inst(i).access_fault - io.executeStage.inst(i).ex.exception(instrPageFault) := io.instFifo.inst(i).page_fault - io.executeStage.inst(i).ex.exception(instrAddrMisaligned) := io.instFifo.inst(i).addr_misaligned || + io.executeStage.inst(i).ex.exception(illegalInst) := !info(i).inst_legal + io.executeStage.inst(i).ex.exception(instAccessFault) := io.instFifo.inst(i).access_fault + io.executeStage.inst(i).ex.exception(instPageFault) := io.instFifo.inst(i).page_fault + io.executeStage.inst(i).ex.exception(instAddrMisaligned) := io.instFifo.inst(i).addr_misaligned || io.fetchUnit.target(log2Ceil(INST_WID / 8) - 1, 0).orR && io.fetchUnit.branch io.executeStage.inst(i).ex.exception(breakPoint) := info(i).op === CSROpType.ebreak && info(i).fusel === FuType.csr @@ -140,10 +140,10 @@ class DecodeUnit(implicit val cpuConfig: CpuConfig) extends Module with HasExcep io.executeStage.inst(i).ex.exception(ecallU) := info(i).op === CSROpType.ecall && mode === ModeU && info(i).fusel === FuType.csr io.executeStage.inst(i).ex.tval.map(_ := DontCare) - io.executeStage.inst(i).ex.tval(instrPageFault) := pc(i) - io.executeStage.inst(i).ex.tval(instrAccessFault) := pc(i) - io.executeStage.inst(i).ex.tval(illegalInstr) := info(i).inst - io.executeStage.inst(i).ex.tval(instrAddrMisaligned) := Mux( + io.executeStage.inst(i).ex.tval(instPageFault) := pc(i) + io.executeStage.inst(i).ex.tval(instAccessFault) := pc(i) + io.executeStage.inst(i).ex.tval(illegalInst) := info(i).inst + io.executeStage.inst(i).ex.tval(instAddrMisaligned) := Mux( io.fetchUnit.target(log2Ceil(INST_WID / 8) - 1, 0).orR && io.fetchUnit.branch, io.fetchUnit.target, pc(i) diff --git a/chisel/playground/src/pipeline/execute/ExecuteUnit.scala b/chisel/playground/src/pipeline/execute/ExecuteUnit.scala index ac04fab..301c609 100644 --- a/chisel/playground/src/pipeline/execute/ExecuteUnit.scala +++ b/chisel/playground/src/pipeline/execute/ExecuteUnit.scala @@ -103,12 +103,12 @@ class ExecuteUnit(implicit val cpuConfig: CpuConfig) extends Module { ) ) ) - io.memoryStage.inst(i).ex.exception(instrAddrMisaligned) := - io.executeStage.inst(i).ex.exception(instrAddrMisaligned) || + io.memoryStage.inst(i).ex.exception(instAddrMisaligned) := + io.executeStage.inst(i).ex.exception(instAddrMisaligned) || io.fetchUnit.flush && io.fetchUnit.target(log2Ceil(INST_WID / 8) - 1, 0).orR - io.memoryStage.inst(i).ex.tval(instrAddrMisaligned) := Mux( - io.executeStage.inst(i).ex.exception(instrAddrMisaligned), - io.executeStage.inst(i).ex.tval(instrAddrMisaligned), + io.memoryStage.inst(i).ex.tval(instAddrMisaligned) := Mux( + io.executeStage.inst(i).ex.exception(instAddrMisaligned), + io.executeStage.inst(i).ex.tval(instAddrMisaligned), io.fetchUnit.target ) diff --git a/chisel/playground/src/pipeline/execute/fu/Csr.scala b/chisel/playground/src/pipeline/execute/fu/Csr.scala index 9f09f78..ffe0a9e 100644 --- a/chisel/playground/src/pipeline/execute/fu/Csr.scala +++ b/chisel/playground/src/pipeline/execute/fu/Csr.scala @@ -403,9 +403,9 @@ class Csr(implicit val cpuConfig: CpuConfig) extends Module with HasCSRConst { io.tlb.mstatus := mstatus io.decodeUnit.mode := mode io.executeUnit.out.ex := io.executeUnit.in.ex - io.executeUnit.out.ex.exception(illegalInstr) := - (illegal_addr || illegal_access) && write | io.executeUnit.in.ex.exception(illegalInstr) - io.executeUnit.out.ex.tval(illegalInstr) := io.executeUnit.in.info.inst + io.executeUnit.out.ex.exception(illegalInst) := + (illegal_addr || illegal_access) && write | io.executeUnit.in.ex.exception(illegalInst) + io.executeUnit.out.ex.tval(illegalInst) := io.executeUnit.in.info.inst io.executeUnit.out.rdata := rdata io.executeUnit.out.flush := write_satp io.executeUnit.out.target := io.executeUnit.in.pc + 4.U