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修改jump ctrl

This commit is contained in:
Liphen 2023-11-19 15:48:37 +08:00
parent 1646a4d75d
commit b509674610
2 changed files with 97 additions and 97 deletions
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116
chisel/playground/src/pipeline/decoder/ForwardCtrl.scala
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@ -1,64 +1,64 @@
// package cpu.pipeline.decoder package cpu.pipeline.decoder
// import chisel3._ import chisel3._
// import chisel3.util._ import chisel3.util._
// import cpu.defines._ import cpu.defines._
// import cpu.defines.Const._ import cpu.defines.Const._
// import cpu.CpuConfig import cpu.CpuConfig
// class ForwardCtrl(implicit val config: CpuConfig) extends Module { class ForwardCtrl(implicit val config: CpuConfig) extends Module {
// val io = IO(new Bundle { val io = IO(new Bundle {
// val in = Input(new Bundle { val in = Input(new Bundle {
// val forward = Vec(config.fuNum, new DataForwardToDecoderUnit()) val forward = Vec(config.fuNum, new DataForwardToDecoderUnit())
// val regfile = Vec(config.decoderNum, new Src12Read()) val regfile = Vec(config.decoderNum, new Src12Read())
// }) })
// val out = Output(new Bundle { val out = Output(new Bundle {
// val inst = Vec(config.decoderNum, new Src12Read()) val inst = Vec(config.decoderNum, new Src12Read())
// }) })
// }) })
// // wb优先度最低 // wb优先度最低
// for (i <- 0 until (config.decoderNum)) { for (i <- 0 until (config.decoderNum)) {
// io.out.inst(i).src1.raddr := DontCare io.out.inst(i).src1.raddr := DontCare
// io.out.inst(i).src2.raddr := DontCare io.out.inst(i).src2.raddr := DontCare
// io.out.inst(i).src1.rdata := io.in.regfile(i).src1.rdata io.out.inst(i).src1.rdata := io.in.regfile(i).src1.rdata
// io.out.inst(i).src2.rdata := io.in.regfile(i).src2.rdata io.out.inst(i).src2.rdata := io.in.regfile(i).src2.rdata
// } }
// // mem优先度中 // mem优先度中
// for (i <- 0 until (config.decoderNum)) { for (i <- 0 until (config.decoderNum)) {
// for (j <- 0 until (config.fuNum)) { for (j <- 0 until (config.fuNum)) {
// when( when(
// io.in.forward(j).mem.wen && io.in.forward(j).mem.wen &&
// io.in.forward(j).mem.waddr === io.in.regfile(i).src1.raddr, io.in.forward(j).mem.waddr === io.in.regfile(i).src1.raddr,
// ) { ) {
// io.out.inst(i).src1.rdata := io.in.forward(j).mem.wdata io.out.inst(i).src1.rdata := io.in.forward(j).mem.wdata
// } }
// when( when(
// io.in.forward(j).mem.wen && io.in.forward(j).mem.wen &&
// io.in.forward(j).mem.waddr === io.in.regfile(i).src2.raddr, io.in.forward(j).mem.waddr === io.in.regfile(i).src2.raddr,
// ) { ) {
// io.out.inst(i).src2.rdata := io.in.forward(j).mem.wdata io.out.inst(i).src2.rdata := io.in.forward(j).mem.wdata
// } }
// } }
// } }
// // exe优先度高 // exe优先度高
// for (i <- 0 until (config.decoderNum)) { for (i <- 0 until (config.decoderNum)) {
// for (j <- 0 until (config.fuNum)) { for (j <- 0 until (config.fuNum)) {
// when( when(
// io.in.forward(j).exe.wen && !io.in.forward(j).mem_wreg && io.in.forward(j).exe.wen && !io.in.forward(j).mem_wreg &&
// io.in.forward(j).exe.waddr === io.in.regfile(i).src1.raddr, io.in.forward(j).exe.waddr === io.in.regfile(i).src1.raddr,
// ) { ) {
// io.out.inst(i).src1.rdata := io.in.forward(j).exe.wdata io.out.inst(i).src1.rdata := io.in.forward(j).exe.wdata
// } }
// when( when(
// io.in.forward(j).exe.wen && !io.in.forward(j).mem_wreg && io.in.forward(j).exe.wen && !io.in.forward(j).mem_wreg &&
// io.in.forward(j).exe.waddr === io.in.regfile(i).src2.raddr, io.in.forward(j).exe.waddr === io.in.regfile(i).src2.raddr,
// ) { ) {
// io.out.inst(i).src2.rdata := io.in.forward(j).exe.wdata io.out.inst(i).src2.rdata := io.in.forward(j).exe.wdata
// } }
// } }
// } }
// } }

78
chisel/playground/src/pipeline/decoder/JumpCtrl.scala
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@ -1,43 +1,43 @@
// package cpu.pipeline.decoder package cpu.pipeline.decoder
// import chisel3._ import chisel3._
// import chisel3.util._ import chisel3.util._
// import cpu.defines._ import cpu.defines._
// import cpu.defines.Const._ import cpu.defines.Const._
// import cpu.CpuConfig import cpu.CpuConfig
// class JumpCtrl(implicit val config: CpuConfig) extends Module { class JumpCtrl(implicit val config: CpuConfig) extends Module {
// val io = IO(new Bundle { val io = IO(new Bundle {
// val in = Input(new Bundle { val in = Input(new Bundle {
// val allow_to_go = Bool() val allow_to_go = Bool()
// val pc = UInt(PC_WID.W) val pc = UInt(PC_WID.W)
// val decoded_inst0 = new InstInfo() val decoded_inst0 = new InstInfo()
// val reg1_data = UInt(DATA_WID.W) val reg1_data = UInt(DATA_WID.W)
// val forward = Vec(config.fuNum, new DataForwardToDecoderUnit()) val forward = Vec(config.fuNum, new DataForwardToDecoderUnit())
// }) })
// val out = Output(new Bundle { val out = Output(new Bundle {
// val jump_inst = Bool() val jump_inst = Bool()
// val jump_register = Bool() val jump_register = Bool()
// val jump = Bool() val jump = Bool()
// val jump_target = UInt(PC_WID.W) val jump_target = UInt(PC_WID.W)
// }) })
// }) })
// val op = io.in.decoded_inst0.op val op = io.in.decoded_inst0.op
// val jump_inst = VecInit(EXE_J, EXE_JAL).contains(op) val jump_inst = VecInit(ALUOpType.jal).contains(op)
// val jump_register_inst = VecInit(EXE_JR, EXE_JALR).contains(op) val jump_register_inst = VecInit(ALUOpType.jalr).contains(op)
// io.out.jump_inst := jump_inst || jump_register_inst io.out.jump_inst := jump_inst || jump_register_inst
// io.out.jump := io.in.allow_to_go && (jump_inst || jump_register_inst && !io.out.jump_register) io.out.jump := io.in.allow_to_go && (jump_inst || jump_register_inst && !io.out.jump_register)
// io.out.jump_register := jump_register_inst && io.out.jump_register := jump_register_inst &&
// ((io.in.forward(0).exe.wen && io.in.decoded_inst0.reg1_raddr === io.in.forward(0).exe.waddr) || ((io.in.forward(0).exe.wen && io.in.decoded_inst0.reg1_raddr === io.in.forward(0).exe.waddr) ||
// (io.in.forward(1).exe.wen && io.in.decoded_inst0.reg1_raddr === io.in.forward(1).exe.waddr) || (io.in.forward(1).exe.wen && io.in.decoded_inst0.reg1_raddr === io.in.forward(1).exe.waddr) ||
// (io.in.forward(0).mem.wen && io.in.decoded_inst0.reg1_raddr === io.in.forward(0).mem.waddr) || (io.in.forward(0).mem.wen && io.in.decoded_inst0.reg1_raddr === io.in.forward(0).mem.waddr) ||
// (io.in.forward(1).mem.wen && io.in.decoded_inst0.reg1_raddr === io.in.forward(1).mem.waddr)) (io.in.forward(1).mem.wen && io.in.decoded_inst0.reg1_raddr === io.in.forward(1).mem.waddr))
// val pc_plus_4 = io.in.pc + 4.U(PC_WID.W) val pc_plus_4 = io.in.pc + 4.U(PC_WID.W)
// io.out.jump_target := Mux( io.out.jump_target := Mux(
// jump_inst, jump_inst,
// Cat(pc_plus_4(31, 28), io.in.decoded_inst0.inst(25, 0), 0.U(2.W)), Cat(pc_plus_4(31, 28), io.in.decoded_inst0.inst(25, 0), 0.U(2.W)),
// io.in.reg1_data, io.in.reg1_data
// ) )
// } }