diff --git a/chisel/playground/src/pipeline/decoder/ForwardCtrl.scala b/chisel/playground/src/pipeline/decoder/ForwardCtrl.scala
index 157757d..364542b 100644
--- a/chisel/playground/src/pipeline/decoder/ForwardCtrl.scala
+++ b/chisel/playground/src/pipeline/decoder/ForwardCtrl.scala
@@ -1,64 +1,64 @@
-// package cpu.pipeline.decoder
+package cpu.pipeline.decoder
 
-// import chisel3._
-// import chisel3.util._
+import chisel3._
+import chisel3.util._
 
-// import cpu.defines._
-// import cpu.defines.Const._
-// import cpu.CpuConfig
+import cpu.defines._
+import cpu.defines.Const._
+import cpu.CpuConfig
 
-// class ForwardCtrl(implicit val config: CpuConfig) extends Module {
-//   val io = IO(new Bundle {
-//     val in = Input(new Bundle {
-//       val forward = Vec(config.fuNum, new DataForwardToDecoderUnit())
-//       val regfile = Vec(config.decoderNum, new Src12Read())
-//     })
-//     val out = Output(new Bundle {
-//       val inst = Vec(config.decoderNum, new Src12Read())
-//     })
-//   })
+class ForwardCtrl(implicit val config: CpuConfig) extends Module {
+  val io = IO(new Bundle {
+    val in = Input(new Bundle {
+      val forward = Vec(config.fuNum, new DataForwardToDecoderUnit())
+      val regfile = Vec(config.decoderNum, new Src12Read())
+    })
+    val out = Output(new Bundle {
+      val inst = Vec(config.decoderNum, new Src12Read())
+    })
+  })
 
-//   // wb优先度最低
-//   for (i <- 0 until (config.decoderNum)) {
-//     io.out.inst(i).src1.raddr := DontCare
-//     io.out.inst(i).src2.raddr := DontCare
-//     io.out.inst(i).src1.rdata := io.in.regfile(i).src1.rdata
-//     io.out.inst(i).src2.rdata := io.in.regfile(i).src2.rdata
-//   }
+  // wb优先度最低
+  for (i <- 0 until (config.decoderNum)) {
+    io.out.inst(i).src1.raddr := DontCare
+    io.out.inst(i).src2.raddr := DontCare
+    io.out.inst(i).src1.rdata := io.in.regfile(i).src1.rdata
+    io.out.inst(i).src2.rdata := io.in.regfile(i).src2.rdata
+  }
 
-//   // mem优先度中
-//   for (i <- 0 until (config.decoderNum)) {
-//     for (j <- 0 until (config.fuNum)) {
-//       when(
-//         io.in.forward(j).mem.wen &&
-//           io.in.forward(j).mem.waddr === io.in.regfile(i).src1.raddr,
-//       ) {
-//         io.out.inst(i).src1.rdata := io.in.forward(j).mem.wdata
-//       }
-//       when(
-//         io.in.forward(j).mem.wen &&
-//           io.in.forward(j).mem.waddr === io.in.regfile(i).src2.raddr,
-//       ) {
-//         io.out.inst(i).src2.rdata := io.in.forward(j).mem.wdata
-//       }
-//     }
-//   }
+  // mem优先度中
+  for (i <- 0 until (config.decoderNum)) {
+    for (j <- 0 until (config.fuNum)) {
+      when(
+        io.in.forward(j).mem.wen &&
+          io.in.forward(j).mem.waddr === io.in.regfile(i).src1.raddr,
+      ) {
+        io.out.inst(i).src1.rdata := io.in.forward(j).mem.wdata
+      }
+      when(
+        io.in.forward(j).mem.wen &&
+          io.in.forward(j).mem.waddr === io.in.regfile(i).src2.raddr,
+      ) {
+        io.out.inst(i).src2.rdata := io.in.forward(j).mem.wdata
+      }
+    }
+  }
 
-//   // exe优先度高
-//   for (i <- 0 until (config.decoderNum)) {
-//     for (j <- 0 until (config.fuNum)) {
-//       when(
-//         io.in.forward(j).exe.wen && !io.in.forward(j).mem_wreg &&
-//           io.in.forward(j).exe.waddr === io.in.regfile(i).src1.raddr,
-//       ) {
-//         io.out.inst(i).src1.rdata := io.in.forward(j).exe.wdata
-//       }
-//       when(
-//         io.in.forward(j).exe.wen && !io.in.forward(j).mem_wreg &&
-//           io.in.forward(j).exe.waddr === io.in.regfile(i).src2.raddr,
-//       ) {
-//         io.out.inst(i).src2.rdata := io.in.forward(j).exe.wdata
-//       }
-//     }
-//   }
-// }
+  // exe优先度高
+  for (i <- 0 until (config.decoderNum)) {
+    for (j <- 0 until (config.fuNum)) {
+      when(
+        io.in.forward(j).exe.wen && !io.in.forward(j).mem_wreg &&
+          io.in.forward(j).exe.waddr === io.in.regfile(i).src1.raddr,
+      ) {
+        io.out.inst(i).src1.rdata := io.in.forward(j).exe.wdata
+      }
+      when(
+        io.in.forward(j).exe.wen && !io.in.forward(j).mem_wreg &&
+          io.in.forward(j).exe.waddr === io.in.regfile(i).src2.raddr,
+      ) {
+        io.out.inst(i).src2.rdata := io.in.forward(j).exe.wdata
+      }
+    }
+  }
+}
diff --git a/chisel/playground/src/pipeline/decoder/JumpCtrl.scala b/chisel/playground/src/pipeline/decoder/JumpCtrl.scala
index 9f914c2..fe3c1db 100644
--- a/chisel/playground/src/pipeline/decoder/JumpCtrl.scala
+++ b/chisel/playground/src/pipeline/decoder/JumpCtrl.scala
@@ -1,43 +1,43 @@
-// package cpu.pipeline.decoder
+package cpu.pipeline.decoder
 
-// import chisel3._
-// import chisel3.util._
+import chisel3._
+import chisel3.util._
 
-// import cpu.defines._
-// import cpu.defines.Const._
-// import cpu.CpuConfig
+import cpu.defines._
+import cpu.defines.Const._
+import cpu.CpuConfig
 
-// class JumpCtrl(implicit val config: CpuConfig) extends Module {
-//   val io = IO(new Bundle {
-//     val in = Input(new Bundle {
-//       val allow_to_go   = Bool()
-//       val pc            = UInt(PC_WID.W)
-//       val decoded_inst0 = new InstInfo()
-//       val reg1_data     = UInt(DATA_WID.W)
-//       val forward       = Vec(config.fuNum, new DataForwardToDecoderUnit())
-//     })
-//     val out = Output(new Bundle {
-//       val jump_inst     = Bool()
-//       val jump_register = Bool()
-//       val jump          = Bool()
-//       val jump_target   = UInt(PC_WID.W)
-//     })
-//   })
+class JumpCtrl(implicit val config: CpuConfig) extends Module {
+  val io = IO(new Bundle {
+    val in = Input(new Bundle {
+      val allow_to_go   = Bool()
+      val pc            = UInt(PC_WID.W)
+      val decoded_inst0 = new InstInfo()
+      val reg1_data     = UInt(DATA_WID.W)
+      val forward       = Vec(config.fuNum, new DataForwardToDecoderUnit())
+    })
+    val out = Output(new Bundle {
+      val jump_inst     = Bool()
+      val jump_register = Bool()
+      val jump          = Bool()
+      val jump_target   = UInt(PC_WID.W)
+    })
+  })
 
-//   val op                 = io.in.decoded_inst0.op
-//   val jump_inst          = VecInit(EXE_J, EXE_JAL).contains(op)
-//   val jump_register_inst = VecInit(EXE_JR, EXE_JALR).contains(op)
-//   io.out.jump_inst := jump_inst || jump_register_inst
-//   io.out.jump      := io.in.allow_to_go && (jump_inst || jump_register_inst && !io.out.jump_register)
-//   io.out.jump_register := jump_register_inst &&
-//     ((io.in.forward(0).exe.wen && io.in.decoded_inst0.reg1_raddr === io.in.forward(0).exe.waddr) ||
-//       (io.in.forward(1).exe.wen && io.in.decoded_inst0.reg1_raddr === io.in.forward(1).exe.waddr) ||
-//       (io.in.forward(0).mem.wen && io.in.decoded_inst0.reg1_raddr === io.in.forward(0).mem.waddr) ||
-//       (io.in.forward(1).mem.wen && io.in.decoded_inst0.reg1_raddr === io.in.forward(1).mem.waddr))
-//   val pc_plus_4 = io.in.pc + 4.U(PC_WID.W)
-//   io.out.jump_target := Mux(
-//     jump_inst,
-//     Cat(pc_plus_4(31, 28), io.in.decoded_inst0.inst(25, 0), 0.U(2.W)),
-//     io.in.reg1_data,
-//   )
-// }
+  val op                 = io.in.decoded_inst0.op
+  val jump_inst          = VecInit(ALUOpType.jal).contains(op)
+  val jump_register_inst = VecInit(ALUOpType.jalr).contains(op)
+  io.out.jump_inst := jump_inst || jump_register_inst
+  io.out.jump      := io.in.allow_to_go && (jump_inst || jump_register_inst && !io.out.jump_register)
+  io.out.jump_register := jump_register_inst &&
+    ((io.in.forward(0).exe.wen && io.in.decoded_inst0.reg1_raddr === io.in.forward(0).exe.waddr) ||
+      (io.in.forward(1).exe.wen && io.in.decoded_inst0.reg1_raddr === io.in.forward(1).exe.waddr) ||
+      (io.in.forward(0).mem.wen && io.in.decoded_inst0.reg1_raddr === io.in.forward(0).mem.waddr) ||
+      (io.in.forward(1).mem.wen && io.in.decoded_inst0.reg1_raddr === io.in.forward(1).mem.waddr))
+  val pc_plus_4 = io.in.pc + 4.U(PC_WID.W)
+  io.out.jump_target := Mux(
+    jump_inst,
+    Cat(pc_plus_4(31, 28), io.in.decoded_inst0.inst(25, 0), 0.U(2.W)),
+    io.in.reg1_data
+  )
+}