修改issue unit
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Liphen
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8cc7e38b8b
commit
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@ -26,11 +26,11 @@ object SrcType {
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object FuType {
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def num = 5
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def alu = "b000".U
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def lsu = "b001".U
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def mdu = "b010".U
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def csr = "b011".U
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def mou = "b100".U
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def alu = "b000".U // arithmetic logic unit
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def lsu = "b001".U // load store unit
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def mdu = "b010".U // mul div unit
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def csr = "b011".U // control status register
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def mou = "b100".U // memory order unit
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def bru = alu
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def apply() = UInt(log2Up(num).W)
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}
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@ -1,59 +1,57 @@
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// package cpu.pipeline.decoder
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package cpu.pipeline.decoder
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// import chisel3._
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// import chisel3.util._
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// import cpu.defines._
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// import cpu.defines.Const._
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// import cpu.CpuConfig
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import chisel3._
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import chisel3.util._
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import cpu.defines._
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import cpu.defines.Const._
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import cpu.defines.Instructions._
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import cpu.CpuConfig
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// class Issue(implicit val config: CpuConfig) extends Module {
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// val io = IO(new Bundle {
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// // 输入
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// val allow_to_go = Input(Bool())
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// val instFifo = Input(new Bundle {
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// val empty = Bool()
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// val almost_empty = Bool()
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// })
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// val decodeInst = Input(Vec(config.decoderNum, new InstInfo()))
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// val execute = Input(Vec(config.fuNum, new MemRead()))
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// // 输出
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// val inst1 = Output(new Bundle {
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// val allow_to_go = Bool()
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// })
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// })
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class Issue(implicit val config: CpuConfig) extends Module {
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val io = IO(new Bundle {
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// 输入
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val allow_to_go = Input(Bool())
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val instFifo = Input(new Bundle {
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val empty = Bool()
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val almost_empty = Bool()
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})
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val decodeInst = Input(Vec(config.decoderNum, new InstInfo()))
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val execute = Input(Vec(config.fuNum, new MemRead()))
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// 输出
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val inst1 = Output(new Bundle {
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val allow_to_go = Bool()
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})
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})
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// val inst0 = io.decodeInst(0)
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// val inst1 = io.decodeInst(1)
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val inst0 = io.decodeInst(0)
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val inst1 = io.decodeInst(1)
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// // inst buffer是否存有至少2条指令
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// val instFifo_invalid = io.instFifo.empty || io.instFifo.almost_empty
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// inst buffer是否存有至少2条指令
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val instFifo_invalid = io.instFifo.empty || io.instFifo.almost_empty
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// // 结构冲突
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// val mem_conflict = inst0.fusel === FU_MEM && inst1.fusel === FU_MEM
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// val mul_conflict = inst0.fusel === FU_MUL && inst1.fusel === FU_MUL
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// val div_conflict = inst0.fusel === FU_DIV && inst1.fusel === FU_DIV
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// val struct_conflict = mem_conflict || mul_conflict || div_conflict
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// 结构冲突
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val mem_conflict = inst0.fusel === FuType.lsu && inst1.fusel === FuType.lsu
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val mul_conflict = inst0.fusel === FuType.mdu && inst1.fusel === FuType.mdu
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val div_conflict = inst0.fusel === FuType.mdu && inst1.fusel === FuType.mdu
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val csr_conflict = inst0.fusel === FuType.csr && inst1.fusel === FuType.csr
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val struct_conflict = mem_conflict || mul_conflict || div_conflict || csr_conflict
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// // 写后读冲突
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// val load_stall =
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// io.execute(0).mem_wreg && (inst1.reg1_ren && inst1.reg1_raddr === io.execute(0).reg_waddr ||
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// inst1.reg2_ren && inst1.reg2_raddr === io.execute(0).reg_waddr) ||
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// io.execute(1).mem_wreg && (inst1.reg1_ren && inst1.reg1_raddr === io.execute(1).reg_waddr ||
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// inst1.reg2_ren && inst1.reg2_raddr === io.execute(1).reg_waddr)
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// val raw_reg =
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// inst0.reg_wen && (inst0.reg_waddr === inst1.reg1_raddr && inst1.reg1_ren || inst0.reg_waddr === inst1.reg2_raddr && inst1.reg2_ren)
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// val raw_hilo = VecInit(FU_DIV, FU_MUL, FU_MTHILO).contains(inst0.fusel) &&
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// VecInit(FU_DIV, FU_MUL, FU_MFHILO, FU_MTHILO).contains(inst1.fusel)
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// val raw_csr =
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// inst0.op === EXE_MTC0 && inst1.op === EXE_MFC0 && inst0.csr_addr === inst1.csr_addr
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// val data_conflict = raw_reg || raw_hilo || raw_csr || load_stall
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// 写后读冲突
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val load_stall =
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io.execute(0).mem_wreg && (inst1.reg1_ren && inst1.reg1_raddr === io.execute(0).reg_waddr ||
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inst1.reg2_ren && inst1.reg2_raddr === io.execute(0).reg_waddr) ||
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io.execute(1).mem_wreg && (inst1.reg1_ren && inst1.reg1_raddr === io.execute(1).reg_waddr ||
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inst1.reg2_ren && inst1.reg2_raddr === io.execute(1).reg_waddr)
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val raw_reg =
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inst0.reg_wen && (inst0.reg_waddr === inst1.reg1_raddr && inst1.reg1_ren || inst0.reg_waddr === inst1.reg2_raddr && inst1.reg2_ren)
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val data_conflict = raw_reg || load_stall
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// // 指令1是否允许执行
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// io.inst1.allow_to_go := io.allow_to_go &&
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// !instFifo_invalid &&
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// inst0.dual_issue &&
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// inst1.dual_issue &&
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// !struct_conflict &&
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// !data_conflict &&
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// !VecInit(FU_BR, FU_EX).contains(io.decodeInst(1).fusel)
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// }
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// 指令1是否允许执行
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io.inst1.allow_to_go := io.allow_to_go &&
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!instFifo_invalid &&
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inst0.dual_issue &&
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inst1.dual_issue &&
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!struct_conflict &&
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!data_conflict &&
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!VecInit(FuType.bru, FuType.mou).contains(io.decodeInst(1).fusel)
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}
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