From 1646a4d75d660b12e682523d67dc64e05e998845 Mon Sep 17 00:00:00 2001 From: Liphen Date: Sun, 19 Nov 2023 15:34:14 +0800 Subject: [PATCH] =?UTF-8?q?=E4=BF=AE=E6=94=B9issue=20unit?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- .../src/defines/isa/Instructions.scala | 10 +- .../src/pipeline/decoder/Issue.scala | 102 +++++++++--------- 2 files changed, 55 insertions(+), 57 deletions(-) diff --git a/chisel/playground/src/defines/isa/Instructions.scala b/chisel/playground/src/defines/isa/Instructions.scala index cd67d06..88c7a55 100644 --- a/chisel/playground/src/defines/isa/Instructions.scala +++ b/chisel/playground/src/defines/isa/Instructions.scala @@ -26,11 +26,11 @@ object SrcType { object FuType { def num = 5 - def alu = "b000".U - def lsu = "b001".U - def mdu = "b010".U - def csr = "b011".U - def mou = "b100".U + def alu = "b000".U // arithmetic logic unit + def lsu = "b001".U // load store unit + def mdu = "b010".U // mul div unit + def csr = "b011".U // control status register + def mou = "b100".U // memory order unit def bru = alu def apply() = UInt(log2Up(num).W) } diff --git a/chisel/playground/src/pipeline/decoder/Issue.scala b/chisel/playground/src/pipeline/decoder/Issue.scala index cf1b80e..6c8eee5 100644 --- a/chisel/playground/src/pipeline/decoder/Issue.scala +++ b/chisel/playground/src/pipeline/decoder/Issue.scala @@ -1,59 +1,57 @@ -// package cpu.pipeline.decoder +package cpu.pipeline.decoder -// import chisel3._ -// import chisel3.util._ -// import cpu.defines._ -// import cpu.defines.Const._ -// import cpu.CpuConfig +import chisel3._ +import chisel3.util._ +import cpu.defines._ +import cpu.defines.Const._ +import cpu.defines.Instructions._ +import cpu.CpuConfig -// class Issue(implicit val config: CpuConfig) extends Module { -// val io = IO(new Bundle { -// // 输入 -// val allow_to_go = Input(Bool()) -// val instFifo = Input(new Bundle { -// val empty = Bool() -// val almost_empty = Bool() -// }) -// val decodeInst = Input(Vec(config.decoderNum, new InstInfo())) -// val execute = Input(Vec(config.fuNum, new MemRead())) -// // 输出 -// val inst1 = Output(new Bundle { -// val allow_to_go = Bool() -// }) -// }) +class Issue(implicit val config: CpuConfig) extends Module { + val io = IO(new Bundle { + // 输入 + val allow_to_go = Input(Bool()) + val instFifo = Input(new Bundle { + val empty = Bool() + val almost_empty = Bool() + }) + val decodeInst = Input(Vec(config.decoderNum, new InstInfo())) + val execute = Input(Vec(config.fuNum, new MemRead())) + // 输出 + val inst1 = Output(new Bundle { + val allow_to_go = Bool() + }) + }) -// val inst0 = io.decodeInst(0) -// val inst1 = io.decodeInst(1) + val inst0 = io.decodeInst(0) + val inst1 = io.decodeInst(1) -// // inst buffer是否存有至少2条指令 -// val instFifo_invalid = io.instFifo.empty || io.instFifo.almost_empty + // inst buffer是否存有至少2条指令 + val instFifo_invalid = io.instFifo.empty || io.instFifo.almost_empty -// // 结构冲突 -// val mem_conflict = inst0.fusel === FU_MEM && inst1.fusel === FU_MEM -// val mul_conflict = inst0.fusel === FU_MUL && inst1.fusel === FU_MUL -// val div_conflict = inst0.fusel === FU_DIV && inst1.fusel === FU_DIV -// val struct_conflict = mem_conflict || mul_conflict || div_conflict + // 结构冲突 + val mem_conflict = inst0.fusel === FuType.lsu && inst1.fusel === FuType.lsu + val mul_conflict = inst0.fusel === FuType.mdu && inst1.fusel === FuType.mdu + val div_conflict = inst0.fusel === FuType.mdu && inst1.fusel === FuType.mdu + val csr_conflict = inst0.fusel === FuType.csr && inst1.fusel === FuType.csr + val struct_conflict = mem_conflict || mul_conflict || div_conflict || csr_conflict -// // 写后读冲突 -// val load_stall = -// io.execute(0).mem_wreg && (inst1.reg1_ren && inst1.reg1_raddr === io.execute(0).reg_waddr || -// inst1.reg2_ren && inst1.reg2_raddr === io.execute(0).reg_waddr) || -// io.execute(1).mem_wreg && (inst1.reg1_ren && inst1.reg1_raddr === io.execute(1).reg_waddr || -// inst1.reg2_ren && inst1.reg2_raddr === io.execute(1).reg_waddr) -// val raw_reg = -// inst0.reg_wen && (inst0.reg_waddr === inst1.reg1_raddr && inst1.reg1_ren || inst0.reg_waddr === inst1.reg2_raddr && inst1.reg2_ren) -// val raw_hilo = VecInit(FU_DIV, FU_MUL, FU_MTHILO).contains(inst0.fusel) && -// VecInit(FU_DIV, FU_MUL, FU_MFHILO, FU_MTHILO).contains(inst1.fusel) -// val raw_csr = -// inst0.op === EXE_MTC0 && inst1.op === EXE_MFC0 && inst0.csr_addr === inst1.csr_addr -// val data_conflict = raw_reg || raw_hilo || raw_csr || load_stall + // 写后读冲突 + val load_stall = + io.execute(0).mem_wreg && (inst1.reg1_ren && inst1.reg1_raddr === io.execute(0).reg_waddr || + inst1.reg2_ren && inst1.reg2_raddr === io.execute(0).reg_waddr) || + io.execute(1).mem_wreg && (inst1.reg1_ren && inst1.reg1_raddr === io.execute(1).reg_waddr || + inst1.reg2_ren && inst1.reg2_raddr === io.execute(1).reg_waddr) + val raw_reg = + inst0.reg_wen && (inst0.reg_waddr === inst1.reg1_raddr && inst1.reg1_ren || inst0.reg_waddr === inst1.reg2_raddr && inst1.reg2_ren) + val data_conflict = raw_reg || load_stall -// // 指令1是否允许执行 -// io.inst1.allow_to_go := io.allow_to_go && -// !instFifo_invalid && -// inst0.dual_issue && -// inst1.dual_issue && -// !struct_conflict && -// !data_conflict && -// !VecInit(FU_BR, FU_EX).contains(io.decodeInst(1).fusel) -// } + // 指令1是否允许执行 + io.inst1.allow_to_go := io.allow_to_go && + !instFifo_invalid && + inst0.dual_issue && + inst1.dual_issue && + !struct_conflict && + !data_conflict && + !VecInit(FuType.bru, FuType.mou).contains(io.decodeInst(1).fusel) +}