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通过了rv虚存测试，开始进行os测试

This commit is contained in:
Liphen 2024-01-20 16:35:38 +08:00
parent 704d4f7e97
commit 9ac5f99e1f
3 changed files with 5 additions and 5 deletions
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2
chisel/difftest

@ -1 +1 @@
Subproject commit ef0f84099590846759803b50a8fa0cf256470361 Subproject commit 718bf7d977b13729ff0b15a96415f65ac848183e

2
chisel/playground/src/CpuConfig.scala
View File

@ -14,7 +14,7 @@ case class CpuConfig(
val hasSMode: Boolean = true, // 是否有S模式 val hasSMode: Boolean = true, // 是否有S模式
val hasUMode: Boolean = true, // 是否有U模式 val hasUMode: Boolean = true, // 是否有U模式
// 模块配置 // 模块配置
val hasCommitBuffer: Boolean = true, // 是否有提交缓存 val hasCommitBuffer: Boolean = false, // 是否有提交缓存
val decoderNum: Int = 2, // 译码级最大解码的指令数，也是同时访问寄存器的指令数 val decoderNum: Int = 2, // 译码级最大解码的指令数，也是同时访问寄存器的指令数
val commitNum: Int = 2, // 同时提交的指令数, 也是最大发射的指令数 val commitNum: Int = 2, // 同时提交的指令数, 也是最大发射的指令数
val instFetchNum: Int = 2, // iCache取到的指令数量，最大取值为4 val instFetchNum: Int = 2, // iCache取到的指令数量，最大取值为4

6
chisel/playground/src/pipeline/writeback/WriteBackUnit.scala
View File

@ -53,15 +53,15 @@ class WriteBackUnit(implicit val cpuConfig: CpuConfig) extends Module {
clock.asBool, clock.asBool,
io.writeBackStage.inst0.pc, io.writeBackStage.inst0.pc,
Mux( Mux(
HasExcInt(io.writeBackStage.inst0.ex), !(io.writeBackStage.inst1.info.valid && io.ctrl.allow_to_go),
0.U, 0.U,
io.writeBackStage.inst1.pc io.writeBackStage.inst1.pc
) )
) )
io.debug.wb_rf_wen := Mux( io.debug.wb_rf_wen := Mux(
clock.asBool, clock.asBool,
Fill(4, io.regfile(0).wen), io.writeBackStage.inst0.info.valid && io.ctrl.allow_to_go,
Fill(4, io.regfile(1).wen) io.writeBackStage.inst1.info.valid && io.ctrl.allow_to_go
) )
io.debug.wb_rf_wnum := Mux( io.debug.wb_rf_wnum := Mux(
clock.asBool, clock.asBool,