diff --git a/chisel/difftest b/chisel/difftest
index ef0f840..718bf7d 160000
--- a/chisel/difftest
+++ b/chisel/difftest
@@ -1 +1 @@
-Subproject commit ef0f84099590846759803b50a8fa0cf256470361
+Subproject commit 718bf7d977b13729ff0b15a96415f65ac848183e
diff --git a/chisel/playground/src/CpuConfig.scala b/chisel/playground/src/CpuConfig.scala
index d9803d8..36031aa 100644
--- a/chisel/playground/src/CpuConfig.scala
+++ b/chisel/playground/src/CpuConfig.scala
@@ -14,7 +14,7 @@ case class CpuConfig(
   val hasSMode: Boolean = true, // 是否有S模式
   val hasUMode: Boolean = true, // 是否有U模式
   // 模块配置
-  val hasCommitBuffer: Boolean = true, // 是否有提交缓存
+  val hasCommitBuffer: Boolean = false, // 是否有提交缓存
   val decoderNum:      Int     = 2, // 译码级最大解码的指令数，也是同时访问寄存器的指令数
   val commitNum:       Int     = 2, // 同时提交的指令数, 也是最大发射的指令数
   val instFetchNum:    Int     = 2, // iCache取到的指令数量，最大取值为4
diff --git a/chisel/playground/src/pipeline/writeback/WriteBackUnit.scala b/chisel/playground/src/pipeline/writeback/WriteBackUnit.scala
index cb9c73b..1ea56e2 100644
--- a/chisel/playground/src/pipeline/writeback/WriteBackUnit.scala
+++ b/chisel/playground/src/pipeline/writeback/WriteBackUnit.scala
@@ -53,15 +53,15 @@ class WriteBackUnit(implicit val cpuConfig: CpuConfig) extends Module {
       clock.asBool,
       io.writeBackStage.inst0.pc,
       Mux(
-        HasExcInt(io.writeBackStage.inst0.ex),
+        !(io.writeBackStage.inst1.info.valid && io.ctrl.allow_to_go),
         0.U,
         io.writeBackStage.inst1.pc
       )
     )
     io.debug.wb_rf_wen := Mux(
       clock.asBool,
-      Fill(4, io.regfile(0).wen),
-      Fill(4, io.regfile(1).wen)
+      io.writeBackStage.inst0.info.valid && io.ctrl.allow_to_go,
+      io.writeBackStage.inst1.info.valid && io.ctrl.allow_to_go
     )
     io.debug.wb_rf_wnum := Mux(
       clock.asBool,