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fix(fu): lr提前访存地址错误

This commit is contained in:
Liphen 2024-01-20 15:32:40 +08:00
parent efb713dce3
commit 704d4f7e97
1 changed files with 1 additions and 1 deletions
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2
chisel/playground/src/pipeline/execute/Fu.scala
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@ -81,7 +81,7 @@ class Fu(implicit val cpuConfig: CpuConfig) extends Module {
val mem_addr = Seq.tabulate(cpuConfig.commitNum)(i =>
Mux(
LSUOpType.isAMO(io.inst(i).info.op),
LSUOpType.isAMO(io.inst(i).info.op) || LSUOpType.isLR(io.inst(i).info.op),
io.inst(i).src_info.src1_data,
io.inst(i).src_info.src1_data + io.inst(i).info.imm
)