From 704d4f7e97b3602a2cf6b8e493961039fae95635 Mon Sep 17 00:00:00 2001 From: Liphen Date: Sat, 20 Jan 2024 15:32:40 +0800 Subject: [PATCH] =?UTF-8?q?fix(fu):=20lr=E6=8F=90=E5=89=8D=E8=AE=BF?= =?UTF-8?q?=E5=AD=98=E5=9C=B0=E5=9D=80=E9=94=99=E8=AF=AF?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- chisel/playground/src/pipeline/execute/Fu.scala | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/chisel/playground/src/pipeline/execute/Fu.scala b/chisel/playground/src/pipeline/execute/Fu.scala index 7e212e1..91eb375 100644 --- a/chisel/playground/src/pipeline/execute/Fu.scala +++ b/chisel/playground/src/pipeline/execute/Fu.scala @@ -81,7 +81,7 @@ class Fu(implicit val cpuConfig: CpuConfig) extends Module { val mem_addr = Seq.tabulate(cpuConfig.commitNum)(i => Mux( - LSUOpType.isAMO(io.inst(i).info.op), + LSUOpType.isAMO(io.inst(i).info.op) || LSUOpType.isLR(io.inst(i).info.op), io.inst(i).src_info.src1_data, io.inst(i).src_info.src1_data + io.inst(i).info.imm )