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fix: Fix FetchUnit PC initialization issue

This commit is contained in:
Liphen 2024-05-08 13:04:57 +08:00
parent 59dc2337cb
commit 9862402688
2 changed files with 2 additions and 2 deletions
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2
chisel/playground/src/pipeline/fetch/FetchUnit.scala
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@ -13,7 +13,7 @@ class FetchUnit extends Module {
val instSram = new InstSram() val instSram = new InstSram()
}) })
val pc = RegNext(io.instSram.addr, (PC_INIT - 4.U)) val pc = RegEnable(io.instSram.addr, (PC_INIT - 4.U), io.decodeStage.data.valid)
io.instSram.addr := MuxCase( io.instSram.addr := MuxCase(
pc + 4.U, pc + 4.U,

2
difftest

@ -1 +1 @@
Subproject commit 2207e5e02ef77abe5d48fdf8ec2174107cc05c1d Subproject commit 8fb9d90b00e02be2baa7536ffa43fe0a6d6dc7f6