35 lines
957 B
Scala
35 lines
957 B
Scala
package cpu.pipeline
|
|
|
|
import chisel3._
|
|
import chisel3.util._
|
|
import cpu.defines.Const._
|
|
import cpu.CpuConfig
|
|
import cpu.defines._
|
|
|
|
class FetchUnit extends Module {
|
|
val io = IO(new Bundle {
|
|
val ctrl = new FetchUnitCtrl()
|
|
val decodeStage = new FetchUnitDecodeUnit()
|
|
val instSram = new InstSram()
|
|
})
|
|
|
|
val pc = RegEnable(io.instSram.addr, (PC_INIT - 4.U), io.decodeStage.data.valid)
|
|
|
|
io.instSram.addr := MuxCase(
|
|
pc + 4.U,
|
|
Seq(
|
|
io.ctrl.ctrlSignal.do_flush -> io.ctrl.target,
|
|
!io.ctrl.ctrlSignal.allow_to_go -> pc
|
|
)
|
|
)
|
|
|
|
io.decodeStage.data.valid := RegNext(!reset.asBool, false.B) & !reset.asBool
|
|
io.decodeStage.data.pc := pc
|
|
io.decodeStage.data.inst := io.instSram.rdata
|
|
io.decodeStage.data.addr_misaligned := pc(1, 0) =/= 0.U
|
|
|
|
io.instSram.en := !reset.asBool & !io.decodeStage.data.addr_misaligned
|
|
io.instSram.wen := 0.U
|
|
io.instSram.wdata := 0.U
|
|
}
|