diff --git a/chisel/playground/src/pipeline/fetch/FetchUnit.scala b/chisel/playground/src/pipeline/fetch/FetchUnit.scala
index 916dc34..86f88c0 100644
--- a/chisel/playground/src/pipeline/fetch/FetchUnit.scala
+++ b/chisel/playground/src/pipeline/fetch/FetchUnit.scala
@@ -13,7 +13,7 @@ class FetchUnit extends Module {
     val instSram    = new InstSram()
   })
 
-  val pc = RegNext(io.instSram.addr, (PC_INIT - 4.U))
+  val pc = RegEnable(io.instSram.addr, (PC_INIT - 4.U), io.decodeStage.data.valid)
 
   io.instSram.addr := MuxCase(
     pc + 4.U,
diff --git a/difftest b/difftest
index 2207e5e..8fb9d90 160000
--- a/difftest
+++ b/difftest
@@ -1 +1 @@
-Subproject commit 2207e5e02ef77abe5d48fdf8ec2174107cc05c1d
+Subproject commit 8fb9d90b00e02be2baa7536ffa43fe0a6d6dc7f6