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fix: 修复了不能生成代码的问题

This commit is contained in:
Liphen 2023-11-07 18:42:06 +08:00
parent 3c7beb03c6
commit 976f0e1a02
2 changed files with 9 additions and 4 deletions
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2
chisel/build.sc
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@ -7,7 +7,7 @@ import mill.scalalib.TestModule.ScalaTest
import mill.bsp._ import mill.bsp._
object playground extends ScalaModule with ScalafmtModule { m => object playground extends ScalaModule with ScalafmtModule { m =>
val useChisel5 = true val useChisel5 = false
override def scalaVersion = "2.13.10" override def scalaVersion = "2.13.10"
override def scalacOptions = Seq( override def scalacOptions = Seq(
"-language:reflectiveCalls", "-language:reflectiveCalls",

11
chisel/playground/src/Elaborate.scala
View File

@ -3,7 +3,12 @@ import circt.stage._
object Elaborate extends App { object Elaborate extends App {
implicit val config = new CpuConfig() implicit val config = new CpuConfig()
def top = new PuaMips() def top = new PuaMips()
val generator = Seq(chisel3.stage.ChiselGeneratorAnnotation(() => top)) val useMFC = false // use MLIR-based firrtl compiler
(new ChiselStage).execute(args, generator :+ CIRCTTargetAnnotation(CIRCTTarget.Verilog)) val generator = Seq(chisel3.stage.ChiselGeneratorAnnotation(() => top))
if (useMFC) {
(new ChiselStage).execute(args, generator :+ CIRCTTargetAnnotation(CIRCTTarget.Verilog))
} else {
(new chisel3.stage.ChiselStage).execute(args, generator)
}
} }