From 976f0e1a02ef7d94cf5494e5ecffd25144cb92a7 Mon Sep 17 00:00:00 2001 From: Liphen Date: Tue, 7 Nov 2023 18:42:06 +0800 Subject: [PATCH] =?UTF-8?q?fix:=20=E4=BF=AE=E5=A4=8D=E4=BA=86=E4=B8=8D?= =?UTF-8?q?=E8=83=BD=E7=94=9F=E6=88=90=E4=BB=A3=E7=A0=81=E7=9A=84=E9=97=AE?= =?UTF-8?q?=E9=A2=98?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- chisel/build.sc | 2 +- chisel/playground/src/Elaborate.scala | 11 ++++++++--- 2 files changed, 9 insertions(+), 4 deletions(-) diff --git a/chisel/build.sc b/chisel/build.sc index 2768db8..548f0b0 100644 --- a/chisel/build.sc +++ b/chisel/build.sc @@ -7,7 +7,7 @@ import mill.scalalib.TestModule.ScalaTest import mill.bsp._ object playground extends ScalaModule with ScalafmtModule { m => - val useChisel5 = true + val useChisel5 = false override def scalaVersion = "2.13.10" override def scalacOptions = Seq( "-language:reflectiveCalls", diff --git a/chisel/playground/src/Elaborate.scala b/chisel/playground/src/Elaborate.scala index 8a52b9c..533da1e 100644 --- a/chisel/playground/src/Elaborate.scala +++ b/chisel/playground/src/Elaborate.scala @@ -3,7 +3,12 @@ import circt.stage._ object Elaborate extends App { implicit val config = new CpuConfig() - def top = new PuaMips() - val generator = Seq(chisel3.stage.ChiselGeneratorAnnotation(() => top)) - (new ChiselStage).execute(args, generator :+ CIRCTTargetAnnotation(CIRCTTarget.Verilog)) + def top = new PuaMips() + val useMFC = false // use MLIR-based firrtl compiler + val generator = Seq(chisel3.stage.ChiselGeneratorAnnotation(() => top)) + if (useMFC) { + (new ChiselStage).execute(args, generator :+ CIRCTTargetAnnotation(CIRCTTarget.Verilog)) + } else { + (new chisel3.stage.ChiselStage).execute(args, generator) + } }