diff --git a/chisel/build.sc b/chisel/build.sc
index 2768db8..548f0b0 100644
--- a/chisel/build.sc
+++ b/chisel/build.sc
@@ -7,7 +7,7 @@ import mill.scalalib.TestModule.ScalaTest
 import mill.bsp._
 
 object playground extends ScalaModule with ScalafmtModule { m =>
-  val useChisel5 = true
+  val useChisel5 = false
   override def scalaVersion = "2.13.10"
   override def scalacOptions = Seq(
     "-language:reflectiveCalls",
diff --git a/chisel/playground/src/Elaborate.scala b/chisel/playground/src/Elaborate.scala
index 8a52b9c..533da1e 100644
--- a/chisel/playground/src/Elaborate.scala
+++ b/chisel/playground/src/Elaborate.scala
@@ -3,7 +3,12 @@ import circt.stage._
 
 object Elaborate extends App {
   implicit val config = new CpuConfig()
-  def top = new PuaMips()
-  val generator = Seq(chisel3.stage.ChiselGeneratorAnnotation(() => top))
-  (new ChiselStage).execute(args, generator :+ CIRCTTargetAnnotation(CIRCTTarget.Verilog))
+  def top             = new PuaMips()
+  val useMFC          = false // use MLIR-based firrtl compiler
+  val generator       = Seq(chisel3.stage.ChiselGeneratorAnnotation(() => top))
+  if (useMFC) {
+    (new ChiselStage).execute(args, generator :+ CIRCTTargetAnnotation(CIRCTTarget.Verilog))
+  } else {
+    (new chisel3.stage.ChiselStage).execute(args, generator)
+  }
 }