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删除addr_err

This commit is contained in:
Liphen 2023-12-01 14:14:14 +08:00
parent 55b5cc7907
commit 8a3e85b201
4 changed files with 0 additions and 4 deletions
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1
chisel/playground/src/Core.scala
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@ -82,7 +82,6 @@ class Core(implicit val config: CpuConfig) extends Module {
instFifo.write(i).pc := io.inst.addr(0) + (i * 4).U instFifo.write(i).pc := io.inst.addr(0) + (i * 4).U
instFifo.write(i).inst := io.inst.inst(i) instFifo.write(i).inst := io.inst.inst(i)
instFifo.write(i).acc_err := io.inst.acc_err instFifo.write(i).acc_err := io.inst.acc_err
instFifo.write(i).addr_err := io.inst.addr_err
} }
decoderUnit.instFifo.info.empty := instFifo.empty decoderUnit.instFifo.info.empty := instFifo.empty

1
chisel/playground/src/cache/ICache.scala vendored
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@ -48,7 +48,6 @@ class ICache(implicit config: CpuConfig) extends Module {
io.cpu.inst_valid(i) := Mux(status === s_idle && !acc_err, false.B, saved(i).valid) && io.cpu.req io.cpu.inst_valid(i) := Mux(status === s_idle && !acc_err, false.B, saved(i).valid) && io.cpu.req
}) })
io.cpu.addr_err := addr_err
io.cpu.acc_err := acc_err io.cpu.acc_err := acc_err
io.cpu.icache_stall := Mux(status === s_idle && !acc_err, io.cpu.req, status =/= s_save) io.cpu.icache_stall := Mux(status === s_idle && !acc_err, io.cpu.req, status =/= s_save)

1
chisel/playground/src/defines/Bundles.scala
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@ -117,7 +117,6 @@ class Cache_ICache(implicit val config: CpuConfig) extends Bundle {
val inst = Input(Vec(config.instFetchNum, UInt(INST_WID.W))) val inst = Input(Vec(config.instFetchNum, UInt(INST_WID.W)))
val inst_valid = Input(Vec(config.instFetchNum, Bool())) val inst_valid = Input(Vec(config.instFetchNum, Bool()))
val acc_err = Input(Bool()) val acc_err = Input(Bool())
val addr_err = Input(Bool())
val icache_stall = Input(Bool()) // icache_stall val icache_stall = Input(Bool()) // icache_stall
} }

1
chisel/playground/src/pipeline/fetch/InstFifo.scala
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@ -10,7 +10,6 @@ class BufferUnit extends Bundle {
val inst = UInt(INST_WID.W) val inst = UInt(INST_WID.W)
val pht_index = UInt(bpuConfig.phtDepth.W) val pht_index = UInt(bpuConfig.phtDepth.W)
val acc_err = Bool() val acc_err = Bool()
val addr_err = Bool()
val pc = UInt(PC_WID.W) val pc = UInt(PC_WID.W)
} }