yystopf
/
riscv-lab
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

fix(ExeAccessMem): 例外信号逻辑错误

This commit is contained in:
Liphen 2023-12-01 13:44:47 +08:00
parent efc80cf223
commit 55b5cc7907
1 changed files with 2 additions and 2 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
chisel/playground/src/pipeline/execute/ExeAccessMemCtrl.scala
View File

@ -76,8 +76,8 @@ class ExeAccessMemCtrl(implicit val config: CpuConfig) extends Module {
for (i <- 0 until config.fuNum) {
val store_inst = LSUOpType.isStore(io.inst(i).info.op)
io.inst(i).ex.out := io.inst(i).ex.in
io.inst(i).ex.out.exception(loadAddrMisaligned) := store_inst && !addr_aligned(i)
io.inst(i).ex.out.exception(storeAddrMisaligned) := !store_inst && !addr_aligned(i)
io.inst(i).ex.out.exception(loadAddrMisaligned) := !store_inst && !addr_aligned(i)
io.inst(i).ex.out.exception(storeAddrMisaligned) := store_inst && !addr_aligned(i)
}
io.inst(0).mem_sel := (io.inst(0).info.fusel === FuType.lsu) &&
!(io.inst(0).ex.out.exception.asUInt.orR || io.inst(0).ex.out.interrupt.asUInt.orR) &&