diff --git a/chisel/playground/src/pipeline/execute/ExeAccessMemCtrl.scala b/chisel/playground/src/pipeline/execute/ExeAccessMemCtrl.scala
index d96b7be..8e576db 100644
--- a/chisel/playground/src/pipeline/execute/ExeAccessMemCtrl.scala
+++ b/chisel/playground/src/pipeline/execute/ExeAccessMemCtrl.scala
@@ -76,8 +76,8 @@ class ExeAccessMemCtrl(implicit val config: CpuConfig) extends Module {
   for (i <- 0 until config.fuNum) {
     val store_inst = LSUOpType.isStore(io.inst(i).info.op)
     io.inst(i).ex.out                                := io.inst(i).ex.in
-    io.inst(i).ex.out.exception(loadAddrMisaligned)  := store_inst && !addr_aligned(i)
-    io.inst(i).ex.out.exception(storeAddrMisaligned) := !store_inst && !addr_aligned(i)
+    io.inst(i).ex.out.exception(loadAddrMisaligned)  := !store_inst && !addr_aligned(i)
+    io.inst(i).ex.out.exception(storeAddrMisaligned) := store_inst && !addr_aligned(i)
   }
   io.inst(0).mem_sel := (io.inst(0).info.fusel === FuType.lsu) &&
     !(io.inst(0).ex.out.exception.asUInt.orR || io.inst(0).ex.out.interrupt.asUInt.orR) &&