From 55b5cc7907f713ee5d08573339ddb881492013bd Mon Sep 17 00:00:00 2001 From: Liphen Date: Fri, 1 Dec 2023 13:44:47 +0800 Subject: [PATCH] =?UTF-8?q?fix(ExeAccessMem):=20=E4=BE=8B=E5=A4=96?= =?UTF-8?q?=E4=BF=A1=E5=8F=B7=E9=80=BB=E8=BE=91=E9=94=99=E8=AF=AF?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- chisel/playground/src/pipeline/execute/ExeAccessMemCtrl.scala | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/chisel/playground/src/pipeline/execute/ExeAccessMemCtrl.scala b/chisel/playground/src/pipeline/execute/ExeAccessMemCtrl.scala index d96b7be..8e576db 100644 --- a/chisel/playground/src/pipeline/execute/ExeAccessMemCtrl.scala +++ b/chisel/playground/src/pipeline/execute/ExeAccessMemCtrl.scala @@ -76,8 +76,8 @@ class ExeAccessMemCtrl(implicit val config: CpuConfig) extends Module { for (i <- 0 until config.fuNum) { val store_inst = LSUOpType.isStore(io.inst(i).info.op) io.inst(i).ex.out := io.inst(i).ex.in - io.inst(i).ex.out.exception(loadAddrMisaligned) := store_inst && !addr_aligned(i) - io.inst(i).ex.out.exception(storeAddrMisaligned) := !store_inst && !addr_aligned(i) + io.inst(i).ex.out.exception(loadAddrMisaligned) := !store_inst && !addr_aligned(i) + io.inst(i).ex.out.exception(storeAddrMisaligned) := store_inst && !addr_aligned(i) } io.inst(0).mem_sel := (io.inst(0).info.fusel === FuType.lsu) && !(io.inst(0).ex.out.exception.asUInt.orR || io.inst(0).ex.out.interrupt.asUInt.orR) &&