From 8a3e85b201f856adb8bcbedc42b71088c3e543cd Mon Sep 17 00:00:00 2001
From: Liphen <xi.lifeng@qq.com>
Date: Fri, 1 Dec 2023 14:14:14 +0800
Subject: [PATCH] =?UTF-8?q?=E5=88=A0=E9=99=A4addr=5Ferr?=
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---
 chisel/playground/src/Core.scala                    | 1 -
 chisel/playground/src/cache/ICache.scala            | 1 -
 chisel/playground/src/defines/Bundles.scala         | 1 -
 chisel/playground/src/pipeline/fetch/InstFifo.scala | 1 -
 4 files changed, 4 deletions(-)

diff --git a/chisel/playground/src/Core.scala b/chisel/playground/src/Core.scala
index 3dbc9e4..f2d3091 100644
--- a/chisel/playground/src/Core.scala
+++ b/chisel/playground/src/Core.scala
@@ -82,7 +82,6 @@ class Core(implicit val config: CpuConfig) extends Module {
     instFifo.write(i).pc        := io.inst.addr(0) + (i * 4).U
     instFifo.write(i).inst      := io.inst.inst(i)
     instFifo.write(i).acc_err   := io.inst.acc_err
-    instFifo.write(i).addr_err  := io.inst.addr_err
   }
 
   decoderUnit.instFifo.info.empty        := instFifo.empty
diff --git a/chisel/playground/src/cache/ICache.scala b/chisel/playground/src/cache/ICache.scala
index e31daed..8f35c0f 100644
--- a/chisel/playground/src/cache/ICache.scala
+++ b/chisel/playground/src/cache/ICache.scala
@@ -48,7 +48,6 @@ class ICache(implicit config: CpuConfig) extends Module {
     io.cpu.inst_valid(i) := Mux(status === s_idle && !acc_err, false.B, saved(i).valid) && io.cpu.req
   })
 
-  io.cpu.addr_err     := addr_err
   io.cpu.acc_err      := acc_err
   io.cpu.icache_stall := Mux(status === s_idle && !acc_err, io.cpu.req, status =/= s_save)
 
diff --git a/chisel/playground/src/defines/Bundles.scala b/chisel/playground/src/defines/Bundles.scala
index 39a59ef..4d2004a 100644
--- a/chisel/playground/src/defines/Bundles.scala
+++ b/chisel/playground/src/defines/Bundles.scala
@@ -117,7 +117,6 @@ class Cache_ICache(implicit val config: CpuConfig) extends Bundle {
   val inst         = Input(Vec(config.instFetchNum, UInt(INST_WID.W)))
   val inst_valid   = Input(Vec(config.instFetchNum, Bool()))
   val acc_err      = Input(Bool())
-  val addr_err     = Input(Bool())
   val icache_stall = Input(Bool()) // icache_stall
 }
 
diff --git a/chisel/playground/src/pipeline/fetch/InstFifo.scala b/chisel/playground/src/pipeline/fetch/InstFifo.scala
index 596000c..87b5284 100644
--- a/chisel/playground/src/pipeline/fetch/InstFifo.scala
+++ b/chisel/playground/src/pipeline/fetch/InstFifo.scala
@@ -10,7 +10,6 @@ class BufferUnit extends Bundle {
   val inst      = UInt(INST_WID.W)
   val pht_index = UInt(bpuConfig.phtDepth.W)
   val acc_err   = Bool()
-  val addr_err  = Bool()
   val pc        = UInt(PC_WID.W)
 }