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增加取指错例外

This commit is contained in:
Liphen 2023-11-20 14:30:14 +08:00
parent b657c0c7f0
commit 79b8387218
4 changed files with 5 additions and 8 deletions
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4
chisel/playground/src/defines/Const.scala
View File

@ -33,10 +33,10 @@ trait Constants extends CoreParameter {
// inst rom
val INST_WID = 32
val INST_ADDR_WID = PC_WID
val INST_ADDR_WID = XLEN
// data ram
val DATA_ADDR_WID = PC_WID
val DATA_ADDR_WID = XLEN
// GPR RegFile
val AREG_NUM = 32

6
chisel/playground/src/pipeline/decoder/ARegfile.scala
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@ -26,7 +26,6 @@ class ARegFile(implicit val config: CpuConfig) extends Module {
val io = IO(new Bundle {
val read = Flipped(Vec(config.decoderNum, new Src12Read()))
val write = Flipped(Vec(config.commitNum, new RegWrite()))
val bpu = if (config.branchPredictor == "pesudo") Some(Flipped(new Src12Read())) else None
})
// 定义32个32位寄存器
@ -64,9 +63,4 @@ class ARegFile(implicit val config: CpuConfig) extends Module {
}
}
}
if (config.branchPredictor == "pesudo") {
io.bpu.get.src1.rdata := regs(io.bpu.get.src1.raddr)
io.bpu.get.src2.rdata := regs(io.bpu.get.src2.raddr)
}
}

2
chisel/playground/src/pipeline/decoder/DecoderUnit.scala
View File

@ -137,6 +137,7 @@ class DecoderUnit(implicit val config: CpuConfig) extends Module with HasExcepti
io.executeStage.inst0.ex.excode.map(_ := false.B)
io.executeStage.inst0.ex.excode(illegalInstr) := !decoder(0).io.out.inst_info.inst_valid &&
!hasInt && !io.instFifo.info.empty
io.executeStage.inst0.ex.excode(instrAccessFault) := io.instFifo.inst(0).acc_err
io.executeStage.inst0.jb_info.jump_regiser := jumpCtrl.out.jump_register
io.executeStage.inst0.jb_info.branch_inst := io.bpu.branch_inst
@ -159,6 +160,7 @@ class DecoderUnit(implicit val config: CpuConfig) extends Module with HasExcepti
io.executeStage.inst1.ex.excode.map(_ := false.B)
io.executeStage.inst1.ex.excode(illegalInstr) := !decoder(1).io.out.inst_info.inst_valid &&
!hasInt && !io.instFifo.info.almost_empty
io.executeStage.inst1.ex.excode(instrAccessFault) := io.instFifo.inst(1).acc_err
}
else {
io.executeStage.inst1 := DontCare

1
chisel/playground/src/pipeline/fetch/InstFifo.scala
View File

@ -9,6 +9,7 @@ class BufferUnit extends Bundle {
val bpuConfig = new BranchPredictorConfig()
val inst = UInt(INST_WID.W)
val pht_index = UInt(bpuConfig.phtDepth.W)
val acc_err = Bool()
val pc = UInt(PC_WID.W)
}