From 79b83872180d093ca406c1c423a8816c09c0cbd8 Mon Sep 17 00:00:00 2001
From: Liphen <xi.lifeng@qq.com>
Date: Mon, 20 Nov 2023 14:30:14 +0800
Subject: [PATCH] =?UTF-8?q?=E5=A2=9E=E5=8A=A0=E5=8F=96=E6=8C=87=E9=94=99?=
 =?UTF-8?q?=E4=BE=8B=E5=A4=96?=
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---
 chisel/playground/src/defines/Const.scala                | 4 ++--
 chisel/playground/src/pipeline/decoder/ARegfile.scala    | 6 ------
 chisel/playground/src/pipeline/decoder/DecoderUnit.scala | 2 ++
 chisel/playground/src/pipeline/fetch/InstFifo.scala      | 1 +
 4 files changed, 5 insertions(+), 8 deletions(-)

diff --git a/chisel/playground/src/defines/Const.scala b/chisel/playground/src/defines/Const.scala
index 5de7a48..5fff97a 100644
--- a/chisel/playground/src/defines/Const.scala
+++ b/chisel/playground/src/defines/Const.scala
@@ -33,10 +33,10 @@ trait Constants extends CoreParameter {
 
   // inst rom
   val INST_WID      = 32
-  val INST_ADDR_WID = PC_WID
+  val INST_ADDR_WID = XLEN
 
   // data ram
-  val DATA_ADDR_WID = PC_WID
+  val DATA_ADDR_WID = XLEN
 
   // GPR RegFile
   val AREG_NUM     = 32
diff --git a/chisel/playground/src/pipeline/decoder/ARegfile.scala b/chisel/playground/src/pipeline/decoder/ARegfile.scala
index 62e3505..2a4ba0d 100644
--- a/chisel/playground/src/pipeline/decoder/ARegfile.scala
+++ b/chisel/playground/src/pipeline/decoder/ARegfile.scala
@@ -26,7 +26,6 @@ class ARegFile(implicit val config: CpuConfig) extends Module {
   val io = IO(new Bundle {
     val read  = Flipped(Vec(config.decoderNum, new Src12Read()))
     val write = Flipped(Vec(config.commitNum, new RegWrite()))
-    val bpu   = if (config.branchPredictor == "pesudo") Some(Flipped(new Src12Read())) else None
   })
 
   // 定义32个32位寄存器
@@ -64,9 +63,4 @@ class ARegFile(implicit val config: CpuConfig) extends Module {
       }
     }
   }
-
-  if (config.branchPredictor == "pesudo") {
-    io.bpu.get.src1.rdata := regs(io.bpu.get.src1.raddr)
-    io.bpu.get.src2.rdata := regs(io.bpu.get.src2.raddr)
-  }
 }
diff --git a/chisel/playground/src/pipeline/decoder/DecoderUnit.scala b/chisel/playground/src/pipeline/decoder/DecoderUnit.scala
index a4991bb..5294ca9 100644
--- a/chisel/playground/src/pipeline/decoder/DecoderUnit.scala
+++ b/chisel/playground/src/pipeline/decoder/DecoderUnit.scala
@@ -137,6 +137,7 @@ class DecoderUnit(implicit val config: CpuConfig) extends Module with HasExcepti
   io.executeStage.inst0.ex.excode.map(_ := false.B)
   io.executeStage.inst0.ex.excode(illegalInstr) := !decoder(0).io.out.inst_info.inst_valid &&
     !hasInt && !io.instFifo.info.empty
+  io.executeStage.inst0.ex.excode(instrAccessFault) := io.instFifo.inst(0).acc_err
 
   io.executeStage.inst0.jb_info.jump_regiser     := jumpCtrl.out.jump_register
   io.executeStage.inst0.jb_info.branch_inst      := io.bpu.branch_inst
@@ -159,6 +160,7 @@ class DecoderUnit(implicit val config: CpuConfig) extends Module with HasExcepti
     io.executeStage.inst1.ex.excode.map(_ := false.B)
     io.executeStage.inst1.ex.excode(illegalInstr) := !decoder(1).io.out.inst_info.inst_valid &&
     !hasInt && !io.instFifo.info.almost_empty
+    io.executeStage.inst1.ex.excode(instrAccessFault) := io.instFifo.inst(1).acc_err
   }
   else {
     io.executeStage.inst1 := DontCare
diff --git a/chisel/playground/src/pipeline/fetch/InstFifo.scala b/chisel/playground/src/pipeline/fetch/InstFifo.scala
index 3e10f45..3bc1b06 100644
--- a/chisel/playground/src/pipeline/fetch/InstFifo.scala
+++ b/chisel/playground/src/pipeline/fetch/InstFifo.scala
@@ -9,6 +9,7 @@ class BufferUnit extends Bundle {
   val bpuConfig = new BranchPredictorConfig()
   val inst      = UInt(INST_WID.W)
   val pht_index = UInt(bpuConfig.phtDepth.W)
+  val acc_err   = Bool()
   val pc        = UInt(PC_WID.W)
 }