fix(mem acc): 修复错误数据宽

2023-11-29 17:41:14 +08:00 · 2023-11-29 17:41:14 +08:00 · 31a35d4ff0
parent 1b3ce1e739
commit 31a35d4ff0
1 changed files with 2 additions and 2 deletions
--- a/chisel/playground/src/pipeline/memory/DataMemoryAccess.scala
+++ b/chisel/playground/src/pipeline/memory/DataMemoryAccess.scala
@ -16,8 +16,8 @@ class DataMemoryAccess_DataMemory extends Bundle {
    val rlen  = UInt(AXI_LEN_WID.W)
    val wen   = Bool()
    val wstrb = UInt(AXI_STRB_WID.W)
-    val addr  = UInt(AXI_ADDR_WID.W)
-    val wdata = UInt(AXI_DATA_WID.W)
+    val addr  = UInt(DATA_ADDR_WID.W)
+    val wdata = UInt(DATA_WID.W)
  })
 }