From 31a35d4ff0132018ba1d94c2a8436514cbc02d4b Mon Sep 17 00:00:00 2001 From: Liphen Date: Wed, 29 Nov 2023 17:41:14 +0800 Subject: [PATCH] =?UTF-8?q?fix(mem=20acc):=20=E4=BF=AE=E5=A4=8D=E9=94=99?= =?UTF-8?q?=E8=AF=AF=E6=95=B0=E6=8D=AE=E5=AE=BD?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- chisel/playground/src/pipeline/memory/DataMemoryAccess.scala | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/chisel/playground/src/pipeline/memory/DataMemoryAccess.scala b/chisel/playground/src/pipeline/memory/DataMemoryAccess.scala index 95ed4ed..9d43164 100644 --- a/chisel/playground/src/pipeline/memory/DataMemoryAccess.scala +++ b/chisel/playground/src/pipeline/memory/DataMemoryAccess.scala @@ -16,8 +16,8 @@ class DataMemoryAccess_DataMemory extends Bundle { val rlen = UInt(AXI_LEN_WID.W) val wen = Bool() val wstrb = UInt(AXI_STRB_WID.W) - val addr = UInt(AXI_ADDR_WID.W) - val wdata = UInt(AXI_DATA_WID.W) + val addr = UInt(DATA_ADDR_WID.W) + val wdata = UInt(DATA_WID.W) }) }