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fix(mem acc): 修复错误数据宽

This commit is contained in:
Liphen 2023-11-29 17:41:14 +08:00
parent 1b3ce1e739
commit 31a35d4ff0
1 changed files with 2 additions and 2 deletions
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4
chisel/playground/src/pipeline/memory/DataMemoryAccess.scala
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@ -16,8 +16,8 @@ class DataMemoryAccess_DataMemory extends Bundle {
val rlen = UInt(AXI_LEN_WID.W) val rlen = UInt(AXI_LEN_WID.W)
val wen = Bool() val wen = Bool()
val wstrb = UInt(AXI_STRB_WID.W) val wstrb = UInt(AXI_STRB_WID.W)
val addr = UInt(AXI_ADDR_WID.W) val addr = UInt(DATA_ADDR_WID.W)
val wdata = UInt(AXI_DATA_WID.W) val wdata = UInt(DATA_WID.W)
}) })
} }