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fix(id): 修复指令错误判断条件

This commit is contained in:
Liphen 2023-11-24 16:23:10 +08:00
parent a761e8ebad
commit 2c59111fbf
1 changed files with 3 additions and 3 deletions
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6
chisel/playground/src/pipeline/decoder/Decoder.scala
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@ -37,7 +37,7 @@ class Decoder extends Module with HasInstrType {
val (rs, rt, rd) = (inst(19, 15), inst(24, 20), inst(11, 7)) val (rs, rt, rd) = (inst(19, 15), inst(24, 20), inst(11, 7))
io.out.inst_info.valid := false.B io.out.inst_info.valid := false.B
io.out.inst_info.inst_legal := instrType === InstrN io.out.inst_info.inst_legal := instrType =/= InstrN
io.out.inst_info.reg1_ren := src1Type === SrcType.reg io.out.inst_info.reg1_ren := src1Type === SrcType.reg
io.out.inst_info.reg1_raddr := Mux(src1Type === SrcType.reg, rs, 0.U) io.out.inst_info.reg1_raddr := Mux(src1Type === SrcType.reg, rs, 0.U)
io.out.inst_info.reg2_ren := src2Type === SrcType.reg io.out.inst_info.reg2_ren := src2Type === SrcType.reg
@ -65,6 +65,6 @@ class Decoder extends Module with HasInstrType {
InstrJ -> SignedExtend(Cat(inst(31), inst(19, 12), inst(20), inst(30, 21), 0.U(1.W)), XLEN) InstrJ -> SignedExtend(Cat(inst(31), inst(19, 12), inst(20), inst(30, 21), 0.U(1.W)), XLEN)
) )
) )
io.out.inst_info.inst := inst io.out.inst_info.inst := inst
io.out.inst_info.mem_wreg := fuType === FuType.lsu && LSUOpType.isLoad(fuOpType) io.out.inst_info.mem_wreg := fuType === FuType.lsu && LSUOpType.isLoad(fuOpType)
} }