From 2c59111fbf92f8f36667f2aba7bd597e4814ddac Mon Sep 17 00:00:00 2001 From: Liphen Date: Fri, 24 Nov 2023 16:23:10 +0800 Subject: [PATCH] =?UTF-8?q?fix(id):=20=E4=BF=AE=E5=A4=8D=E6=8C=87=E4=BB=A4?= =?UTF-8?q?=E9=94=99=E8=AF=AF=E5=88=A4=E6=96=AD=E6=9D=A1=E4=BB=B6?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- chisel/playground/src/pipeline/decoder/Decoder.scala | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/chisel/playground/src/pipeline/decoder/Decoder.scala b/chisel/playground/src/pipeline/decoder/Decoder.scala index 4d5c465..52bf3bd 100644 --- a/chisel/playground/src/pipeline/decoder/Decoder.scala +++ b/chisel/playground/src/pipeline/decoder/Decoder.scala @@ -37,7 +37,7 @@ class Decoder extends Module with HasInstrType { val (rs, rt, rd) = (inst(19, 15), inst(24, 20), inst(11, 7)) io.out.inst_info.valid := false.B - io.out.inst_info.inst_legal := instrType === InstrN + io.out.inst_info.inst_legal := instrType =/= InstrN io.out.inst_info.reg1_ren := src1Type === SrcType.reg io.out.inst_info.reg1_raddr := Mux(src1Type === SrcType.reg, rs, 0.U) io.out.inst_info.reg2_ren := src2Type === SrcType.reg @@ -65,6 +65,6 @@ class Decoder extends Module with HasInstrType { InstrJ -> SignedExtend(Cat(inst(31), inst(19, 12), inst(20), inst(30, 21), 0.U(1.W)), XLEN) ) ) - io.out.inst_info.inst := inst - io.out.inst_info.mem_wreg := fuType === FuType.lsu && LSUOpType.isLoad(fuOpType) + io.out.inst_info.inst := inst + io.out.inst_info.mem_wreg := fuType === FuType.lsu && LSUOpType.isLoad(fuOpType) }