fix: 增加valid标识
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parent
3000c5b424
commit
a761e8ebad
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@ -28,7 +28,8 @@ class RdInfo extends Bundle {
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}
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class InstInfo extends Bundle {
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val inst_valid = Bool()
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val valid = Bool()
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val inst_legal = Bool()
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val reg1_ren = Bool()
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val reg1_raddr = UInt(REG_ADDR_WID.W)
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val reg2_ren = Bool()
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@ -38,7 +39,6 @@ class InstInfo extends Bundle {
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val reg_wen = Bool()
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val reg_waddr = UInt(REG_ADDR_WID.W)
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val imm = UInt(XLEN.W)
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val dual_issue = Bool()
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val inst = UInt(INST_WID.W)
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val mem_wreg = Bool()
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}
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@ -36,7 +36,8 @@ class Decoder extends Module with HasInstrType {
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val (rs, rt, rd) = (inst(19, 15), inst(24, 20), inst(11, 7))
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io.out.inst_info.inst_valid := instrType === InstrN
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io.out.inst_info.valid := false.B
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io.out.inst_info.inst_legal := instrType === InstrN
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io.out.inst_info.reg1_ren := src1Type === SrcType.reg
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io.out.inst_info.reg1_raddr := Mux(src1Type === SrcType.reg, rs, 0.U)
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io.out.inst_info.reg2_ren := src2Type === SrcType.reg
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@ -64,7 +65,6 @@ class Decoder extends Module with HasInstrType {
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InstrJ -> SignedExtend(Cat(inst(31), inst(19, 12), inst(20), inst(30, 21), 0.U(1.W)), XLEN)
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)
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)
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io.out.inst_info.dual_issue := false.B
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io.out.inst_info.inst := inst
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io.out.inst_info.mem_wreg := fuType === FuType.lsu && LSUOpType.isLoad(fuOpType)
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}
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@ -103,9 +103,9 @@ class DecoderUnit(implicit val config: CpuConfig) extends Module with HasExcepti
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io.ctrl.inst0.src2.raddr := decoder(0).io.out.inst_info.reg2_raddr
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io.ctrl.branch := inst0_branch
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io.executeStage.inst0.valid := !io.instFifo.info.empty
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io.executeStage.inst0.pc := pc(0)
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io.executeStage.inst0.inst_info := inst_info(0)
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io.executeStage.inst0.pc := pc(0)
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io.executeStage.inst0.inst_info := inst_info(0)
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io.executeStage.inst0.inst_info.valid := !io.instFifo.info.empty
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io.executeStage.inst0.src_info.src1_data := Mux(
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inst_info(0).reg1_ren,
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forwardCtrl.out.inst(0).src1.rdata,
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@ -118,7 +118,7 @@ class DecoderUnit(implicit val config: CpuConfig) extends Module with HasExcepti
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)
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(0 until (INT_WID)).foreach(i => io.executeStage.inst0.ex.interrupt(i) := io.csr.interrupt(i))
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io.executeStage.inst0.ex.exception.map(_ := false.B)
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io.executeStage.inst0.ex.exception(illegalInstr) := !inst_info(0).inst_valid
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io.executeStage.inst0.ex.exception(illegalInstr) := !inst_info(0).inst_legal
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io.executeStage.inst0.ex.exception(instrAccessFault) := io.instFifo.inst(0).acc_err
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io.executeStage.inst0.ex.exception(instrAddrMisaligned) := io.instFifo.inst(0).addr_err
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io.executeStage.inst0.ex.exception(breakPoint) := inst_info(0).inst(31, 20) === privEbreak &&
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@ -141,9 +141,9 @@ class DecoderUnit(implicit val config: CpuConfig) extends Module with HasExcepti
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io.executeStage.inst0.jb_info.branch_target := io.bpu.branch_target
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io.executeStage.inst0.jb_info.update_pht_index := io.bpu.update_pht_index
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io.executeStage.inst1.valid := !io.instFifo.info.almost_empty
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io.executeStage.inst1.pc := pc(1)
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io.executeStage.inst1.inst_info := inst_info(1)
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io.executeStage.inst1.pc := pc(1)
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io.executeStage.inst1.inst_info := inst_info(1)
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io.executeStage.inst1.inst_info.valid := !io.instFifo.info.almost_empty && !io.instFifo.info.empty
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io.executeStage.inst1.src_info.src1_data := Mux(
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inst_info(1).reg1_ren,
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forwardCtrl.out.inst(1).src1.rdata,
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@ -156,7 +156,7 @@ class DecoderUnit(implicit val config: CpuConfig) extends Module with HasExcepti
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)
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(0 until (INT_WID)).foreach(i => io.executeStage.inst1.ex.interrupt(i) := io.csr.interrupt(i))
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io.executeStage.inst1.ex.exception.map(_ := false.B)
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io.executeStage.inst1.ex.exception(illegalInstr) := !inst_info(1).inst_valid
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io.executeStage.inst1.ex.exception(illegalInstr) := !inst_info(1).inst_legal
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io.executeStage.inst1.ex.exception(instrAccessFault) := io.instFifo.inst(1).acc_err
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io.executeStage.inst1.ex.exception(instrAddrMisaligned) := io.instFifo.inst(1).addr_err
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io.executeStage.inst1.ex.exception(breakPoint) := inst_info(1).inst(31, 20) === privEbreak &&
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@ -50,8 +50,6 @@ class Issue(implicit val config: CpuConfig) extends Module {
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// 指令1是否允许执行
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io.inst1.allow_to_go := io.allow_to_go &&
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!instFifo_invalid &&
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inst0.dual_issue &&
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inst1.dual_issue &&
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!struct_conflict &&
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!data_conflict &&
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!VecInit(FuType.bru, FuType.mou).contains(io.decodeInst(1).fusel)
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@ -17,6 +17,8 @@ class BranchCtrl extends Module {
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val pred_fail = Output(Bool())
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}
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})
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val valid =
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io.in.inst_info.fusel === FuType.bru && ALUOpType.isBranch(io.in.inst_info.op) && io.in.inst_info.valid
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val src1 = io.in.src_info.src1_data
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val src2 = io.in.src_info.src2_data
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val op = io.in.inst_info.op
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@ -31,5 +33,6 @@ class BranchCtrl extends Module {
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ALUOpType.getBranchType(ALUOpType.bltu) -> sltu
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)
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io.out.pred_fail := io.in.pred_branch =/= io.out.branch
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io.out.branch := LookupTree(ALUOpType.getBranchType(op), table) ^ ALUOpType.isBranchInvert(op)
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io.out.branch := (LookupTree(ALUOpType.getBranchType(op), table) ^
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ALUOpType.isBranchInvert(op)) & valid
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}
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@ -80,8 +80,8 @@ class ExeAccessMemCtrl(implicit val config: CpuConfig) extends Module {
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io.inst(i).ex.out.exception(storeAddrMisaligned) := !store_inst && !addr_aligned(i)
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}
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io.inst(0).mem_sel := (LSUOpType.isStore(io.inst(0).inst_info.op) || LSUOpType.isLoad(io.inst(0).inst_info.op)) &&
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!io.inst(0).ex.out.exception.asUInt.orR
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!io.inst(0).ex.out.exception.asUInt.orR && io.inst(0).inst_info.valid
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io.inst(1).mem_sel := (LSUOpType.isStore(io.inst(1).inst_info.op) || LSUOpType.isLoad(io.inst(1).inst_info.op)) &&
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!io.inst(0).ex.out.exception.asUInt.orR && !io.inst(1).ex.out.exception.asUInt.orR
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!io.inst(0).ex.out.exception.asUInt.orR && !io.inst(1).ex.out.exception.asUInt.orR && io.inst(1).inst_info.valid
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}
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@ -7,7 +7,6 @@ import cpu.defines.Const._
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import cpu.{BranchPredictorConfig, CpuConfig}
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class IdExeInst0 extends Bundle {
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val valid = Bool()
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val config = new BranchPredictorConfig()
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val pc = UInt(PC_WID.W)
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val inst_info = new InstInfo()
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@ -25,7 +24,6 @@ class IdExeInst0 extends Bundle {
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}
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class IdExeInst1 extends Bundle {
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val valid = Bool()
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val allow_to_go = Bool()
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val pc = UInt(PC_WID.W)
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val inst_info = new InstInfo()
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@ -36,15 +36,19 @@ class ExecuteUnit(implicit val config: CpuConfig) extends Module {
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val fu = Module(new Fu()).io
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val accessMemCtrl = Module(new ExeAccessMemCtrl()).io
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val valid = VecInit(io.executeStage.inst0.inst_info.valid, io.executeStage.inst1.inst_info.valid)
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io.ctrl.inst(0).mem_wreg := io.executeStage.inst0.inst_info.mem_wreg
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io.ctrl.inst(0).reg_waddr := io.executeStage.inst0.inst_info.reg_waddr
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io.ctrl.inst(1).mem_wreg := io.executeStage.inst1.inst_info.mem_wreg
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io.ctrl.inst(1).reg_waddr := io.executeStage.inst1.inst_info.reg_waddr
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io.ctrl.branch := io.ctrl.allow_to_go &&
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io.ctrl.branch := valid(0) && io.ctrl.allow_to_go &&
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(io.executeStage.inst0.jb_info.jump_regiser || fu.branch.pred_fail)
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val csr_sel0 = io.executeStage.inst0.inst_info.fusel === FuType.csr && !io.executeStage.inst0.ex.exception.asUInt.orR
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val csr_sel1 = io.executeStage.inst1.inst_info.fusel === FuType.csr && !io.executeStage.inst1.ex.exception.asUInt.orR
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val csr_sel0 = valid(0) && io.executeStage.inst0.inst_info.fusel === FuType.csr &&
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!io.executeStage.inst0.ex.exception.asUInt.orR
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val csr_sel1 = valid(1) && io.executeStage.inst1.inst_info.fusel === FuType.csr &&
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!io.executeStage.inst1.ex.exception.asUInt.orR
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io.csr.in.valid := csr_sel0 || csr_sel1
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io.csr.in.inst_info := Mux(
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csr_sel0 && !csr_sel1,
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@ -96,8 +100,7 @@ class ExecuteUnit(implicit val config: CpuConfig) extends Module {
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io.bpu.branch := fu.branch.branch
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io.bpu.branch_inst := io.executeStage.inst0.jb_info.branch_inst
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io.fetchUnit.branch := io.ctrl.allow_to_go &&
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(io.executeStage.inst0.jb_info.jump_regiser || fu.branch.pred_fail) && io.executeStage.inst0.valid
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io.fetchUnit.branch := io.ctrl.branch
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io.fetchUnit.target := MuxCase(
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io.executeStage.inst0.pc + 4.U, // 默认顺序运行吧
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Seq(
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