diff --git a/chisel/playground/src/defines/Bundles.scala b/chisel/playground/src/defines/Bundles.scala
index 51712dc..8c819a7 100644
--- a/chisel/playground/src/defines/Bundles.scala
+++ b/chisel/playground/src/defines/Bundles.scala
@@ -28,7 +28,8 @@ class RdInfo extends Bundle {
 }
 
 class InstInfo extends Bundle {
-  val inst_valid = Bool()
+  val valid      = Bool()
+  val inst_legal = Bool()
   val reg1_ren   = Bool()
   val reg1_raddr = UInt(REG_ADDR_WID.W)
   val reg2_ren   = Bool()
@@ -38,7 +39,6 @@ class InstInfo extends Bundle {
   val reg_wen    = Bool()
   val reg_waddr  = UInt(REG_ADDR_WID.W)
   val imm        = UInt(XLEN.W)
-  val dual_issue = Bool()
   val inst       = UInt(INST_WID.W)
   val mem_wreg   = Bool()
 }
diff --git a/chisel/playground/src/pipeline/decoder/Decoder.scala b/chisel/playground/src/pipeline/decoder/Decoder.scala
index 4c1060c..4d5c465 100644
--- a/chisel/playground/src/pipeline/decoder/Decoder.scala
+++ b/chisel/playground/src/pipeline/decoder/Decoder.scala
@@ -36,7 +36,8 @@ class Decoder extends Module with HasInstrType {
 
   val (rs, rt, rd) = (inst(19, 15), inst(24, 20), inst(11, 7))
 
-  io.out.inst_info.inst_valid := instrType === InstrN
+  io.out.inst_info.valid      := false.B
+  io.out.inst_info.inst_legal := instrType === InstrN
   io.out.inst_info.reg1_ren   := src1Type === SrcType.reg
   io.out.inst_info.reg1_raddr := Mux(src1Type === SrcType.reg, rs, 0.U)
   io.out.inst_info.reg2_ren   := src2Type === SrcType.reg
@@ -64,7 +65,6 @@ class Decoder extends Module with HasInstrType {
       InstrJ  -> SignedExtend(Cat(inst(31), inst(19, 12), inst(20), inst(30, 21), 0.U(1.W)), XLEN)
     )
   )
-  io.out.inst_info.dual_issue := false.B
   io.out.inst_info.inst       := inst
   io.out.inst_info.mem_wreg   := fuType === FuType.lsu && LSUOpType.isLoad(fuOpType)
 }
diff --git a/chisel/playground/src/pipeline/decoder/DecoderUnit.scala b/chisel/playground/src/pipeline/decoder/DecoderUnit.scala
index 6c5205b..4a92043 100644
--- a/chisel/playground/src/pipeline/decoder/DecoderUnit.scala
+++ b/chisel/playground/src/pipeline/decoder/DecoderUnit.scala
@@ -103,9 +103,9 @@ class DecoderUnit(implicit val config: CpuConfig) extends Module with HasExcepti
   io.ctrl.inst0.src2.raddr := decoder(0).io.out.inst_info.reg2_raddr
   io.ctrl.branch           := inst0_branch
 
-  io.executeStage.inst0.valid     := !io.instFifo.info.empty
-  io.executeStage.inst0.pc        := pc(0)
-  io.executeStage.inst0.inst_info := inst_info(0)
+  io.executeStage.inst0.pc              := pc(0)
+  io.executeStage.inst0.inst_info       := inst_info(0)
+  io.executeStage.inst0.inst_info.valid := !io.instFifo.info.empty
   io.executeStage.inst0.src_info.src1_data := Mux(
     inst_info(0).reg1_ren,
     forwardCtrl.out.inst(0).src1.rdata,
@@ -118,7 +118,7 @@ class DecoderUnit(implicit val config: CpuConfig) extends Module with HasExcepti
   )
   (0 until (INT_WID)).foreach(i => io.executeStage.inst0.ex.interrupt(i) := io.csr.interrupt(i))
   io.executeStage.inst0.ex.exception.map(_                := false.B)
-  io.executeStage.inst0.ex.exception(illegalInstr)        := !inst_info(0).inst_valid
+  io.executeStage.inst0.ex.exception(illegalInstr)        := !inst_info(0).inst_legal
   io.executeStage.inst0.ex.exception(instrAccessFault)    := io.instFifo.inst(0).acc_err
   io.executeStage.inst0.ex.exception(instrAddrMisaligned) := io.instFifo.inst(0).addr_err
   io.executeStage.inst0.ex.exception(breakPoint) := inst_info(0).inst(31, 20) === privEbreak &&
@@ -141,9 +141,9 @@ class DecoderUnit(implicit val config: CpuConfig) extends Module with HasExcepti
   io.executeStage.inst0.jb_info.branch_target    := io.bpu.branch_target
   io.executeStage.inst0.jb_info.update_pht_index := io.bpu.update_pht_index
 
-  io.executeStage.inst1.valid     := !io.instFifo.info.almost_empty
-  io.executeStage.inst1.pc        := pc(1)
-  io.executeStage.inst1.inst_info := inst_info(1)
+  io.executeStage.inst1.pc              := pc(1)
+  io.executeStage.inst1.inst_info       := inst_info(1)
+  io.executeStage.inst1.inst_info.valid := !io.instFifo.info.almost_empty && !io.instFifo.info.empty
   io.executeStage.inst1.src_info.src1_data := Mux(
     inst_info(1).reg1_ren,
     forwardCtrl.out.inst(1).src1.rdata,
@@ -156,7 +156,7 @@ class DecoderUnit(implicit val config: CpuConfig) extends Module with HasExcepti
   )
   (0 until (INT_WID)).foreach(i => io.executeStage.inst1.ex.interrupt(i) := io.csr.interrupt(i))
   io.executeStage.inst1.ex.exception.map(_                := false.B)
-  io.executeStage.inst1.ex.exception(illegalInstr)        := !inst_info(1).inst_valid
+  io.executeStage.inst1.ex.exception(illegalInstr)        := !inst_info(1).inst_legal
   io.executeStage.inst1.ex.exception(instrAccessFault)    := io.instFifo.inst(1).acc_err
   io.executeStage.inst1.ex.exception(instrAddrMisaligned) := io.instFifo.inst(1).addr_err
   io.executeStage.inst1.ex.exception(breakPoint) := inst_info(1).inst(31, 20) === privEbreak &&
diff --git a/chisel/playground/src/pipeline/decoder/Issue.scala b/chisel/playground/src/pipeline/decoder/Issue.scala
index 13565fa..f8f6cd5 100644
--- a/chisel/playground/src/pipeline/decoder/Issue.scala
+++ b/chisel/playground/src/pipeline/decoder/Issue.scala
@@ -50,8 +50,6 @@ class Issue(implicit val config: CpuConfig) extends Module {
     // 指令1是否允许执行
     io.inst1.allow_to_go := io.allow_to_go &&
     !instFifo_invalid &&
-    inst0.dual_issue &&
-    inst1.dual_issue &&
     !struct_conflict &&
     !data_conflict &&
     !VecInit(FuType.bru, FuType.mou).contains(io.decodeInst(1).fusel)
diff --git a/chisel/playground/src/pipeline/execute/BranchCtrl.scala b/chisel/playground/src/pipeline/execute/BranchCtrl.scala
index add39b3..e04112d 100644
--- a/chisel/playground/src/pipeline/execute/BranchCtrl.scala
+++ b/chisel/playground/src/pipeline/execute/BranchCtrl.scala
@@ -17,6 +17,8 @@ class BranchCtrl extends Module {
       val pred_fail = Output(Bool())
     }
   })
+  val valid =
+    io.in.inst_info.fusel === FuType.bru && ALUOpType.isBranch(io.in.inst_info.op) && io.in.inst_info.valid
   val src1   = io.in.src_info.src1_data
   val src2   = io.in.src_info.src2_data
   val op     = io.in.inst_info.op
@@ -31,5 +33,6 @@ class BranchCtrl extends Module {
     ALUOpType.getBranchType(ALUOpType.bltu) -> sltu
   )
   io.out.pred_fail := io.in.pred_branch =/= io.out.branch
-  io.out.branch    := LookupTree(ALUOpType.getBranchType(op), table) ^ ALUOpType.isBranchInvert(op)
+  io.out.branch := (LookupTree(ALUOpType.getBranchType(op), table) ^
+    ALUOpType.isBranchInvert(op)) & valid
 }
diff --git a/chisel/playground/src/pipeline/execute/ExeAccessMemCtrl.scala b/chisel/playground/src/pipeline/execute/ExeAccessMemCtrl.scala
index ddfe2dd..e1ef7aa 100644
--- a/chisel/playground/src/pipeline/execute/ExeAccessMemCtrl.scala
+++ b/chisel/playground/src/pipeline/execute/ExeAccessMemCtrl.scala
@@ -80,8 +80,8 @@ class ExeAccessMemCtrl(implicit val config: CpuConfig) extends Module {
     io.inst(i).ex.out.exception(storeAddrMisaligned) := !store_inst && !addr_aligned(i)
   }
   io.inst(0).mem_sel := (LSUOpType.isStore(io.inst(0).inst_info.op) || LSUOpType.isLoad(io.inst(0).inst_info.op)) &&
-    !io.inst(0).ex.out.exception.asUInt.orR
+    !io.inst(0).ex.out.exception.asUInt.orR && io.inst(0).inst_info.valid
   io.inst(1).mem_sel := (LSUOpType.isStore(io.inst(1).inst_info.op) || LSUOpType.isLoad(io.inst(1).inst_info.op)) &&
-    !io.inst(0).ex.out.exception.asUInt.orR && !io.inst(1).ex.out.exception.asUInt.orR
+    !io.inst(0).ex.out.exception.asUInt.orR && !io.inst(1).ex.out.exception.asUInt.orR && io.inst(1).inst_info.valid
 
 }
diff --git a/chisel/playground/src/pipeline/execute/ExecuteStage.scala b/chisel/playground/src/pipeline/execute/ExecuteStage.scala
index 22ecca4..f166948 100644
--- a/chisel/playground/src/pipeline/execute/ExecuteStage.scala
+++ b/chisel/playground/src/pipeline/execute/ExecuteStage.scala
@@ -7,7 +7,6 @@ import cpu.defines.Const._
 import cpu.{BranchPredictorConfig, CpuConfig}
 
 class IdExeInst0 extends Bundle {
-  val valid     = Bool()
   val config    = new BranchPredictorConfig()
   val pc        = UInt(PC_WID.W)
   val inst_info = new InstInfo()
@@ -25,7 +24,6 @@ class IdExeInst0 extends Bundle {
 }
 
 class IdExeInst1 extends Bundle {
-  val valid       = Bool()
   val allow_to_go = Bool()
   val pc          = UInt(PC_WID.W)
   val inst_info   = new InstInfo()
diff --git a/chisel/playground/src/pipeline/execute/ExecuteUnit.scala b/chisel/playground/src/pipeline/execute/ExecuteUnit.scala
index 04ed125..9ae7f66 100644
--- a/chisel/playground/src/pipeline/execute/ExecuteUnit.scala
+++ b/chisel/playground/src/pipeline/execute/ExecuteUnit.scala
@@ -36,15 +36,19 @@ class ExecuteUnit(implicit val config: CpuConfig) extends Module {
   val fu            = Module(new Fu()).io
   val accessMemCtrl = Module(new ExeAccessMemCtrl()).io
 
+  val valid = VecInit(io.executeStage.inst0.inst_info.valid, io.executeStage.inst1.inst_info.valid)
+
   io.ctrl.inst(0).mem_wreg  := io.executeStage.inst0.inst_info.mem_wreg
   io.ctrl.inst(0).reg_waddr := io.executeStage.inst0.inst_info.reg_waddr
   io.ctrl.inst(1).mem_wreg  := io.executeStage.inst1.inst_info.mem_wreg
   io.ctrl.inst(1).reg_waddr := io.executeStage.inst1.inst_info.reg_waddr
-  io.ctrl.branch := io.ctrl.allow_to_go &&
+  io.ctrl.branch := valid(0) && io.ctrl.allow_to_go &&
     (io.executeStage.inst0.jb_info.jump_regiser || fu.branch.pred_fail)
 
-  val csr_sel0 = io.executeStage.inst0.inst_info.fusel === FuType.csr && !io.executeStage.inst0.ex.exception.asUInt.orR
-  val csr_sel1 = io.executeStage.inst1.inst_info.fusel === FuType.csr && !io.executeStage.inst1.ex.exception.asUInt.orR
+  val csr_sel0 = valid(0) && io.executeStage.inst0.inst_info.fusel === FuType.csr &&
+    !io.executeStage.inst0.ex.exception.asUInt.orR
+  val csr_sel1 = valid(1) && io.executeStage.inst1.inst_info.fusel === FuType.csr &&
+    !io.executeStage.inst1.ex.exception.asUInt.orR
   io.csr.in.valid := csr_sel0 || csr_sel1
   io.csr.in.inst_info := Mux(
     csr_sel0 && !csr_sel1,
@@ -96,8 +100,7 @@ class ExecuteUnit(implicit val config: CpuConfig) extends Module {
   io.bpu.branch           := fu.branch.branch
   io.bpu.branch_inst      := io.executeStage.inst0.jb_info.branch_inst
 
-  io.fetchUnit.branch := io.ctrl.allow_to_go &&
-    (io.executeStage.inst0.jb_info.jump_regiser || fu.branch.pred_fail) && io.executeStage.inst0.valid
+  io.fetchUnit.branch := io.ctrl.branch
   io.fetchUnit.target := MuxCase(
     io.executeStage.inst0.pc + 4.U, // 默认顺序运行吧
     Seq(