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style: 修改全加器顶层模块格式

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Liphen 2023-11-03 15:37:47 +08:00
parent 5b775df08a
commit 2182d0f464
1 changed files with 7 additions and 7 deletions
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14
doc/数字电路实验/全加器/全加器.md
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@ -40,14 +40,14 @@
```verilog ```verilog
module FullAdder ( module FullAdder (
input wire A, input wire A,
input wire B, input wire B,
input wire Cin, input wire Cin,
output wire S, output wire S,
output wire Cout output wire Cout
); );
// TODO：你的代码实现 // TODO：你的代码实现
endmodule endmodule