From 2182d0f464dcb2fa8613f624bf04c136a16b2190 Mon Sep 17 00:00:00 2001
From: Liphen <xi.lifeng@qq.com>
Date: Fri, 3 Nov 2023 15:37:47 +0800
Subject: [PATCH] =?UTF-8?q?style:=20=E4=BF=AE=E6=94=B9=E5=85=A8=E5=8A=A0?=
 =?UTF-8?q?=E5=99=A8=E9=A1=B6=E5=B1=82=E6=A8=A1=E5=9D=97=E6=A0=BC=E5=BC=8F?=
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---
 doc/数字电路实验/全加器/全加器.md | 14 +++++++-------
 1 file changed, 7 insertions(+), 7 deletions(-)

diff --git a/doc/数字电路实验/全加器/全加器.md b/doc/数字电路实验/全加器/全加器.md
index 9027975..537f075 100644
--- a/doc/数字电路实验/全加器/全加器.md
+++ b/doc/数字电路实验/全加器/全加器.md
@@ -40,14 +40,14 @@
 
 ```verilog
 module FullAdder (
-         input wire A,
-         input wire B,
-         input wire Cin,
-         output wire S,
-         output wire Cout
-       );
+        input wire A,
+        input wire B,
+        input wire Cin,
+        output wire S,
+        output wire Cout
+    );
 
-// TODO：你的代码实现
+    // TODO：你的代码实现
 
 endmodule