yystopf
/
riscv-lab
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

feat(csr): 增加debug用csr

This commit is contained in:
Liphen 2023-11-30 14:02:43 +08:00
parent ea283c3f20
commit 10b720d322
2 changed files with 17 additions and 11 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
chisel/playground/src/defines/isa/Instructions.scala
View File

@ -249,7 +249,9 @@ trait HasCSRConst {
// 0xB80 - 0x89F are also used as perfcnt csr
// Machine Counter Setup (not implemented)
// Debug/Trace Registers (shared with Debug Mode) (not implemented)
// Debug/Trace Registers (shared with Debug Mode) (simply implemented)
val Tselect = 0x7a0
val Tdata1 = 0x7a1
// Debug Mode Registers (not implemented)
def privEcall = 0x000.U

6
chisel/playground/src/pipeline/execute/Csr.scala
View File

@ -168,7 +168,7 @@ class Csr(implicit val config: CpuConfig) extends Module with HasCSRConst {
MaskedRegMap(Mepc, mepc),
MaskedRegMap(Mcause, mcause),
MaskedRegMap(Mtval, mtval),
MaskedRegMap(Mip, mip.asUInt, 0.U, MaskedRegMap.Unwritable)
MaskedRegMap(Mip, mip.asUInt, 0.U, MaskedRegMap.Unwritable),
// Machine Memory Protection
// MaskedRegMap(Pmpcfg0, pmpcfg0),
// MaskedRegMap(Pmpcfg1, pmpcfg1),
@ -178,6 +178,10 @@ class Csr(implicit val config: CpuConfig) extends Module with HasCSRConst {
// MaskedRegMap(PmpaddrBase + 1, pmpaddr1, pmpaddrWmask),
// MaskedRegMap(PmpaddrBase + 2, pmpaddr2, pmpaddrWmask),
// MaskedRegMap(PmpaddrBase + 3, pmpaddr3, pmpaddrWmask)
// Debug/Trace Registers (shared with Debug Mode)
MaskedRegMap(Tselect, tselect, 0.U, MaskedRegMap.Unwritable), // 用于通过 risc-v test
MaskedRegMap(Tdata1, tdata1, 0.U, MaskedRegMap.Unwritable)
) //++ perfCntsLoMapping
val priv_mode = RegInit(Priv.m) // 当前特权模式