yystopf
/
riscv-lab
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

fix(exe): 修复csr读数据问题

This commit is contained in:
Liphen 2023-11-29 21:32:17 +08:00
parent 160daec1e2
commit ea283c3f20
1 changed files with 2 additions and 2 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
chisel/playground/src/pipeline/execute/ExecuteUnit.scala
View File

@ -124,7 +124,7 @@ class ExecuteUnit(implicit val config: CpuConfig) extends Module {
io.memoryStage.inst0.inst_info := io.executeStage.inst0.inst_info
io.memoryStage.inst0.rd_info.wdata(FuType.alu) := fu.inst(0).result.alu
io.memoryStage.inst0.rd_info.wdata(FuType.mdu) := fu.inst(0).result.mdu
io.memoryStage.inst0.rd_info.wdata(FuType.csr) := io.csr.out.rdata(0)
io.memoryStage.inst0.rd_info.wdata(FuType.csr) := io.csr.out.rdata
io.memoryStage.inst0.rd_info.wdata(FuType.lsu) := 0.U
io.memoryStage.inst0.rd_info.wdata(FuType.mou) := 0.U
io.memoryStage.inst0.ex := MuxLookup(io.executeStage.inst0.inst_info.fusel, fu.inst(0).ex.out)(
@ -138,7 +138,7 @@ class ExecuteUnit(implicit val config: CpuConfig) extends Module {
io.memoryStage.inst1.inst_info := io.executeStage.inst1.inst_info
io.memoryStage.inst1.rd_info.wdata(FuType.alu) := fu.inst(1).result.alu
io.memoryStage.inst1.rd_info.wdata(FuType.mdu) := fu.inst(1).result.mdu
io.memoryStage.inst1.rd_info.wdata(FuType.csr) := io.csr.out.rdata(1)
io.memoryStage.inst1.rd_info.wdata(FuType.csr) := io.csr.out.rdata
io.memoryStage.inst1.rd_info.wdata(FuType.lsu) := 0.U
io.memoryStage.inst1.rd_info.wdata(FuType.mou) := 0.U
io.memoryStage.inst1.ex := MuxLookup(io.executeStage.inst1.inst_info.fusel, fu.inst(1).ex.out)(