diff --git a/chisel/playground/src/pipeline/execute/ExecuteUnit.scala b/chisel/playground/src/pipeline/execute/ExecuteUnit.scala
index ca4bd1d..bd4a0e8 100644
--- a/chisel/playground/src/pipeline/execute/ExecuteUnit.scala
+++ b/chisel/playground/src/pipeline/execute/ExecuteUnit.scala
@@ -124,7 +124,7 @@ class ExecuteUnit(implicit val config: CpuConfig) extends Module {
   io.memoryStage.inst0.inst_info                 := io.executeStage.inst0.inst_info
   io.memoryStage.inst0.rd_info.wdata(FuType.alu) := fu.inst(0).result.alu
   io.memoryStage.inst0.rd_info.wdata(FuType.mdu) := fu.inst(0).result.mdu
-  io.memoryStage.inst0.rd_info.wdata(FuType.csr) := io.csr.out.rdata(0)
+  io.memoryStage.inst0.rd_info.wdata(FuType.csr) := io.csr.out.rdata
   io.memoryStage.inst0.rd_info.wdata(FuType.lsu) := 0.U
   io.memoryStage.inst0.rd_info.wdata(FuType.mou) := 0.U
   io.memoryStage.inst0.ex := MuxLookup(io.executeStage.inst0.inst_info.fusel, fu.inst(0).ex.out)(
@@ -138,7 +138,7 @@ class ExecuteUnit(implicit val config: CpuConfig) extends Module {
   io.memoryStage.inst1.inst_info                 := io.executeStage.inst1.inst_info
   io.memoryStage.inst1.rd_info.wdata(FuType.alu) := fu.inst(1).result.alu
   io.memoryStage.inst1.rd_info.wdata(FuType.mdu) := fu.inst(1).result.mdu
-  io.memoryStage.inst1.rd_info.wdata(FuType.csr) := io.csr.out.rdata(1)
+  io.memoryStage.inst1.rd_info.wdata(FuType.csr) := io.csr.out.rdata
   io.memoryStage.inst1.rd_info.wdata(FuType.lsu) := 0.U
   io.memoryStage.inst1.rd_info.wdata(FuType.mou) := 0.U
   io.memoryStage.inst1.ex := MuxLookup(io.executeStage.inst1.inst_info.fusel, fu.inst(1).ex.out)(