From 10b720d3221cfecc89ea5f9c76f67405c4bbaea9 Mon Sep 17 00:00:00 2001
From: Liphen <xi.lifeng@qq.com>
Date: Thu, 30 Nov 2023 14:02:43 +0800
Subject: [PATCH] =?UTF-8?q?feat(csr):=20=E5=A2=9E=E5=8A=A0debug=E7=94=A8cs?=
 =?UTF-8?q?r?=
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---
 .../src/defines/isa/Instructions.scala        |  4 +++-
 .../playground/src/pipeline/execute/Csr.scala | 24 +++++++++++--------
 2 files changed, 17 insertions(+), 11 deletions(-)

diff --git a/chisel/playground/src/defines/isa/Instructions.scala b/chisel/playground/src/defines/isa/Instructions.scala
index 36380ff..ef5373f 100644
--- a/chisel/playground/src/defines/isa/Instructions.scala
+++ b/chisel/playground/src/defines/isa/Instructions.scala
@@ -249,7 +249,9 @@ trait HasCSRConst {
   // 0xB80 - 0x89F are also used as perfcnt csr
 
   // Machine Counter Setup (not implemented)
-  // Debug/Trace Registers (shared with Debug Mode) (not implemented)
+  // Debug/Trace Registers (shared with Debug Mode) (simply implemented)
+  val Tselect = 0x7a0
+  val Tdata1  = 0x7a1
   // Debug Mode Registers (not implemented)
 
   def privEcall  = 0x000.U
diff --git a/chisel/playground/src/pipeline/execute/Csr.scala b/chisel/playground/src/pipeline/execute/Csr.scala
index 9182431..88edf84 100644
--- a/chisel/playground/src/pipeline/execute/Csr.scala
+++ b/chisel/playground/src/pipeline/execute/Csr.scala
@@ -168,7 +168,7 @@ class Csr(implicit val config: CpuConfig) extends Module with HasCSRConst {
     MaskedRegMap(Mepc, mepc),
     MaskedRegMap(Mcause, mcause),
     MaskedRegMap(Mtval, mtval),
-    MaskedRegMap(Mip, mip.asUInt, 0.U, MaskedRegMap.Unwritable)
+    MaskedRegMap(Mip, mip.asUInt, 0.U, MaskedRegMap.Unwritable),
     // Machine Memory Protection
     // MaskedRegMap(Pmpcfg0, pmpcfg0),
     // MaskedRegMap(Pmpcfg1, pmpcfg1),
@@ -178,6 +178,10 @@ class Csr(implicit val config: CpuConfig) extends Module with HasCSRConst {
     // MaskedRegMap(PmpaddrBase + 1, pmpaddr1, pmpaddrWmask),
     // MaskedRegMap(PmpaddrBase + 2, pmpaddr2, pmpaddrWmask),
     // MaskedRegMap(PmpaddrBase + 3, pmpaddr3, pmpaddrWmask)
+
+    // Debug/Trace Registers (shared with Debug Mode)
+    MaskedRegMap(Tselect, tselect, 0.U, MaskedRegMap.Unwritable), // 用于通过 risc-v test
+    MaskedRegMap(Tdata1, tdata1, 0.U, MaskedRegMap.Unwritable)
   ) //++ perfCntsLoMapping
 
   val priv_mode = RegInit(Priv.m) // 当前特权模式
@@ -210,15 +214,15 @@ class Csr(implicit val config: CpuConfig) extends Module with HasCSRConst {
   val mem_valid     = mem_inst_info.valid
   val mem_addr      = mem_inst(31, 20)
   // 不带前缀的信号为exe阶段的信号
-  val valid         = io.executeUnit.in.valid
-  val op            = io.executeUnit.in.inst_info.op
-  val fusel         = io.executeUnit.in.inst_info.fusel
-  val addr          = io.executeUnit.in.inst_info.inst(31, 20)
-  val rdata         = Wire(UInt(XLEN.W))
-  val src1          = io.executeUnit.in.src_info.src1_data
-  val csri          = ZeroExtend(io.executeUnit.in.inst_info.inst(19, 15), XLEN)
-  val exe_stall     = io.ctrl.exe_stall
-  val mem_stall     = io.ctrl.mem_stall
+  val valid     = io.executeUnit.in.valid
+  val op        = io.executeUnit.in.inst_info.op
+  val fusel     = io.executeUnit.in.inst_info.fusel
+  val addr      = io.executeUnit.in.inst_info.inst(31, 20)
+  val rdata     = Wire(UInt(XLEN.W))
+  val src1      = io.executeUnit.in.src_info.src1_data
+  val csri      = ZeroExtend(io.executeUnit.in.inst_info.inst(19, 15), XLEN)
+  val exe_stall = io.ctrl.exe_stall
+  val mem_stall = io.ctrl.mem_stall
   val wdata = LookupTree(
     op,
     List(