support u16550 drivers and based on u16550 support ch376, ec200, can

Ubiquitous/Nuttx_Fusion_XiUOS/aiit_board/xidatong-riscv64/Kconfig

@@ -5,6 +5,11 @@
 
 if ARCH_BOARD_XIDATONG_RISCV64
 
+menuconfig BSP_USING_CH376
+    depends on U16550_UART3
+    bool "Using CH376 device"
+    default n
+
 menuconfig BSP_USING_CH438
     bool "Using CH438 device"
     default n
@@ -123,4 +128,20 @@ menu "Ch438 Port 7 Configuration"
 endmenu
 
 endif # BSP_USING_CH438
+
+menuconfig BSP_USING_EC200
+    depends on U16550_UART2
+    bool "Using EC200 device"
+    default n
+
+menuconfig BSP_USING_CAN
+    depends on U16550_UART1
+    bool "Using CAN device"
+    default n
+
+menuconfig BSP_USING_ESP8266
+    depends on U16550_UART3
+    bool "Using ESP8266 device"
+    default n
+
 endif # ARCH_BOARD_XIDATONG_RISCV64

Ubiquitous/Nuttx_Fusion_XiUOS/aiit_board/xidatong-riscv64/configs/cannsh/defconfig

@@ -0,0 +1,78 @@
+#
+# This file is autogenerated: PLEASE DO NOT EDIT IT.
+#
+# You can use "make menuconfig" to make any modifications to the installed .config file.
+# You can then do "make savedefconfig" to generate a new defconfig file that includes your
+# modifications.
+#
+# CONFIG_NSH_DISABLE_LOSMART is not set
+# CONFIG_STANDARD_SERIAL is not set
+CONFIG_ADD_NUTTX_FETURES=y
+CONFIG_ARCH="risc-v"
+CONFIG_ARCH_BOARD="xidatong-riscv64"
+CONFIG_ARCH_BOARD_XIDATONG_RISCV64=y
+CONFIG_ARCH_CHIP="k210"
+CONFIG_ARCH_CHIP_K210=y
+CONFIG_ARCH_INTERRUPTSTACK=2048
+CONFIG_ARCH_RISCV=y
+CONFIG_ARCH_STACKDUMP=y
+CONFIG_BINFMT_DISABLE=y
+CONFIG_BOARD_LOOPSPERMSEC=46000
+CONFIG_BUILTIN=y
+CONFIG_DEBUG_FULLOPT=y
+CONFIG_DEBUG_SYMBOLS=y
+CONFIG_EXAMPLES_HELLO=y
+CONFIG_IDLETHREAD_STACKSIZE=2048
+CONFIG_INIT_ENTRYPOINT="nsh_main"
+CONFIG_INIT_STACKSIZE=3072
+CONFIG_INTELHEX_BINARY=y
+CONFIG_LIBC_PERROR_STDOUT=y
+CONFIG_LIBC_STRERROR=y
+CONFIG_NSH_ARCHINIT=y
+CONFIG_NSH_BUILTIN_APPS=y
+CONFIG_NSH_DISABLE_IFUPDOWN=y
+CONFIG_NSH_DISABLE_MKDIR=y
+CONFIG_NSH_DISABLE_RM=y
+CONFIG_NSH_DISABLE_RMDIR=y
+CONFIG_NSH_DISABLE_UMOUNT=y
+CONFIG_NSH_READLINE=y
+CONFIG_NSH_STRERROR=y
+CONFIG_PREALLOC_TIMERS=4
+CONFIG_RAM_SIZE=2097152
+CONFIG_RAM_START=0x80400000
+CONFIG_RAW_BINARY=y
+CONFIG_READLINE_CMD_HISTORY=y
+CONFIG_READLINE_CMD_HISTORY_LEN=100
+CONFIG_READLINE_CMD_HISTORY_LINELEN=120
+CONFIG_RR_INTERVAL=200
+CONFIG_SCHED_WAITPID=y
+CONFIG_STACK_COLORATION=y
+CONFIG_START_DAY=28
+CONFIG_START_MONTH=12
+CONFIG_START_YEAR=2019
+CONFIG_SYSTEM_NSH=y
+CONFIG_TASK_NAME_SIZE=20
+CONFIG_TESTING_GETPRIME=y
+CONFIG_UART0_SERIAL_CONSOLE=y
+CONFIG_READLINE_TABCOMPLETION=y
+CONFIG_SCHED_HPWORK=y
+CONFIG_DEV_GPIO=y
+CONFIG_BOARDCTL_RESET=y
+CONFIG_U16550_UART=y
+CONFIG_U16550_UART1=y
+CONFIG_U16550_UART1_BASE=0x50230000
+CONFIG_U16550_UART1_CLOCK=195000000
+CONFIG_U16550_UART1_IRQ=38
+CONFIG_U16550_UART1_BAUD=9600
+CONFIG_U16550_UART1_PARITY=0
+CONFIG_U16550_UART1_BITS=8
+CONFIG_U16550_UART1_2STOP=0
+CONFIG_U16550_UART1_RXBUFSIZE=256
+CONFIG_U16550_UART1_TXBUFSIZE=256
+CONFIG_U16550_NO_SERIAL_CONSOLE=y
+CONFIG_U16550_SUPRESS_INITIAL_CONFIG=y
+CONFIG_SERIAL_UART_ARCH_MMIO=y
+CONFIG_U16550_REGINCR=4
+CONFIG_U16550_REGWIDTH=32
+CONFIG_U16550_ADDRWIDTH=32
+CONFIG_BSP_USING_CAN=y

Ubiquitous/Nuttx_Fusion_XiUOS/aiit_board/xidatong-riscv64/configs/ch376nsh/defconfig

@@ -0,0 +1,78 @@
+#
+# This file is autogenerated: PLEASE DO NOT EDIT IT.
+#
+# You can use "make menuconfig" to make any modifications to the installed .config file.
+# You can then do "make savedefconfig" to generate a new defconfig file that includes your
+# modifications.
+#
+# CONFIG_NSH_DISABLE_LOSMART is not set
+# CONFIG_STANDARD_SERIAL is not set
+CONFIG_ADD_NUTTX_FETURES=y
+CONFIG_ARCH="risc-v"
+CONFIG_ARCH_BOARD="xidatong-riscv64"
+CONFIG_ARCH_BOARD_XIDATONG_RISCV64=y
+CONFIG_ARCH_CHIP="k210"
+CONFIG_ARCH_CHIP_K210=y
+CONFIG_ARCH_INTERRUPTSTACK=2048
+CONFIG_ARCH_RISCV=y
+CONFIG_ARCH_STACKDUMP=y
+CONFIG_BINFMT_DISABLE=y
+CONFIG_BOARD_LOOPSPERMSEC=46000
+CONFIG_BUILTIN=y
+CONFIG_DEBUG_FULLOPT=y
+CONFIG_DEBUG_SYMBOLS=y
+CONFIG_EXAMPLES_HELLO=y
+CONFIG_IDLETHREAD_STACKSIZE=2048
+CONFIG_INIT_ENTRYPOINT="nsh_main"
+CONFIG_INIT_STACKSIZE=3072
+CONFIG_INTELHEX_BINARY=y
+CONFIG_LIBC_PERROR_STDOUT=y
+CONFIG_LIBC_STRERROR=y
+CONFIG_NSH_ARCHINIT=y
+CONFIG_NSH_BUILTIN_APPS=y
+CONFIG_NSH_DISABLE_IFUPDOWN=y
+CONFIG_NSH_DISABLE_MKDIR=y
+CONFIG_NSH_DISABLE_RM=y
+CONFIG_NSH_DISABLE_RMDIR=y
+CONFIG_NSH_DISABLE_UMOUNT=y
+CONFIG_NSH_READLINE=y
+CONFIG_NSH_STRERROR=y
+CONFIG_PREALLOC_TIMERS=4
+CONFIG_RAM_SIZE=2097152
+CONFIG_RAM_START=0x80400000
+CONFIG_RAW_BINARY=y
+CONFIG_READLINE_CMD_HISTORY=y
+CONFIG_READLINE_CMD_HISTORY_LEN=100
+CONFIG_READLINE_CMD_HISTORY_LINELEN=120
+CONFIG_RR_INTERVAL=200
+CONFIG_SCHED_WAITPID=y
+CONFIG_STACK_COLORATION=y
+CONFIG_START_DAY=28
+CONFIG_START_MONTH=12
+CONFIG_START_YEAR=2019
+CONFIG_SYSTEM_NSH=y
+CONFIG_TASK_NAME_SIZE=20
+CONFIG_TESTING_GETPRIME=y
+CONFIG_UART0_SERIAL_CONSOLE=y
+CONFIG_READLINE_TABCOMPLETION=y
+CONFIG_SCHED_HPWORK=y
+CONFIG_DEV_GPIO=y
+CONFIG_BOARDCTL_RESET=y
+CONFIG_U16550_UART=y
+CONFIG_U16550_UART3=y
+CONFIG_U16550_UART3_BASE=0x50230000
+CONFIG_U16550_UART3_CLOCK=195000000
+CONFIG_U16550_UART3_IRQ=40
+CONFIG_U16550_UART3_BAUD=115200
+CONFIG_U16550_UART3_PARITY=0
+CONFIG_U16550_UART3_BITS=8
+CONFIG_U16550_UART3_2STOP=0
+CONFIG_U16550_UART3_RXBUFSIZE=256
+CONFIG_U16550_UART3_TXBUFSIZE=256
+CONFIG_U16550_NO_SERIAL_CONSOLE=y
+CONFIG_U16550_SUPRESS_INITIAL_CONFIG=y
+CONFIG_SERIAL_UART_ARCH_MMIO=y
+CONFIG_U16550_REGINCR=4
+CONFIG_U16550_REGWIDTH=32
+CONFIG_U16550_ADDRWIDTH=32
+CONFIG_BSP_USING_CH376=y

Ubiquitous/Nuttx_Fusion_XiUOS/aiit_board/xidatong-riscv64/configs/ec200nsh/defconfig

@@ -0,0 +1,78 @@
+#
+# This file is autogenerated: PLEASE DO NOT EDIT IT.
+#
+# You can use "make menuconfig" to make any modifications to the installed .config file.
+# You can then do "make savedefconfig" to generate a new defconfig file that includes your
+# modifications.
+#
+# CONFIG_NSH_DISABLE_LOSMART is not set
+# CONFIG_STANDARD_SERIAL is not set
+CONFIG_ADD_NUTTX_FETURES=y
+CONFIG_ARCH="risc-v"
+CONFIG_ARCH_BOARD="xidatong-riscv64"
+CONFIG_ARCH_BOARD_XIDATONG_RISCV64=y
+CONFIG_ARCH_CHIP="k210"
+CONFIG_ARCH_CHIP_K210=y
+CONFIG_ARCH_INTERRUPTSTACK=2048
+CONFIG_ARCH_RISCV=y
+CONFIG_ARCH_STACKDUMP=y
+CONFIG_BINFMT_DISABLE=y
+CONFIG_BOARD_LOOPSPERMSEC=46000
+CONFIG_BUILTIN=y
+CONFIG_DEBUG_FULLOPT=y
+CONFIG_DEBUG_SYMBOLS=y
+CONFIG_EXAMPLES_HELLO=y
+CONFIG_IDLETHREAD_STACKSIZE=2048
+CONFIG_INIT_ENTRYPOINT="nsh_main"
+CONFIG_INIT_STACKSIZE=3072
+CONFIG_INTELHEX_BINARY=y
+CONFIG_LIBC_PERROR_STDOUT=y
+CONFIG_LIBC_STRERROR=y
+CONFIG_NSH_ARCHINIT=y
+CONFIG_NSH_BUILTIN_APPS=y
+CONFIG_NSH_DISABLE_IFUPDOWN=y
+CONFIG_NSH_DISABLE_MKDIR=y
+CONFIG_NSH_DISABLE_RM=y
+CONFIG_NSH_DISABLE_RMDIR=y
+CONFIG_NSH_DISABLE_UMOUNT=y
+CONFIG_NSH_READLINE=y
+CONFIG_NSH_STRERROR=y
+CONFIG_PREALLOC_TIMERS=4
+CONFIG_RAM_SIZE=2097152
+CONFIG_RAM_START=0x80400000
+CONFIG_RAW_BINARY=y
+CONFIG_READLINE_CMD_HISTORY=y
+CONFIG_READLINE_CMD_HISTORY_LEN=100
+CONFIG_READLINE_CMD_HISTORY_LINELEN=120
+CONFIG_RR_INTERVAL=200
+CONFIG_SCHED_WAITPID=y
+CONFIG_STACK_COLORATION=y
+CONFIG_START_DAY=28
+CONFIG_START_MONTH=12
+CONFIG_START_YEAR=2019
+CONFIG_SYSTEM_NSH=y
+CONFIG_TASK_NAME_SIZE=20
+CONFIG_TESTING_GETPRIME=y
+CONFIG_UART0_SERIAL_CONSOLE=y
+CONFIG_READLINE_TABCOMPLETION=y
+CONFIG_SCHED_HPWORK=y
+CONFIG_DEV_GPIO=y
+CONFIG_BOARDCTL_RESET=y
+CONFIG_U16550_UART=y
+CONFIG_U16550_UART2=y
+CONFIG_U16550_UART2_BASE=0x50220000
+CONFIG_U16550_UART2_CLOCK=195000000
+CONFIG_U16550_UART2_IRQ=39
+CONFIG_U16550_UART2_BAUD=115200
+CONFIG_U16550_UART2_PARITY=0
+CONFIG_U16550_UART2_BITS=8
+CONFIG_U16550_UART2_2STOP=0
+CONFIG_U16550_UART2_RXBUFSIZE=256
+CONFIG_U16550_UART2_TXBUFSIZE=256
+CONFIG_U16550_NO_SERIAL_CONSOLE=y
+CONFIG_U16550_SUPRESS_INITIAL_CONFIG=y
+CONFIG_SERIAL_UART_ARCH_MMIO=y
+CONFIG_U16550_REGINCR=4
+CONFIG_U16550_REGWIDTH=32
+CONFIG_U16550_ADDRWIDTH=32
+CONFIG_BSP_USING_EC200=y

Ubiquitous/Nuttx_Fusion_XiUOS/aiit_board/xidatong-riscv64/src/Makefile

@@ -46,4 +46,16 @@ ifeq ($(CONFIG_BSP_USING_CH438),y)
 CSRCS += k210_ch438.c ch438_demo.c
 endif
 
+ifeq ($(CONFIG_BSP_USING_CH376),y)
+CSRCS += k210_ch376.c ch376_demo.c
+endif
+
+ifeq ($(CONFIG_BSP_USING_EC200),y)
+CSRCS += k210_ec200.c ec200_demo.c
+endif
+
+ifeq ($(CONFIG_BSP_USING_CAN),y)
+CSRCS += k210_can.c can_demo.c
+endif
+
 include $(TOPDIR)/boards/Board.mk

Ubiquitous/Nuttx_Fusion_XiUOS/aiit_board/xidatong-riscv64/src/can_demo.c

@@ -0,0 +1,172 @@
+/*
+* Copyright (c) 2022 AIIT XUOS Lab
+* XiUOS is licensed under Mulan PSL v2.
+* You can use this software according to the terms and conditions of the Mulan PSL v2.
+* You may obtain a copy of Mulan PSL v2 at:
+*        http://license.coscl.org.cn/MulanPSL2
+* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
+* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
+* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
+* See the Mulan PSL v2 for more details.
+*/
+
+/**
+ * @file can_demo.c
+ * @brief xidatong-riscv64 can demo
+ * @version 1.0
+ * @author AIIT XUOS Lab
+ * @date 2022.9.9
+ */
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+#include "k210_can.h"
+#include <sys/ioctl.h>
+#include "time.h"
+
+#define can_print printf
+#define CAN_DEMO_TIMEOUT 10
+#define CAN_NAME "/dev/can"
+
+
+static int can_read_with_time(int fd, char *buffer, int seconds)
+{
+    int read_size = 0;
+    time_t cur_time = time(NULL);
+    time_t last_time = cur_time;
+
+    while(cur_time < last_time + seconds)
+    {
+        read_size = read(fd, buffer, 256);
+
+        if(read_size < 0)
+        {
+            can_print("can read failed %d\n", read_size);
+            return -ETIME;
+        }
+        else if(read_size)
+        {
+            can_print("can read size %d ok!\n", read_size);
+            break;
+        }
+        cur_time = time(NULL);
+    }
+    return read_size;
+}
+
+static int can_cfg_start(int fd)
+{
+    int ret = OK;
+
+    //cmd[3]: can speed = 100K
+    //cmd[4]: 1 Byte
+    //cmd[5]: 100K
+    uint8_t cmd1[] = {0xAA, 0x55, 0xFD, 0x32, 0x01, 0x0B, 0xC4, 0x29};
+
+    //cmd[3] = 0xc8;  //serial parameter
+    //cmd[4] = 0x04;  //4 Bytes
+    //cmd[5] = 0x09;  //115200
+    //cmd[6] = 0x01;  //8
+    //cmd[7] = 0x00;  //N
+    //cmd[8] = 0x00;  //1
+    uint8_t cmd2[] = {0xAA, 0x55, 0xFD, 0xC8, 0x04, 0x09, 0x01, 0x00, 0x00, 0xD6, 0x4F};
+
+    // start config
+    k210_gpiohs_set_value(FPIOA_CAN_CFG, GPIO_PV_LOW);
+    ret = close(fd);
+    up_mdelay(1000);
+
+    // open with 9600 baudrate
+    ret = open(CAN_NAME, O_RDWR);
+    if (ret != OK)
+    {
+        can_print("Open %s device failed!\n", CAN_NAME);
+        return ret;
+    }
+
+    //initialization and config parameter
+    k210_gpiohs_set_direction(FPIOA_CAN_CFG, GPIO_DM_OUTPUT);
+    k210_gpiohs_set_value(FPIOA_CAN_CFG, GPIO_PV_LOW);
+    up_mdelay(200);
+
+    write(fd, cmd1, 8);
+    up_mdelay(1000);
+
+    write(fd, cmd2, 11);
+    return ret;
+}
+
+static int can_cfg_end(int fd)
+{
+    int ret = OK;
+
+    // manual exit configuration
+    k210_gpiohs_set_value(FPIOA_CAN_CFG, GPIO_PV_HIGH);
+
+    // close firstly
+    ret = close(fd);
+    up_mdelay(1000);
+
+    fd = open(CAN_NAME, O_RDWR);
+    if (fd < 0)
+    {
+        can_print("Open %s device failed!\n", CAN_NAME);
+        return ret;
+    }
+
+    return ret;
+}
+
+static void can_test(int fd)
+{
+    uint8_t cmd[16];
+
+    for(int i = 0; i < 5; i++)
+    {
+        cmd[0] = 0x55;
+        cmd[1] = 0x77;
+        write(fd, cmd, 2);
+        up_mdelay(200);
+
+        cmd[0] = 0x99;
+        cmd[1] = 0xBB;
+        write(fd, cmd, 2);
+        up_mdelay(200);
+    }
+}
+
+static void can_read_para(int fd)
+{
+    uint8_t cmd[] = {0xAA, 0x55, 0xFE};
+    char recv_buf[256] = {0};
+
+    k210_gpiohs_set_value(FPIOA_CAN_CFG, GPIO_PV_LOW);
+    up_mdelay(100);
+
+    write(fd, cmd, 3);
+    can_read_with_time(fd, recv_buf, CAN_DEMO_TIMEOUT);
+    up_mdelay(200);
+}
+
+void CanDemo(void)
+{
+    int fd;
+
+    can_print("start %s\n", __func__);
+
+    fd = open(CAN_NAME, O_RDWR);
+    if(fd < 0)
+    {
+        can_print("can open failed %d\n", fd);
+        return;
+    }
+
+    can_print("open can fd = %d ok!\n", fd);
+    can_read_para(fd);
+
+    up_mdelay(1000);
+    close(fd);
+
+    can_print("end %s\n", __func__);
+}

Ubiquitous/Nuttx_Fusion_XiUOS/aiit_board/xidatong-riscv64/src/ch376_demo.c

@@ -0,0 +1,100 @@
+/*
+* Copyright (c) 2022 AIIT XUOS Lab
+* XiUOS is licensed under Mulan PSL v2.
+* You can use this software according to the terms and conditions of the Mulan PSL v2.
+* You may obtain a copy of Mulan PSL v2 at:
+*        http://license.coscl.org.cn/MulanPSL2
+* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
+* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
+* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
+* See the Mulan PSL v2 for more details.
+*/
+
+/**
+ * @file ch376_demo.c
+ * @brief xidatong-riscv64 ch376_demo.c
+ * @version 1.0
+ * @author AIIT XUOS Lab
+ * @date 2022.08.22
+ */
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+#include "k210_ch376.h"
+#include <sys/ioctl.h>
+
+#define CONFIG_DEBUG_CH376_INFO 1
+#define ch376_print printf
+
+static int ch376_test_fd = 0;
+
+void ch376_show_buf(char *str, int size, uint8_t *buf)
+{
+    ch376_print("%s size %d: ", str, size);
+    for(int i = 0; i < size; i++)
+    {
+        ch376_print("[%x] ", buf[i]);
+    }
+    ch376_print("\n");
+}
+
+static void ch376_cmd_demo(void)
+{
+    uint8_t cmd[16] = CH376_CMD_HEADER;
+    uint8_t buf[256] = {0};
+
+    cmd[2] = CH376_CMD_SET_MODE;
+    cmd[3] = CH376_CMD_USB_MODE;
+    ch376_show_buf("sending", 4, cmd);
+    write(ch376_test_fd, cmd, 4);
+    read(ch376_test_fd, buf, 1);
+    ch376_show_buf("received", 1, buf);
+    up_mdelay(1000);
+
+    cmd[2] = CH376_CMD_DISK_CONN;
+    ch376_show_buf("sending", 3, cmd);
+    write(ch376_test_fd, cmd, 3);
+    read(ch376_test_fd, buf, 1);
+    ch376_show_buf("received", 1, buf);
+    up_mdelay(1000);
+
+    cmd[2] = CH376_CMD_DISK_MOUNT;
+    ch376_show_buf("sending", 3, cmd);
+    write(ch376_test_fd, cmd, 3);
+    read(ch376_test_fd, buf, 1);
+    ch376_show_buf("received", 1, buf);
+    up_mdelay(1000);
+
+    cmd[2] = CH376_CMD_OPEN_FILE;
+    ch376_show_buf("sending", 3, cmd);
+    write(ch376_test_fd, cmd, 3);
+    read(ch376_test_fd, buf, 1);
+    ch376_show_buf("received", 1, buf);
+    up_mdelay(1000);
+
+    cmd[2] = CH376_CMD_DISK_QUERY;
+    ch376_show_buf("sending", 3, cmd);
+    write(ch376_test_fd, cmd, 3);
+    read(ch376_test_fd, buf, 1);
+    ch376_show_buf("received", 1, buf);
+    up_mdelay(1000);
+
+    cmd[2] = CH376_CMD_RD_USB;
+    ch376_show_buf("sending", 3, cmd);
+    write(ch376_test_fd, cmd, 3);
+    read(ch376_test_fd, buf, 1);
+    ch376_show_buf("received", 1, buf);
+    up_mdelay(1000);
+}
+
+void CH376Demo(void)
+{
+    ch376_test_fd = open("/dev/ch376", O_RDWR);
+
+    ch376_print("open ch376 fd = %d\n", ch376_test_fd);
+    ch376_print("start demo ...\n");
+    ch376_cmd_demo();
+    ch376_print("end demo...\n");
+}
+

Ubiquitous/Nuttx_Fusion_XiUOS/aiit_board/xidatong-riscv64/src/ec200_demo.c

@@ -0,0 +1,138 @@
+/*
+* Copyright (c) 2022 AIIT XUOS Lab
+* XiUOS is licensed under Mulan PSL v2.
+* You can use this software according to the terms and conditions of the Mulan PSL v2.
+* You may obtain a copy of Mulan PSL v2 at:
+*        http://license.coscl.org.cn/MulanPSL2
+* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
+* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
+* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
+* See the Mulan PSL v2 for more details.
+*/
+
+/**
+ * @file ec200_demo.c
+ * @brief xidatong-riscv64 ec200_demo.c
+ * @version 1.0
+ * @author AIIT XUOS Lab
+ * @date 2022.08.22
+ */
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+#include "k210_ec200.h"
+#include <sys/ioctl.h>
+#include "time.h"
+
+#define ec_print printf
+#define EC200_DEMO_TIMEOUT 10
+
+
+// first:  receive \n\rRDY\n\r
+// second: AT -> OK
+
+// APN configuration "CTNET"(中国电信)
+char *ec200_ctnet_cmd[] =
+{
+
+    "AT\r\n",
+    "AT+QICSGP=1,1,\"CTNET\",\"\",\"\",1\r\n",
+    "AT+QIACT=1\r\n",
+    "AT+QIOPEN=1,0,\"TCP\",\"121.41.20.48\",8840,0,2\r\n"
+};
+
+// APN configuration "CMNET"(中国移动)
+char *ec200_cmnet_cmd[] =
+{
+    "AT\r\n",
+    "AT+QICSGP=1,1,\"CMNET\",\"\",\"\",1\r\n",
+    "AT+QIACT=1\r\n",
+    "AT+QIOPEN=1,0,\"TCP\",\"121.41.20.48\",8840,0,2\r\n"
+};
+
+static int ec200_read_with_time(int fd, char *buffer, int seconds)
+{
+    int read_size = 0;
+    time_t cur_time = time(NULL);
+    time_t last_time = cur_time;
+
+    while(cur_time < last_time + seconds)
+    {
+        read_size = read(fd, buffer, 256);
+
+        if(read_size < 0)
+        {
+            ec_print("ec200 read failed %d\n", read_size);
+            return -ETIME;
+        }
+        else if(read_size)
+        {
+            ec_print("ec200 read size %d ok!\n", read_size);
+            break;
+        }
+        cur_time = time(NULL);
+    }
+    return read_size;
+}
+
+int ec200_check_demo(int fd, char *send_str, char *recv_str)
+{
+    int ret;
+    char buf[EC200_RECV_BUF_SIZE] = {0};
+
+    if(send_str)
+    {
+        ret = write(fd, send_str, strlen(send_str));
+
+        if(ret < 0)
+        {
+            ec_print("ec200 write failed %d\n", ret);
+            return ret;
+        }
+
+        ec_print("write %s ret = %d\n", send_str, ret);
+    }
+
+    ret = ec200_read_with_time(fd, buf, EC200_DEMO_TIMEOUT);
+    if(ret < 0)
+    {
+        ec_print("ec200 read failed %d\n", ret);
+        return ret;
+    }
+
+    ec_print("ec200 read: %s!\n", buf);
+
+    if(strstr(buf, recv_str))
+    {
+        ec_print("ec200 %s found!\n", recv_str);
+    }
+
+    return ret;
+}
+
+
+void EC200Demo(void)
+{
+    int fd;
+
+    ec_print("start %s\n", __func__);
+
+    fd = open("/dev/ec200", O_RDWR);
+    if(fd < 0)
+    {
+        ec_print("ec200 open failed %d\n", fd);
+        return;
+    }
+
+    ec200_check_demo(fd, NULL, "RDY");
+    ec200_check_demo(fd, "AT\r\n", "OK");
+    ec200_check_demo(fd, "AT+QICSGP=1,1,\"CTNET\",\"\",\"\",1\r\n", "OK");
+    ec200_check_demo(fd, "AT+QIACT=1\r\n", "OK");
+    ec200_check_demo(fd, "AT+QIOPEN=1,0,\"TCP\",\"121.41.20.48\",8840,0,2\r\n", "OK");
+
+    up_mdelay(2000);
+    close(fd);
+
+    ec_print("end %s\n", __func__);
+}

Ubiquitous/Nuttx_Fusion_XiUOS/aiit_board/xidatong-riscv64/src/k210_bringup.c

@@ -41,6 +41,24 @@
 #  include "k210_ch438.h"
 #endif
 
+#ifdef CONFIG_BSP_USING_CH376
+#  include "k210_ch376.h"
+#endif
+
+#ifdef CONFIG_BSP_USING_EC200
+#  include "k210_ec200.h"
+#endif
+
+#ifdef CONFIG_BSP_USING_CAN
+#  include "k210_can.h"
+#endif
+
+#ifdef CONFIG_BSP_USING_ESP8266
+#  include "k210_esp8266.h"
+#endif
+
+#include "k210_sysctl.h"
+
 /****************************************************************************
  * Public Functions
  ****************************************************************************/
@@ -85,5 +103,33 @@ int k210_bringup(void)
     }
 #endif
 
+#ifdef CONFIG_BSP_USING_CH376
+  sysctl_clock_enable(SYSCTL_CLOCK_UART3);
+  sysctl_reset(SYSCTL_RESET_UART3);
+
+  board_ch376_initialize();
+#endif
+
+#ifdef CONFIG_BSP_USING_EC200
+  k210_sysctl_init();
+  sysctl_clock_enable(SYSCTL_CLOCK_UART2);
+  sysctl_reset(SYSCTL_RESET_UART2);
+  board_ec200_initialize();
+#endif
+
+#ifdef CONFIG_BSP_USING_CAN
+  k210_sysctl_init();
+  sysctl_clock_enable(SYSCTL_CLOCK_UART1);
+  sysctl_reset(SYSCTL_RESET_UART1);
+  board_can_initialize();
+#endif
+
+#ifdef CONFIG_BSP_USING_ESP8266
+  k210_sysctl_init();
+  sysctl_clock_enable(SYSCTL_CLOCK_UART3);
+  sysctl_reset(SYSCTL_RESET_UART3);
+  board_esp8266_initialize();
+#endif
+
   return ret;
 }

Ubiquitous/Nuttx_Fusion_XiUOS/aiit_board/xidatong-riscv64/src/k210_can.c

@@ -0,0 +1,461 @@
+/*
+* Copyright (c) 2022 AIIT XUOS Lab
+* XiUOS is licensed under Mulan PSL v2.
+* You can use this software according to the terms and conditions of the Mulan PSL v2.
+* You may obtain a copy of Mulan PSL v2 at:
+*        http://license.coscl.org.cn/MulanPSL2
+* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
+* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
+* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
+* See the Mulan PSL v2 for more details.
+*/
+
+/**
+* @file k210_can.c
+* @brief support to register can pointer and function
+* @version 1.0
+* @author AIIT XUOS Lab
+* @date 2022-07-20
+*/
+
+#include <nuttx/fs/fs.h>
+#include <nuttx/wqueue.h>
+#include <sys/poll.h>
+#include "ctype.h"
+#include "k210_can.h"
+
+#define ec_print printf
+
+/******************************************************************************/
+
+struct can_dev_s g_candev;
+static char *can_dev_name = "/dev/can";
+
+/******************************************************************************/
+
+void can_print_buf(int size, uint8_t *buf)
+{
+    char ch[10] = {0};
+    char temp[256] = {0};
+
+    if(size >= 256)
+        size = 256;
+
+    for(int i = 0; i < size; i++)
+    {
+        if(buf[i] == '\r')
+        {
+            strcat(temp, "\\r");
+        }
+        else if(buf[i] == '\n')
+        {
+            strcat(temp, "\\n");
+        }
+        else if(isascii(buf[i]))
+        {
+            snprintf(ch, sizeof(ch), "%c", buf[i]);
+            strcat(temp, ch);
+        }
+        else
+        {
+            snprintf(ch, sizeof(ch), "%#x ", buf[i]);
+            strcat(temp, ch);
+        }
+    }
+    if(size)
+        ec_print("can read %d data: %s\n", size, temp);
+}
+
+int can_read_buf(void *dev, int *size, uint8_t *buf)
+{
+    uart_dev_t *uart_dev = (uart_dev_t *)dev;
+    int cur_size = uart_dev->recv.head - uart_dev->recv.tail;
+    *size = *size > cur_size ? cur_size : *size;
+    memcpy(buf, uart_dev->recv.buffer, *size);
+    uart_dev->recv.head = uart_dev->recv.tail;
+    can_print_buf(*size, buf);
+    return *size;
+}
+
+/****************************************************************************
+ * Name: can_data_work
+ *
+ * Description:
+ *   thread task can_data_work
+ *
+ ****************************************************************************/
+static FAR void can_data_work(FAR void *arg)
+{
+    struct can_dev_s *can_dev = (struct can_dev_s *)arg;
+    uart_dev_t *uart_dev = can_dev->uart_dev;
+    nxsem_wait(&can_dev->waitsem);
+    can_dev->recv_size = CAN_RECV_BUF_SIZE;
+    can_read_buf(uart_dev, &can_dev->recv_size, can_dev->recv_buf);
+    work_queue(HPWORK, &can_dev->irqwork, can_data_work, can_dev, CAN_INCREMENT);
+//    caninfo("uart size %d ok!\n", can_dev->recv_size);
+}
+
+static int can_bringup(struct can_dev_s *dev)
+{
+//    struct can_dev_s *can_dev = &g_candev;
+
+    dev->uart_fd = open(dev->dev_name, O_RDWR);
+
+    caninfo("open %s fd = %d\n", dev->dev_name, dev->uart_fd);
+
+    work_queue(HPWORK, &dev->irqwork, can_data_work, dev, CAN_INCREMENT);
+    return OK;
+}
+
+static int can_write_config(struct can_dev_s *dev)
+{
+    return OK;
+}
+
+static int can_shutdown(struct can_dev_s *dev)
+{
+    close(dev->uart_fd);
+    return OK;
+}
+
+static int can_open(FAR struct file *filep)
+{
+    FAR struct inode *inode;
+    FAR struct can_dev_s *priv;
+
+    uint8_t ref_cnt;
+
+    int ret;
+
+    DEBUGASSERT(filep);
+    inode = filep->f_inode;
+    DEBUGASSERT(inode && inode->i_private);
+
+    priv  = (FAR struct can_dev_s *)inode->i_private;
+
+    /* Get exclusive access to the driver data structure */
+    ret = nxsem_wait(&priv->devsem);
+
+    if(ret < 0)
+    {
+        canerr("ERROR: nxsem_wait failed: %d\n", ret);
+        return ret;
+    }
+
+    /* Increment the reference count */
+    ref_cnt = priv->crefs + 1;
+
+    if(ref_cnt == 0)
+    {
+        /* More than 255 opens; uint8_t overflows to zero */
+        nxsem_post(&priv->devsem);
+        return -EMFILE;
+    }
+
+    /* When the reference increments to 1, this is the first open event
+     * on the driver.. and the time when we must initialize the driver.
+     */
+
+    if(ref_cnt == 1)
+    {
+        ret = can_bringup(priv);
+
+        if(ret < 0)
+        {
+            canerr("ERROR: can_bringup failed: %d\n", ret);
+            nxsem_post(&priv->devsem);
+            return ret;
+        }
+
+        ret = can_write_config(priv);
+
+        if(ret < 0)
+        {
+            canerr("ERROR: can_write_config failed: %d\n", ret);
+            nxsem_post(&priv->devsem);
+            return ret;
+        }
+    }
+
+    /* Save the new open count on success */
+    priv->crefs = ref_cnt;
+
+    nxsem_post(&priv->devsem);
+    return ret;
+}
+
+/****************************************************************************
+ * Name: can_close
+ ****************************************************************************/
+
+static int can_close(FAR struct file *filep)
+{
+    FAR struct inode *inode;
+    FAR struct can_dev_s *priv;
+
+    int ret;
+
+    DEBUGASSERT(filep);
+    inode = filep->f_inode;
+    DEBUGASSERT(inode && inode->i_private);
+
+    priv  = (FAR struct can_dev_s *)inode->i_private;
+
+    /* Get exclusive access to the driver data structure */
+    ret = nxsem_wait(&priv->devsem);
+
+    if(ret < 0)
+    {
+        canerr("ERROR: nxsem_wait failed: %d\n", ret);
+        return ret;
+    }
+
+    /* Decrement the reference count unless it would decrement a negative
+     * value.
+     */
+
+    if(priv->crefs >= 1)
+    {
+        priv->crefs--;
+    }
+
+    /* When the count decrements to zero, there are no further open references
+     * to the driver and it can be uninitialized.
+     */
+
+    if(priv->crefs == 0)
+    {
+        can_shutdown(priv);
+    }
+
+    nxsem_post(&priv->devsem);
+    return OK;
+}
+
+/****************************************************************************
+ * Name: can_read
+ ****************************************************************************/
+
+static ssize_t can_read(FAR struct file *filep, FAR char *buffer, size_t len)
+{
+    FAR struct inode *inode;
+    FAR struct can_dev_s *priv;
+    int ret, buf_size = len;
+
+    DEBUGASSERT(filep);
+    inode = filep->f_inode;
+    DEBUGASSERT(inode && inode->i_private);
+
+    priv  = (FAR struct can_dev_s *)inode->i_private;
+
+    ret = nxsem_wait(&priv->devsem);
+
+    if(ret < 0)
+    {
+        canerr("ERROR: nxsem_wait failed: %d\n", ret);
+        return ret;
+    }
+
+    buf_size = len > priv->recv_size ? priv->recv_size : len;
+    memcpy(buffer, priv->recv_buf, buf_size);
+    nxsem_post(&priv->devsem);
+    return ret;
+}
+
+
+/****************************************************************************
+ * Name: can_write
+ ****************************************************************************/
+
+static ssize_t can_write(FAR struct file *filep, FAR const char *buffer, size_t len)
+{
+    FAR struct inode *inode;
+    FAR struct can_dev_s  *priv;
+    int ret;
+    DEBUGASSERT(filep);
+    inode = filep->f_inode;
+    DEBUGASSERT(inode && inode->i_private);
+    priv  = (FAR struct can_dev_s *)inode->i_private;
+
+    /* Get exclusive access to the driver data structure */
+    ret = nxsem_wait(&priv->devsem);
+
+    if(ret < 0)
+    {
+        canerr("ERROR: nxsem_wait failed: %d\n", ret);
+        return ret;
+    }
+
+    ret = write(priv->uart_fd, buffer, len);
+    caninfo("write fd %d len %ld ret = %d\n", priv->uart_fd, len, ret);
+    nxsem_post(&priv->devsem);
+    return ret;
+}
+
+/****************************************************************************
+ * Name: can_ioctl
+ ****************************************************************************/
+
+static int can_ioctl(FAR struct file *filep, int cmd, unsigned long arg)
+{
+    FAR struct inode *inode;
+    FAR struct can_dev_s *priv;
+    FAR uint32_t *ptr;
+
+    int ret;
+
+    DEBUGASSERT(filep);
+    inode = filep->f_inode;
+    DEBUGASSERT(inode && inode->i_private);
+
+    priv  = (FAR struct can_dev_s *)inode->i_private;
+
+    /* Get exclusive access to the driver data structure */
+    ret = nxsem_wait(&priv->devsem);
+
+    if(ret < 0)
+    {
+        canerr("ERROR: nxsem_wait failed: %d\n", ret);
+        return ret;
+    }
+
+    /* Process the IOCTL by command */
+
+    switch(cmd)
+    {
+        case CANIOC_SETFREQUENCY:  /* arg: Pointer to uint32_t frequency value */
+            ptr = (FAR uint32_t *)((uintptr_t)arg);
+            DEBUGASSERT(priv->config != NULL && ptr != NULL);
+            break;
+
+        default:
+            ret = -ENOTTY;
+            break;
+    }
+
+    nxsem_post(&priv->devsem);
+    return ret;
+}
+
+/****************************************************************************
+ * Name: can_poll
+ ****************************************************************************/
+
+static int can_poll(FAR struct file *filep, FAR struct pollfd *fds, bool setup)
+{
+    FAR struct inode *inode;
+    FAR struct can_dev_s *priv;
+
+    int ret;
+
+    caninfo("setup: %d\n", (int)setup);
+
+    DEBUGASSERT(filep && fds);
+    inode = filep->f_inode;
+    DEBUGASSERT(inode && inode->i_private);
+
+    priv  = (FAR struct can_dev_s *)inode->i_private;
+
+    /* Are we setting up the poll?  Or tearing it down? */
+    ret = nxsem_wait(&priv->devsem);
+
+    if(ret < 0)
+    {
+        canerr("ERROR: nxsem_wait failed: %d\n", ret);
+        return ret;
+    }
+
+    if(setup)
+    {
+        /* Ignore waits that do not include POLLIN */
+        if((fds->events & POLLIN) == 0)
+        {
+            canerr("ERROR: Missing POLLIN: revents: %08x\n", fds->revents);
+            nxsem_post(&priv->devsem);
+            return -EDEADLK;
+        }
+        can_notify(priv->uart_dev);
+    }
+    else if(fds->priv)
+    {
+        /* This is a request to tear down the poll. */
+        struct pollfd **slot = (struct pollfd **)fds->priv;
+        DEBUGASSERT(slot != NULL);
+        /* Remove all memory of the poll setup */
+        *slot                = NULL;
+        fds->priv            = NULL;
+    }
+
+    nxsem_post(&priv->devsem);
+    return ret;
+}
+
+
+static const struct file_operations can_fops =
+{
+    can_open,    /* open */
+    can_close,   /* close */
+    can_read,    /* read */
+    can_write,   /* write */
+    NULL,          /* seek */
+    can_ioctl,   /* ioctl */
+    can_poll     /* poll */
+};
+
+
+/****************************************************************************
+ * Name: can_register
+ *
+ * Description:
+ *   Register /dev/ext_uartN
+ *
+ ****************************************************************************/
+static int can_register(FAR const char *devpath)
+{
+    FAR struct can_dev_s *priv = &g_candev;
+    int ret = 0;
+
+    nxsem_init(&priv->devsem, 0, 1);
+    nxsem_init(&priv->waitsem,  0, 0);
+    nxsem_set_protocol(&priv->waitsem, SEM_PRIO_NONE);
+
+    /* Register the driver */
+    ret = register_driver(devpath, &can_fops, 0666, priv);
+    if(ret < 0)
+    {
+        kmm_free(priv);
+    }
+
+    return ret;
+}
+
+void can_notify(uart_dev_t *dev)
+{
+    if(dev == g_candev.uart_dev)
+        nxsem_post(&g_candev.waitsem);
+}
+
+/****************************************************************************
+ * Name: can_init
+ *
+ * Description:
+ *   Ch376 default initialization function
+ *
+ ****************************************************************************/
+
+void board_can_initialize(void)
+{
+    k210_fpioa_config(CAN_CFG_PIN, CAN_FUNC_GPIO(FPIOA_CAN_CFG));
+    k210_gpiohs_set_direction(FPIOA_CAN_CFG, GPIO_DM_OUTPUT);
+
+    fpioa_set_function(CAN_RX_PIN, FPIOA_CAN_RX);
+    fpioa_set_function(CAN_TX_PIN, FPIOA_CAN_TX);
+
+#if defined(CONFIG_U16550_UART1)
+    g_candev.dev_name = "/dev/uart1";
+    u16550_register(&g_candev.uart_dev, 1);
+    can_register(can_dev_name);
+    caninfo("dev %p ok!\n", g_candev.uart_dev);
+#endif
+}
+

Ubiquitous/Nuttx_Fusion_XiUOS/aiit_board/xidatong-riscv64/src/k210_can.h

@@ -0,0 +1,137 @@
+/*
+* Copyright (c) 2022 AIIT XUOS Lab
+* XiUOS is licensed under Mulan PSL v2.
+* You can use this software according to the terms and conditions of the Mulan PSL v2.
+* You may obtain a copy of Mulan PSL v2 at:
+*        http://license.coscl.org.cn/MulanPSL2
+* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
+* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
+* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
+* See the Mulan PSL v2 for more details.
+*/
+
+/**
+* @file k210_can.h
+* @brief define aiit-riscv64-board can function and struct
+* @version 1.0
+* @author AIIT XUOS Lab
+* @date 2022-09-7
+*/
+
+#ifndef __K210_CAN_H_
+#define __K210_CAN_H_
+
+#include <nuttx/config.h>
+#include <nuttx/kmalloc.h>
+#include <nuttx/arch.h>
+#include <nuttx/irq.h>
+#include <nuttx/pthread.h>
+#include <nuttx/semaphore.h>
+#include <nuttx/wqueue.h>
+#include <nuttx/wdog.h>
+#include <nuttx/clock.h>
+#include <nuttx/time.h>
+#include <nuttx/fs/fs.h>
+#include <nuttx/fs/ioctl.h>
+
+#include <sys/types.h>
+#include <sys/stat.h>
+#include <sys/ioctl.h>
+#include <errno.h>
+#include <stddef.h>
+#include <stdint.h>
+#include <stdio.h>
+#include <sched.h>
+#include <debug.h>
+#include <assert.h>
+#include <unistd.h>
+#include <stdbool.h>
+#include <string.h>
+#include <stdlib.h>
+#include <fcntl.h>
+
+#include <arch/board/board.h>
+#include "riscv_internal.h"
+
+#include "k210_config.h"
+#include "k210_fpioa.h"
+#include "k210_gpiohs.h"
+#include "xidatong-riscv64.h"
+#include "nuttx/serial/serial.h"
+#include "nuttx/serial/uart_16550.h"
+
+
+/* Define CH438 PIN NUM */
+#define CAN_RX_PIN     18
+#define CAN_TX_PIN     19
+#define CAN_CFG_PIN    43
+
+/* Define ch438 FPIOA NUMBER */
+#define FPIOA_CAN_RX   64
+#define FPIOA_CAN_TX   65
+#define FPIOA_CAN_CFG  4
+
+#define CAN_FUNC_GPIO(n)  ((K210_IO_FUNC_GPIOHS0 + n) | K210_IOFLAG_GPIOHS)
+
+#define CANIOC_SETFREQUENCY   _CANIOC(0x0001)  /* arg: Pointer to uint32_t frequency value */
+#define CANIOC_GETFREQUENCY   _CANIOC(0x0002)  /* arg: Pointer to uint32_t frequency value */
+
+/* can debug */
+#ifdef CONFIG_DEBUG_CAN_ERROR
+#  define canerr    _err
+#else
+#  define canerr    _none
+#endif
+
+#ifdef CONFIG_DEBUG_CAN_WARN
+#  define canwarn    _warn
+#else
+#  define canwarn    _none
+#endif
+
+#ifdef CONFIG_DEBUG_CAN_INFO
+#  define caninfo    _info
+#else
+#  define caninfo    _none
+#endif
+
+#define CAN_RECV_BUF_SIZE 256
+#define CAN_INCREMENT  MSEC2TICK(33)
+
+struct can_config_s
+{
+    int (*attach)(FAR const struct can_config_s *config, xcpt_t isr,
+                  FAR void *arg);
+    void (*enable)(FAR const struct can_config_s *config, bool enable);
+    void (*clear)(FAR const struct can_config_s *config);
+
+    void (*wakeup)(FAR const struct can_config_s *config);
+    void (*nreset)(FAR const struct can_config_s *config, bool state);
+};
+
+
+struct can_dev_s
+{
+    uint8_t crefs;                          /* Number of times the device
+                                             * has been opened */
+    uint8_t nwaiters;                       /* Number of threads waiting for
+                                             * data */
+    sem_t devsem;                           /* Manages exclusive access to
+                                             * this structure */
+    sem_t waitsem;                          /* Used to wait for the
+                                             * availability of data */
+    FAR const struct can_config_s *config;  /* Board configuration data */
+    struct work_s irqwork;                  /* Supports the interrupt
+                                             * handling "bottom half" */
+    char *dev_name;
+    int uart_fd;
+    uart_dev_t *uart_dev;
+    int recv_size;
+    uint8_t recv_buf[CAN_RECV_BUF_SIZE];
+};
+
+
+void can_notify(uart_dev_t *dev);
+void board_can_initialize(void);
+
+#endif

Ubiquitous/Nuttx_Fusion_XiUOS/aiit_board/xidatong-riscv64/src/k210_ch376.c

@@ -0,0 +1,455 @@
+/*
+* Copyright (c) 2022 AIIT XUOS Lab
+* XiUOS is licensed under Mulan PSL v2.
+* You can use this software according to the terms and conditions of the Mulan PSL v2.
+* You may obtain a copy of Mulan PSL v2 at:
+*        http://license.coscl.org.cn/MulanPSL2
+* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
+* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
+* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
+* See the Mulan PSL v2 for more details.
+*/
+
+/**
+* @file k210_ch376.c
+* @brief support to register ch376 pointer and function
+* @version 1.0
+* @author AIIT XUOS Lab
+* @date 2022-07-20
+*/
+
+#include <nuttx/fs/fs.h>
+#include <nuttx/wqueue.h>
+#include <sys/poll.h>
+#include "k210_ch376.h"
+
+/******************************************************************************/
+
+#define CH376_INCREMENT  MSEC2TICK(33)
+
+struct ch376_config_s
+{
+    int (*attach)(FAR const struct ch376_config_s *config, xcpt_t isr,
+                  FAR void *arg);
+    void (*enable)(FAR const struct ch376_config_s *config, bool enable);
+    void (*clear)(FAR const struct ch376_config_s *config);
+
+    void (*wakeup)(FAR const struct ch376_config_s *config);
+    void (*nreset)(FAR const struct ch376_config_s *config, bool state);
+};
+
+#define CH376_RECV_BUF_SIZE 256
+
+struct ch376_dev_s
+{
+    uint8_t crefs;                          /* Number of times the device
+                                             * has been opened */
+    uint8_t nwaiters;                       /* Number of threads waiting for
+                                             * data */
+    sem_t devsem;                           /* Manages exclusive access to
+                                             * this structure */
+    sem_t waitsem;                          /* Used to wait for the
+                                             * availability of data */
+
+    FAR const struct ch376_config_s *config;/* Board configuration data */
+    struct work_s irqwork;                     /* Supports the interrupt
+                                             * handling "bottom half" */
+    char *dev_name;
+    int uart_fd;
+    uart_dev_t *uart_dev;
+    int recv_size;
+    uint8_t recv_buf[CH376_RECV_BUF_SIZE];
+};
+
+
+struct ch376_dev_s g_ch376dev;
+static char *ch376_dev_name = "/dev/ch376";
+
+/******************************************************************************/
+
+int ch376_read_buf(void *dev, int *size, uint8_t *buf)
+{
+    uart_dev_t *uart_dev = (uart_dev_t *)dev;
+    int cur_size = uart_dev->recv.head - uart_dev->recv.tail;
+    *size = *size > cur_size ? cur_size : *size;
+    ch376info("%s received %d\n", __func__, *size);
+    for(int i = 0; i < *size; i++)
+    {
+        ch376info("%x ", uart_dev->recv.buffer[i]);
+        buf[i] = uart_dev->recv.buffer[i];
+    }
+    ch376info("\n");
+    uart_dev->recv.head = uart_dev->recv.tail;
+    return *size;
+}
+
+/****************************************************************************
+ * Name: ch376_data_work
+ *
+ * Description:
+ *   thread task ch376_data_work
+ *
+ ****************************************************************************/
+static FAR void ch376_data_work(FAR void *arg)
+{
+    struct ch376_dev_s *ch376_dev = (struct ch376_dev_s *)arg;
+    uart_dev_t *uart_dev = ch376_dev->uart_dev;
+    nxsem_wait(&ch376_dev->waitsem);
+    ch376_dev->recv_size = CH376_RECV_BUF_SIZE;
+    ch376_read_buf(uart_dev, &ch376_dev->recv_size, ch376_dev->recv_buf);
+    work_queue(HPWORK, &ch376_dev->irqwork, ch376_data_work, ch376_dev, CH376_INCREMENT);
+    ch376info("recv size %d!\n", ch376_dev->recv_size);
+}
+
+static int ch376_bringup(struct ch376_dev_s *dev)
+{
+    dev->uart_fd = open(dev->dev_name, O_RDWR);
+    work_queue(HPWORK, &dev->irqwork, ch376_data_work, dev, CH376_INCREMENT);
+    return OK;
+}
+
+static int ch376_write_config(struct ch376_dev_s *dev)
+{
+    return OK;
+}
+
+static int ch376_shutdown(struct ch376_dev_s *dev)
+{
+    close(dev->uart_fd);
+    return OK;
+}
+
+static int ch376_open(FAR struct file *filep)
+{
+    FAR struct inode *inode;
+    FAR struct ch376_dev_s *priv;
+
+    uint8_t ref_cnt;
+
+    int ret;
+
+    DEBUGASSERT(filep);
+    inode = filep->f_inode;
+    DEBUGASSERT(inode && inode->i_private);
+
+    priv  = (FAR struct ch376_dev_s *)inode->i_private;
+
+    /* Get exclusive access to the driver data structure */
+    ret = nxsem_wait(&priv->devsem);
+
+    if(ret < 0)
+    {
+        ch376err("ERROR: nxsem_wait failed: %d\n", ret);
+        return ret;
+    }
+
+    /* Increment the reference count */
+    ref_cnt = priv->crefs + 1;
+
+    if(ref_cnt == 0)
+    {
+        /* More than 255 opens; uint8_t overflows to zero */
+        nxsem_post(&priv->devsem);
+        return -EMFILE;
+    }
+
+    /* When the reference increments to 1, this is the first open event
+     * on the driver.. and the time when we must initialize the driver.
+     */
+
+    if(ref_cnt == 1)
+    {
+        ret = ch376_bringup(priv);
+
+        if(ret < 0)
+        {
+            ch376err("ERROR: ch376_bringup failed: %d\n", ret);
+            nxsem_post(&priv->devsem);
+            return ret;
+        }
+
+        ret = ch376_write_config(priv);
+
+        if(ret < 0)
+        {
+            ch376err("ERROR: ch376_write_config failed: %d\n", ret);
+            nxsem_post(&priv->devsem);
+            return ret;
+        }
+    }
+
+    /* Save the new open count on success */
+    priv->crefs = ref_cnt;
+
+    nxsem_post(&priv->devsem);
+    return ret;
+}
+
+/****************************************************************************
+ * Name: ch376_close
+ ****************************************************************************/
+
+static int ch376_close(FAR struct file *filep)
+{
+    FAR struct inode *inode;
+    FAR struct ch376_dev_s *priv;
+
+    int ret;
+
+    DEBUGASSERT(filep);
+    inode = filep->f_inode;
+    DEBUGASSERT(inode && inode->i_private);
+
+    priv  = (FAR struct ch376_dev_s *)inode->i_private;
+
+    /* Get exclusive access to the driver data structure */
+    ret = nxsem_wait(&priv->devsem);
+
+    if(ret < 0)
+    {
+        ch376err("ERROR: nxsem_wait failed: %d\n", ret);
+        return ret;
+    }
+
+    /* Decrement the reference count unless it would decrement a negative
+     * value.
+     */
+
+    if(priv->crefs >= 1)
+    {
+        priv->crefs--;
+    }
+
+    /* When the count decrements to zero, there are no further open references
+     * to the driver and it can be uninitialized.
+     */
+
+    if(priv->crefs == 0)
+    {
+        ch376_shutdown(priv);
+    }
+
+    nxsem_post(&priv->devsem);
+    return OK;
+}
+
+/****************************************************************************
+ * Name: ch376_read
+ ****************************************************************************/
+
+static ssize_t ch376_read(FAR struct file *filep, FAR char *buffer, size_t len)
+{
+    FAR struct inode *inode;
+    FAR struct ch376_dev_s *priv;
+    int ret, buf_size = len;
+
+    DEBUGASSERT(filep);
+    inode = filep->f_inode;
+    DEBUGASSERT(inode && inode->i_private);
+
+    priv  = (FAR struct ch376_dev_s *)inode->i_private;
+
+    ret = nxsem_wait(&priv->devsem);
+
+    if(ret < 0)
+    {
+        ch376err("ERROR: nxsem_wait failed: %d\n", ret);
+        return ret;
+    }
+
+    buf_size = len > priv->recv_size ? priv->recv_size : len;
+    memcpy(buffer, priv->recv_buf, buf_size);
+    nxsem_post(&priv->devsem);
+    return ret;
+}
+
+
+/****************************************************************************
+ * Name: ch376_write
+ ****************************************************************************/
+
+static ssize_t ch376_write(FAR struct file *filep, FAR const char *buffer, size_t len)
+{
+    FAR struct inode *inode;
+    FAR struct ch376_dev_s  *priv;
+    int ret;
+    DEBUGASSERT(filep);
+    inode = filep->f_inode;
+    DEBUGASSERT(inode && inode->i_private);
+    priv  = (FAR struct ch376_dev_s *)inode->i_private;
+
+    /* Get exclusive access to the driver data structure */
+    ret = nxsem_wait(&priv->devsem);
+
+    if(ret < 0)
+    {
+        ch376err("ERROR: nxsem_wait failed: %d\n", ret);
+        return ret;
+    }
+
+    ret = write(priv->uart_fd, buffer, len);
+
+    nxsem_post(&priv->devsem);
+    return ret;
+}
+
+/****************************************************************************
+ * Name: ch376_ioctl
+ ****************************************************************************/
+
+static int ch376_ioctl(FAR struct file *filep, int cmd, unsigned long arg)
+{
+    FAR struct inode *inode;
+    FAR struct ch376_dev_s *priv;
+
+    int ret;
+
+    DEBUGASSERT(filep);
+    inode = filep->f_inode;
+    DEBUGASSERT(inode && inode->i_private);
+
+    priv  = (FAR struct ch376_dev_s *)inode->i_private;
+
+    /* Get exclusive access to the driver data structure */
+    ret = nxsem_wait(&priv->devsem);
+
+    if(ret < 0)
+    {
+        ch376err("ERROR: nxsem_wait failed: %d\n", ret);
+        return ret;
+    }
+
+    /* Process the IOCTL by command */
+
+    switch(cmd)
+    {
+        default:
+            ret = -ENOTTY;
+            break;
+    }
+
+    nxsem_post(&priv->devsem);
+    return ret;
+}
+
+/****************************************************************************
+ * Name: ch376_poll
+ ****************************************************************************/
+
+static int ch376_poll(FAR struct file *filep, FAR struct pollfd *fds, bool setup)
+{
+    FAR struct inode *inode;
+    FAR struct ch376_dev_s *priv;
+
+    int ret;
+
+    ch376info("setup: %d\n", (int)setup);
+
+    DEBUGASSERT(filep && fds);
+    inode = filep->f_inode;
+    DEBUGASSERT(inode && inode->i_private);
+
+    priv  = (FAR struct ch376_dev_s *)inode->i_private;
+
+    /* Are we setting up the poll?  Or tearing it down? */
+    ret = nxsem_wait(&priv->devsem);
+
+    if(ret < 0)
+    {
+        ch376err("ERROR: nxsem_wait failed: %d\n", ret);
+        return ret;
+    }
+
+    if(setup)
+    {
+        /* Ignore waits that do not include POLLIN */
+        if((fds->events & POLLIN) == 0)
+        {
+            ch376err("ERROR: Missing POLLIN: revents: %08x\n", fds->revents);
+            nxsem_post(&priv->devsem);
+            return -EDEADLK;
+        }
+
+        /* Should we immediately notify on any of the requested events? */
+        ch376_notify(priv->uart_dev);
+    }
+    else if(fds->priv)
+    {
+        /* This is a request to tear down the poll. */
+        struct pollfd **slot = (struct pollfd **)fds->priv;
+        DEBUGASSERT(slot != NULL);
+        /* Remove all memory of the poll setup */
+        *slot                = NULL;
+        fds->priv            = NULL;
+    }
+
+    nxsem_post(&priv->devsem);
+    return ret;
+}
+
+
+static const struct file_operations ch376_fops =
+{
+    ch376_open,    /* open */
+    ch376_close,   /* close */
+    ch376_read,    /* read */
+    ch376_write,   /* write */
+    NULL,          /* seek */
+    ch376_ioctl,   /* ioctl */
+    ch376_poll     /* poll */
+};
+
+
+/****************************************************************************
+ * Name: ch376_register
+ *
+ * Description:
+ *   Register /dev/ext_uartN
+ *
+ ****************************************************************************/
+static int ch376_register(FAR const char *devpath)
+{
+    FAR struct ch376_dev_s *priv = &g_ch376dev;
+    int ret = 0;
+
+    nxsem_init(&priv->devsem, 0, 1);
+    nxsem_init(&priv->waitsem,  0, 0);
+    nxsem_set_protocol(&priv->waitsem, SEM_PRIO_NONE);
+
+    /* Register the driver */
+    ret = register_driver(devpath, &ch376_fops, 0666, priv);
+    if(ret < 0)
+    {
+        kmm_free(priv);
+    }
+
+    return ret;
+}
+
+void ch376_notify(uart_dev_t *dev)
+{
+    if(dev == g_ch376dev.uart_dev)
+        nxsem_post(&g_ch376dev.waitsem);
+}
+
+/****************************************************************************
+ * Name: ch376_init
+ *
+ * Description:
+ *   Ch376 default initialization function
+ *
+ ****************************************************************************/
+
+void board_ch376_initialize(void)
+{
+    fpioa_set_function(CH376_TX_PIN, FPIOA_CH376_TX);
+    fpioa_set_function(CH376_RX_PIN, FPIOA_CH376_RX);
+
+#if defined(CONFIG_U16550_UART3)
+    g_ch376dev.dev_name = "/dev/uart3";
+    u16550_register(&g_ch376dev.uart_dev, 3);
+    ch376_register(ch376_dev_name);
+    ch376info("dev %p ok!\n", g_ch376dev.uart_dev);
+#endif
+}
+

Ubiquitous/Nuttx_Fusion_XiUOS/aiit_board/xidatong-riscv64/src/k210_ch376.h

@@ -0,0 +1,111 @@
+/*
+* Copyright (c) 2022 AIIT XUOS Lab
+* XiUOS is licensed under Mulan PSL v2.
+* You can use this software according to the terms and conditions of the Mulan PSL v2.
+* You may obtain a copy of Mulan PSL v2 at:
+*        http://license.coscl.org.cn/MulanPSL2
+* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
+* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
+* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
+* See the Mulan PSL v2 for more details.
+*/
+
+/**
+* @file k210_ch376.h
+* @brief define aiit-riscv64-board ch376 function and struct
+* @version 1.0
+* @author AIIT XUOS Lab
+* @date 2022-07-19
+*/
+
+#ifndef __K210_CH376_H_
+#define __K210_CH376_H_
+
+#include <nuttx/config.h>
+#include <nuttx/kmalloc.h>
+#include <nuttx/arch.h>
+#include <nuttx/irq.h>
+#include <nuttx/pthread.h>
+#include <nuttx/semaphore.h>
+#include <nuttx/wqueue.h>
+#include <nuttx/wdog.h>
+#include <nuttx/clock.h>
+#include <nuttx/time.h>
+#include <nuttx/fs/fs.h>
+#include <nuttx/fs/ioctl.h>
+
+#include <sys/types.h>
+#include <sys/stat.h>
+#include <sys/ioctl.h>
+#include <errno.h>
+#include <stddef.h>
+#include <stdint.h>
+#include <stdio.h>
+#include <sched.h>
+#include <debug.h>
+#include <assert.h>
+#include <unistd.h>
+#include <stdbool.h>
+#include <string.h>
+#include <stdlib.h>
+#include <fcntl.h>
+
+#include <arch/board/board.h>
+#include "riscv_internal.h"
+
+#include "k210_config.h"
+#include "k210_fpioa.h"
+#include "k210_gpiohs.h"
+#include "xidatong-riscv64.h"
+#include "nuttx/serial/serial.h"
+#include "nuttx/serial/uart_16550.h"
+
+
+/* Define CH438 PIN NUM */
+#define CH376_RX_PIN     22
+#define CH376_TX_PIN     23
+
+/* Define ch438 FPIOA NUMBER */
+#define FPIOA_CH376_RX   68
+#define FPIOA_CH376_TX   69
+
+#define CH376_CMD_HEADER {0x57, 0xAB}
+
+#define CH376_CMD_SIZE 256
+
+#define CH376_CMD_SET_MODE 0x15
+#define CH376_CMD_USB_MODE 0x5
+#define CH376_CMD_SDC_MODE 0x3
+
+#define CH376_CMD_RD_USB 0x27
+
+#define CH376_CMD_DISK_CONN 0x30
+#define CH376_CMD_DISK_MOUNT 0x31
+#define CH376_CMD_DISK_QUERY 0x3F
+
+#define CH376_CMD_OPEN_FILE 0x32
+
+
+/* ch376 debug */
+#ifdef CONFIG_DEBUG_CH376_ERROR
+#  define ch376err    _err
+#else
+#  define ch376err    _none
+#endif
+
+#ifdef CONFIG_DEBUG_CH376_WARN
+#  define ch376warn    _warn
+#else
+#  define ch376warn    _none
+#endif
+
+#ifdef CONFIG_DEBUG_CH376_INFO
+#  define ch376info    _info
+#else
+#  define ch376info    _none
+#endif
+
+void ch376_notify(uart_dev_t *dev);
+void board_ch376_initialize(void);
+
+#endif

Ubiquitous/Nuttx_Fusion_XiUOS/aiit_board/xidatong-riscv64/src/k210_ec200.c

@@ -0,0 +1,458 @@
+/*
+* Copyright (c) 2022 AIIT XUOS Lab
+* XiUOS is licensed under Mulan PSL v2.
+* You can use this software according to the terms and conditions of the Mulan PSL v2.
+* You may obtain a copy of Mulan PSL v2 at:
+*        http://license.coscl.org.cn/MulanPSL2
+* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
+* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
+* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
+* See the Mulan PSL v2 for more details.
+*/
+
+/**
+* @file k210_ec200.c
+* @brief support to register ch436 pointer and function
+* @version 1.0
+* @author AIIT XUOS Lab
+* @date 2022-07-20
+*/
+
+#include <nuttx/fs/fs.h>
+#include <nuttx/wqueue.h>
+#include <sys/poll.h>
+#include "ctype.h"
+#include "k210_ec200.h"
+
+#define ec_print printf
+
+/******************************************************************************/
+
+struct ec200_dev_s g_ec200dev;
+static char *ec200_dev_name = "/dev/ec200";
+
+/******************************************************************************/
+
+void ec200_print_buf(int size, uint8_t *buf)
+{
+    char ch[10] = {0};
+    char temp[256] = {0};
+
+    if(size >= 256)
+        size = 256;
+
+    for(int i = 0; i < size; i++)
+    {
+        if(buf[i] == '\r')
+        {
+            strcat(temp, "\\r");
+        }
+        else if(buf[i] == '\n')
+        {
+            strcat(temp, "\\n");
+        }
+        else if(isascii(buf[i]))
+        {
+            snprintf(ch, sizeof(ch), "%c", buf[i]);
+            strcat(temp, ch);
+        }
+        else
+        {
+            snprintf(ch, sizeof(ch), "%#x ", buf[i]);
+            strcat(temp, ch);
+        }
+    }
+    if(size)
+        ec_print("ec200 read %d data: %s\n", size, temp);
+}
+
+int ec200_read_buf(void *dev, int *size, uint8_t *buf)
+{
+    uart_dev_t *uart_dev = (uart_dev_t *)dev;
+    int cur_size = uart_dev->recv.head - uart_dev->recv.tail;
+    *size = *size > cur_size ? cur_size : *size;
+    memcpy(buf, uart_dev->recv.buffer, *size);
+    uart_dev->recv.head = uart_dev->recv.tail;
+    ec200_print_buf(*size, buf);
+    return *size;
+}
+
+/****************************************************************************
+ * Name: ec200_data_work
+ *
+ * Description:
+ *   thread task ec200_data_work
+ *
+ ****************************************************************************/
+static FAR void ec200_data_work(FAR void *arg)
+{
+    struct ec200_dev_s *ec200_dev = (struct ec200_dev_s *)arg;
+    uart_dev_t *uart_dev = ec200_dev->uart_dev;
+    nxsem_wait(&ec200_dev->waitsem);
+    ec200_dev->recv_size = EC200_RECV_BUF_SIZE;
+    ec200_read_buf(uart_dev, &ec200_dev->recv_size, ec200_dev->recv_buf);
+    work_queue(HPWORK, &ec200_dev->irqwork, ec200_data_work, ec200_dev, EC200_INCREMENT);
+//    ec200info("uart size %d ok!\n", ec200_dev->recv_size);
+}
+
+static int ec200_bringup(struct ec200_dev_s *dev)
+{
+//    struct ec200_dev_s *ec200_dev = &g_ec200dev;
+
+    dev->uart_fd = open(dev->dev_name, O_RDWR);
+
+    ec200info("open %s fd = %d\n", dev->dev_name, dev->uart_fd);
+
+    work_queue(HPWORK, &dev->irqwork, ec200_data_work, dev, EC200_INCREMENT);
+    return OK;
+}
+
+static int ec200_write_config(struct ec200_dev_s *dev)
+{
+    return OK;
+}
+
+static int ec200_shutdown(struct ec200_dev_s *dev)
+{
+    close(dev->uart_fd);
+    return OK;
+}
+
+static int ec200_open(FAR struct file *filep)
+{
+    FAR struct inode *inode;
+    FAR struct ec200_dev_s *priv;
+
+    uint8_t ref_cnt;
+
+    int ret;
+
+    DEBUGASSERT(filep);
+    inode = filep->f_inode;
+    DEBUGASSERT(inode && inode->i_private);
+
+    priv  = (FAR struct ec200_dev_s *)inode->i_private;
+
+    /* Get exclusive access to the driver data structure */
+    ret = nxsem_wait(&priv->devsem);
+
+    if(ret < 0)
+    {
+        ec200err("ERROR: nxsem_wait failed: %d\n", ret);
+        return ret;
+    }
+
+    /* Increment the reference count */
+    ref_cnt = priv->crefs + 1;
+
+    if(ref_cnt == 0)
+    {
+        /* More than 255 opens; uint8_t overflows to zero */
+        nxsem_post(&priv->devsem);
+        return -EMFILE;
+    }
+
+    /* When the reference increments to 1, this is the first open event
+     * on the driver.. and the time when we must initialize the driver.
+     */
+
+    if(ref_cnt == 1)
+    {
+        ret = ec200_bringup(priv);
+
+        if(ret < 0)
+        {
+            ec200err("ERROR: ec200_bringup failed: %d\n", ret);
+            nxsem_post(&priv->devsem);
+            return ret;
+        }
+
+        ret = ec200_write_config(priv);
+
+        if(ret < 0)
+        {
+            ec200err("ERROR: ec200_write_config failed: %d\n", ret);
+            nxsem_post(&priv->devsem);
+            return ret;
+        }
+    }
+
+    /* Save the new open count on success */
+    priv->crefs = ref_cnt;
+
+    nxsem_post(&priv->devsem);
+    return ret;
+}
+
+/****************************************************************************
+ * Name: ec200_close
+ ****************************************************************************/
+
+static int ec200_close(FAR struct file *filep)
+{
+    FAR struct inode *inode;
+    FAR struct ec200_dev_s *priv;
+
+    int ret;
+
+    DEBUGASSERT(filep);
+    inode = filep->f_inode;
+    DEBUGASSERT(inode && inode->i_private);
+
+    priv  = (FAR struct ec200_dev_s *)inode->i_private;
+
+    /* Get exclusive access to the driver data structure */
+    ret = nxsem_wait(&priv->devsem);
+
+    if(ret < 0)
+    {
+        ec200err("ERROR: nxsem_wait failed: %d\n", ret);
+        return ret;
+    }
+
+    /* Decrement the reference count unless it would decrement a negative
+     * value.
+     */
+
+    if(priv->crefs >= 1)
+    {
+        priv->crefs--;
+    }
+
+    /* When the count decrements to zero, there are no further open references
+     * to the driver and it can be uninitialized.
+     */
+
+    if(priv->crefs == 0)
+    {
+        ec200_shutdown(priv);
+    }
+
+    nxsem_post(&priv->devsem);
+    return OK;
+}
+
+/****************************************************************************
+ * Name: ec200_read
+ ****************************************************************************/
+
+static ssize_t ec200_read(FAR struct file *filep, FAR char *buffer, size_t len)
+{
+    FAR struct inode *inode;
+    FAR struct ec200_dev_s *priv;
+    int ret, buf_size = len;
+
+    DEBUGASSERT(filep);
+    inode = filep->f_inode;
+    DEBUGASSERT(inode && inode->i_private);
+
+    priv  = (FAR struct ec200_dev_s *)inode->i_private;
+
+    ret = nxsem_wait(&priv->devsem);
+
+    if(ret < 0)
+    {
+        ec200err("ERROR: nxsem_wait failed: %d\n", ret);
+        return ret;
+    }
+
+    buf_size = len > priv->recv_size ? priv->recv_size : len;
+    memcpy(buffer, priv->recv_buf, buf_size);
+    nxsem_post(&priv->devsem);
+    return ret;
+}
+
+
+/****************************************************************************
+ * Name: ec200_write
+ ****************************************************************************/
+
+static ssize_t ec200_write(FAR struct file *filep, FAR const char *buffer, size_t len)
+{
+    FAR struct inode *inode;
+    FAR struct ec200_dev_s  *priv;
+    int ret;
+    DEBUGASSERT(filep);
+    inode = filep->f_inode;
+    DEBUGASSERT(inode && inode->i_private);
+    priv  = (FAR struct ec200_dev_s *)inode->i_private;
+
+    /* Get exclusive access to the driver data structure */
+    ret = nxsem_wait(&priv->devsem);
+
+    if(ret < 0)
+    {
+        ec200err("ERROR: nxsem_wait failed: %d\n", ret);
+        return ret;
+    }
+
+    ret = write(priv->uart_fd, buffer, len);
+    ec200info("write fd %d len %ld ret = %d\n", priv->uart_fd, len, ret);
+    nxsem_post(&priv->devsem);
+    return ret;
+}
+
+/****************************************************************************
+ * Name: ec200_ioctl
+ ****************************************************************************/
+
+static int ec200_ioctl(FAR struct file *filep, int cmd, unsigned long arg)
+{
+    FAR struct inode *inode;
+    FAR struct ec200_dev_s *priv;
+
+    int ret;
+
+    DEBUGASSERT(filep);
+    inode = filep->f_inode;
+    DEBUGASSERT(inode && inode->i_private);
+
+    priv  = (FAR struct ec200_dev_s *)inode->i_private;
+
+    /* Get exclusive access to the driver data structure */
+    ret = nxsem_wait(&priv->devsem);
+
+    if(ret < 0)
+    {
+        ec200err("ERROR: nxsem_wait failed: %d\n", ret);
+        return ret;
+    }
+
+    /* Process the IOCTL by command */
+
+    switch(cmd)
+    {
+//        case TSIOC_SETFREQUENCY:  /* arg: Pointer to uint32_t frequency value */
+//            FAR uint32_t *ptr = (FAR uint32_t *)((uintptr_t)arg);
+//            DEBUGASSERT(priv->config != NULL && ptr != NULL);
+//            break;
+
+        default:
+            ret = -ENOTTY;
+            break;
+    }
+
+    nxsem_post(&priv->devsem);
+    return ret;
+}
+
+/****************************************************************************
+ * Name: ec200_poll
+ ****************************************************************************/
+
+static int ec200_poll(FAR struct file *filep, FAR struct pollfd *fds, bool setup)
+{
+    FAR struct inode *inode;
+    FAR struct ec200_dev_s *priv;
+
+    int ret;
+
+    ec200info("setup: %d\n", (int)setup);
+
+    DEBUGASSERT(filep && fds);
+    inode = filep->f_inode;
+    DEBUGASSERT(inode && inode->i_private);
+
+    priv  = (FAR struct ec200_dev_s *)inode->i_private;
+
+    /* Are we setting up the poll?  Or tearing it down? */
+    ret = nxsem_wait(&priv->devsem);
+
+    if(ret < 0)
+    {
+        ec200err("ERROR: nxsem_wait failed: %d\n", ret);
+        return ret;
+    }
+
+    if(setup)
+    {
+        /* Ignore waits that do not include POLLIN */
+        if((fds->events & POLLIN) == 0)
+        {
+            ec200err("ERROR: Missing POLLIN: revents: %08x\n", fds->revents);
+            nxsem_post(&priv->devsem);
+            return -EDEADLK;
+        }
+        ec200_notify(priv->uart_dev);
+    }
+    else if(fds->priv)
+    {
+        /* This is a request to tear down the poll. */
+        struct pollfd **slot = (struct pollfd **)fds->priv;
+        DEBUGASSERT(slot != NULL);
+        /* Remove all memory of the poll setup */
+        *slot                = NULL;
+        fds->priv            = NULL;
+    }
+
+    nxsem_post(&priv->devsem);
+    return ret;
+}
+
+
+static const struct file_operations ec200_fops =
+{
+    ec200_open,    /* open */
+    ec200_close,   /* close */
+    ec200_read,    /* read */
+    ec200_write,   /* write */
+    NULL,          /* seek */
+    ec200_ioctl,   /* ioctl */
+    ec200_poll     /* poll */
+};
+
+
+/****************************************************************************
+ * Name: ec200_register
+ *
+ * Description:
+ *   Register /dev/ext_uartN
+ *
+ ****************************************************************************/
+static int ec200_register(FAR const char *devpath)
+{
+    FAR struct ec200_dev_s *priv = &g_ec200dev;
+    int ret = 0;
+
+    nxsem_init(&priv->devsem, 0, 1);
+    nxsem_init(&priv->waitsem,  0, 0);
+    nxsem_set_protocol(&priv->waitsem, SEM_PRIO_NONE);
+
+    /* Register the driver */
+    ret = register_driver(devpath, &ec200_fops, 0666, priv);
+    if(ret < 0)
+    {
+        kmm_free(priv);
+    }
+
+    return ret;
+}
+
+void ec200_notify(uart_dev_t *dev)
+{
+    if(dev == g_ec200dev.uart_dev)
+        nxsem_post(&g_ec200dev.waitsem);
+}
+
+/****************************************************************************
+ * Name: ec200_init
+ *
+ * Description:
+ *   Ch376 default initialization function
+ *
+ ****************************************************************************/
+
+void board_ec200_initialize(void)
+{
+#if defined(CONFIG_U16550_UART2)
+
+    fpioa_set_function(EC200_RX_PIN, FPIOA_EC200_RX);
+    fpioa_set_function(EC200_TX_PIN, FPIOA_EC200_TX);
+
+    g_ec200dev.dev_name = "/dev/uart2";
+    u16550_register(&g_ec200dev.uart_dev, 2);
+    ec200_register(ec200_dev_name);
+    ec200info("dev %p ok!\n", g_ec200dev.uart_dev);
+#endif
+}
+

Ubiquitous/Nuttx_Fusion_XiUOS/aiit_board/xidatong-riscv64/src/k210_ec200.h

@@ -0,0 +1,132 @@
+/*
+* Copyright (c) 2022 AIIT XUOS Lab
+* XiUOS is licensed under Mulan PSL v2.
+* You can use this software according to the terms and conditions of the Mulan PSL v2.
+* You may obtain a copy of Mulan PSL v2 at:
+*        http://license.coscl.org.cn/MulanPSL2
+* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
+* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
+* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
+* See the Mulan PSL v2 for more details.
+*/
+
+/**
+* @file k210_ec200.h
+* @brief define aiit-riscv64-board ec200 function and struct
+* @version 1.0
+* @author AIIT XUOS Lab
+* @date 2022-09-7
+*/
+
+#ifndef __K210_EC200_H_
+#define __K210_EC200_H_
+
+#include <nuttx/config.h>
+#include <nuttx/kmalloc.h>
+#include <nuttx/arch.h>
+#include <nuttx/irq.h>
+#include <nuttx/pthread.h>
+#include <nuttx/semaphore.h>
+#include <nuttx/wqueue.h>
+#include <nuttx/wdog.h>
+#include <nuttx/clock.h>
+#include <nuttx/time.h>
+#include <nuttx/fs/fs.h>
+#include <nuttx/fs/ioctl.h>
+
+#include <sys/types.h>
+#include <sys/stat.h>
+#include <sys/ioctl.h>
+#include <errno.h>
+#include <stddef.h>
+#include <stdint.h>
+#include <stdio.h>
+#include <sched.h>
+#include <debug.h>
+#include <assert.h>
+#include <unistd.h>
+#include <stdbool.h>
+#include <string.h>
+#include <stdlib.h>
+#include <fcntl.h>
+
+#include <arch/board/board.h>
+#include "riscv_internal.h"
+
+#include "k210_config.h"
+#include "k210_fpioa.h"
+#include "k210_gpiohs.h"
+#include "xidatong-riscv64.h"
+#include "nuttx/serial/serial.h"
+#include "nuttx/serial/uart_16550.h"
+
+
+/* Define CH438 PIN NUM */
+#define EC200_RX_PIN     21
+#define EC200_TX_PIN     20
+
+/* Define ch438 FPIOA NUMBER */
+#define FPIOA_EC200_RX   66
+#define FPIOA_EC200_TX   67
+
+
+/* ec200 debug */
+#ifdef CONFIG_DEBUG_EC200_ERROR
+#  define ec200err    _err
+#else
+#  define ec200err    _none
+#endif
+
+#ifdef CONFIG_DEBUG_EC200_WARN
+#  define ec200warn    _warn
+#else
+#  define ec200warn    _none
+#endif
+
+#ifdef CONFIG_DEBUG_EC200_INFO
+#  define ec200info    _info
+#else
+#  define ec200info    _none
+#endif
+
+#define EC200_RECV_BUF_SIZE 256
+#define EC200_INCREMENT  MSEC2TICK(33)
+
+struct ec200_config_s
+{
+    int (*attach)(FAR const struct ec200_config_s *config, xcpt_t isr,
+                  FAR void *arg);
+    void (*enable)(FAR const struct ec200_config_s *config, bool enable);
+    void (*clear)(FAR const struct ec200_config_s *config);
+
+    void (*wakeup)(FAR const struct ec200_config_s *config);
+    void (*nreset)(FAR const struct ec200_config_s *config, bool state);
+};
+
+
+struct ec200_dev_s
+{
+    uint8_t crefs;                          /* Number of times the device
+                                             * has been opened */
+    uint8_t nwaiters;                       /* Number of threads waiting for
+                                             * data */
+    sem_t devsem;                           /* Manages exclusive access to
+                                             * this structure */
+    sem_t waitsem;                          /* Used to wait for the
+                                             * availability of data */
+
+    FAR const struct ec200_config_s *config;/* Board configuration data */
+    struct work_s irqwork;                     /* Supports the interrupt
+                                             * handling "bottom half" */
+    char *dev_name;
+    int uart_fd;
+    uart_dev_t *uart_dev;
+    int recv_size;
+    uint8_t recv_buf[EC200_RECV_BUF_SIZE];
+};
+
+
+void ec200_notify(uart_dev_t *dev);
+void board_ec200_initialize(void);
+
+#endif

Ubiquitous/Nuttx_Fusion_XiUOS/app_match_nuttx/apps/nshlib/nsh.h

@@ -1454,6 +1454,22 @@ int nsh_foreach_var(FAR struct nsh_vtbl_s *vtbl, nsh_foreach_var_t cb,
   int cmd_Ch438(FAR struct nsh_vtbl_s *vtbl, int argc, char **argv);
 #endif
 
+#if defined(CONFIG_BSP_USING_CH376) && !defined(CONFIG_NSH_DISABLE_CH376)
+  int cmd_Ch376(FAR struct nsh_vtbl_s *vtbl, int argc, char **argv);
+#endif
+
+#if defined(CONFIG_BSP_USING_EC200) && !defined(CONFIG_NSH_DISABLE_EC200)
+  int cmd_EC200(FAR struct nsh_vtbl_s *vtbl, int argc, char **argv);
+#endif
+
+#if defined(CONFIG_BSP_USING_CAN) && !defined(CONFIG_NSH_DISABLE_CAN)
+  int cmd_CAN(FAR struct nsh_vtbl_s *vtbl, int argc, char **argv);
+#endif
+
+#if defined(CONFIG_BSP_USING_ESP8266) && !defined(CONFIG_NSH_DISABLE_ESP8266)
+  int cmd_Esp8266(FAR struct nsh_vtbl_s *vtbl, int argc, char **argv);
+#endif
+
 #if defined(CONFIG_K210_LCD) && !defined(CONFIG_NSH_DISABLE_LCD)
   int cmd_Lcd(FAR struct nsh_vtbl_s *vtbl, int argc, char **argv);
 #endif

Ubiquitous/Nuttx_Fusion_XiUOS/app_match_nuttx/apps/nshlib/nsh_Applicationscmd.c

@@ -51,6 +51,58 @@ int cmd_Ch438(FAR struct nsh_vtbl_s *vtbl, int argc, char **argv)
 }
 #endif
 
+/****************************************************************************
+ * Name: cmd_Ch376
+ ****************************************************************************/
+#if defined(CONFIG_BSP_USING_CH376) && !defined(CONFIG_NSH_DISABLE_CH376)
+extern void CH376Demo(void);
+int cmd_Ch376(FAR struct nsh_vtbl_s *vtbl, int argc, char **argv)
+{
+    nsh_output(vtbl, "Hello, ch376!\n");
+    CH376Demo();
+    return OK;
+}
+#endif
+
+/****************************************************************************
+ * Name: cmd_Ch376
+ ****************************************************************************/
+#if defined(CONFIG_BSP_USING_EC200) && !defined(CONFIG_NSH_DISABLE_EC200)
+extern void EC200Demo(void);
+int cmd_EC200(FAR struct nsh_vtbl_s *vtbl, int argc, char **argv)
+{
+    nsh_output(vtbl, "Hello, EC200!\n");
+    EC200Demo();
+    return OK;
+}
+#endif
+
+/****************************************************************************
+ * Name: cmd_CAN
+ ****************************************************************************/
+#if defined(CONFIG_BSP_USING_CAN) && !defined(CONFIG_NSH_DISABLE_CAN)
+extern void CanDemo(void);
+int cmd_CAN(FAR struct nsh_vtbl_s *vtbl, int argc, char **argv)
+{
+    nsh_output(vtbl, "Hello, CAN!\n");
+    CanDemo();
+    return OK;
+}
+#endif
+
+/****************************************************************************
+ * Name: cmd_Esp8266
+ ****************************************************************************/
+#if defined(CONFIG_BSP_USING_ESP8266) && !defined(CONFIG_NSH_DISABLE_ESP8266)
+extern void Esp8266Demo(void);
+int cmd_Esp8266(FAR struct nsh_vtbl_s *vtbl, int argc, char **argv)
+{
+    nsh_output(vtbl, "Hello, Esp8266!\n");
+    Esp8266Demo();
+    return OK;
+}
+#endif
+
 /****************************************************************************
  * Name: cmd_lcd
  ****************************************************************************/

Ubiquitous/Nuttx_Fusion_XiUOS/app_match_nuttx/apps/nshlib/nsh_command.c

@@ -597,11 +597,27 @@ static const struct cmdmap_s g_cmdmap[] =
 #endif
 
 #if defined(CONFIG_BSP_USING_CH438) && !defined(CONFIG_NSH_DISABLE_CH438)
-  { "ch438",    cmd_Ch438,     1, 1, "[ch438 demo cmd.]" },
+  { "ch438",    cmd_Ch438,    1, 1, "[ch438 demo cmd.]" },
+#endif
+
+#if defined(CONFIG_BSP_USING_CH376) && !defined(CONFIG_NSH_DISABLE_CH376)
+  { "ch376",    cmd_Ch376,    1, 1, "[ch376 demo cmd.]" },
+#endif
+
+#if defined(CONFIG_BSP_USING_EC200) && !defined(CONFIG_NSH_DISABLE_EC200)
+  { "ec200",    cmd_EC200,    1, 1, "[ec200 demo cmd.]" },
+#endif
+
+#if defined(CONFIG_BSP_USING_CAN) && !defined(CONFIG_NSH_DISABLE_CAN)
+  { "can",      cmd_CAN,      1, 1, "[can demo cmd.]" },
+#endif
+
+#if defined(CONFIG_BSP_USING_ESP8266) && !defined(CONFIG_NSH_DISABLE_ESP8266)
+  { "esp8266",  cmd_Esp8266,  1, 1, "[can demo cmd.]" },
 #endif
 
 #if defined(CONFIG_K210_LCD) && !defined(CONFIG_NSH_DISABLE_LCD)
-  { "lcd",      cmd_Lcd,     1, 1, "[LCD demo cmd.]" },
+  { "lcd",      cmd_Lcd,      1, 1, "[LCD demo cmd.]" },
 #endif
 
 #if defined(CONFIG_APPLICATION_SENSOR_HCHO_TB600B_WQ_HCHO1OS) && !defined(CONFIG_NSH_DISABLE_HCHO_TB600B_WQ_HCHO1OS)

Ubiquitous/Nuttx_Fusion_XiUOS/app_match_nuttx/nuttx/arch/risc-v/include/k210/irq.h

@@ -0,0 +1,49 @@
+/****************************************************************************
+ * arch/risc-v/include/k210/irq.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements.  See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership.  The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License.  You may obtain a copy of the License at
+ *
+ *   http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.  See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+#ifndef __ARCH_RISCV_INCLUDE_K210_IRQ_H
+#define __ARCH_RISCV_INCLUDE_K210_IRQ_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <arch/irq.h>
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/* Map RISC-V exception code to NuttX IRQ */
+
+#ifdef CONFIG_K210_WITH_QEMU
+#define K210_IRQ_UART0    (RISCV_IRQ_MEXT + 4)
+#else
+#define K210_IRQ_UART0    (RISCV_IRQ_MEXT + 33)
+#define K210_IRQ_UART1    (RISCV_IRQ_MEXT + 11)
+#define K210_IRQ_UART2    (RISCV_IRQ_MEXT + 12)
+#define K210_IRQ_UART3    (RISCV_IRQ_MEXT + 13)
+#endif
+
+/* Total number of IRQs */
+
+#define NR_IRQS           (64 + 16 +16)
+
+#endif /* __ARCH_RISCV_INCLUDE_K210_IRQ_H */

Ubiquitous/Nuttx_Fusion_XiUOS/app_match_nuttx/nuttx/arch/risc-v/src/k210/Make.defs

@@ -55,7 +55,7 @@ endif
 # Specify our C code within this directory to be included
 CHIP_CSRCS  = k210_allocateheap.c k210_clockconfig.c
 CHIP_CSRCS += k210_irq.c k210_irq_dispatch.c k210_systemreset.c
-CHIP_CSRCS += k210_lowputc.c k210_serial.c k210_fpioa.c
+CHIP_CSRCS += k210_lowputc.c k210_serial.c k210_fpioa.c fpioa.c
 CHIP_CSRCS += k210_start.c k210_timerisr.c k210_gpiohs.c k210_gpio.c
 CHIP_CSRCS += k210_sysctl.c
 

Ubiquitous/Nuttx_Fusion_XiUOS/app_match_nuttx/nuttx/arch/risc-v/src/k210/k210_clockconfig.c

@@ -142,12 +142,18 @@ void k210_clockconfig(void)
 
 void k210_sysctl_init(void)
 {
-//    sysctl_pll_set_freq(SYSCTL_PLL0, 800000000UL);
+    sysctl_pll_set_freq(SYSCTL_PLL0, 800000000UL);
-//    sysctl_pll_set_freq(SYSCTL_PLL1, 400000000UL);
+    sysctl_pll_set_freq(SYSCTL_PLL1, 400000000UL);
-//    sysctl_pll_set_freq(SYSCTL_PLL2, 45158400UL);
+    sysctl_pll_set_freq(SYSCTL_PLL2, 45158400UL);
+
     sysctl_clock_set_threshold(SYSCTL_THRESHOLD_APB1, 2);
 
-//    sysctl_set_power_mode(SYSCTL_POWER_BANK0, SYSCTL_POWER_V18);
+    sysctl_set_power_mode(SYSCTL_POWER_BANK0, SYSCTL_POWER_V18);
-//    sysctl_set_power_mode(SYSCTL_POWER_BANK1, SYSCTL_POWER_V18);
+    sysctl_set_power_mode(SYSCTL_POWER_BANK1, SYSCTL_POWER_V18);
-//    sysctl_set_power_mode(SYSCTL_POWER_BANK2, SYSCTL_POWER_V18);
+    sysctl_set_power_mode(SYSCTL_POWER_BANK2, SYSCTL_POWER_V18);
+
+    // for IO-27/28
+    sysctl_set_power_mode(SYSCTL_POWER_BANK4, SYSCTL_POWER_V33);
+    // for IO-20~23
+    sysctl_set_power_mode(SYSCTL_POWER_BANK3, SYSCTL_POWER_V33);
 }

Ubiquitous/Nuttx_Fusion_XiUOS/app_match_nuttx/nuttx/arch/risc-v/src/k210/k210_fpioa.c

@@ -58,40 +58,6 @@ int k210_fpioa_get_io_by_function(uint8_t function)
   return -1;
 }
 
-int fpioa_set_io_pull(int number, fpioa_pull_t pull)
-{
-  /* Check parameters */
-  if (number < 0 || number >= K210_IO_NUMBER || pull >= FPIOA_PULL_MAX)
-      return -1;
-
-  /* read register */
-  uint32_t *fpioa = (uint32_t *)K210_FPIOA_BASE;
-  fpioa_io_config_t cfg = *(fpioa_io_config_t *)(&fpioa[number]);
-  uint32_t ioflags = 0x0000;
-
-  switch (pull)
-  {
-      case FPIOA_PULL_NONE:
-          cfg.pu = 0;
-          cfg.pd = 0;
-          break;
-      case FPIOA_PULL_DOWN:
-          cfg.pu = 0;
-          cfg.pd = 1;
-          break;
-      case FPIOA_PULL_UP:
-          cfg.pu = 1;
-          cfg.pd = 0;
-          break;
-      default:
-          break;
-  }
-
-  /* write register */
-  ioflags = *(uint32_t*)(&cfg);
-  putreg32(ioflags, &fpioa[number]);
-  return 0;
-}
 
 void k210_fpioa_config(uint32_t io, uint32_t ioflags)
 {

Ubiquitous/Nuttx_Fusion_XiUOS/app_match_nuttx/nuttx/arch/risc-v/src/k210/k210_fpioa.h

@@ -22,7 +22,7 @@
 * @file k210_fpioa.h
 * @brief nuttx source code
 *                https://github.com/apache/incubator-nuttx.git
-* @version 10.3.0 
+* @version 10.3.0
 * @author AIIT XUOS Lab
 * @date 2022-03-23
 */
@@ -35,6 +35,7 @@
  ****************************************************************************/
 
 #include <stdint.h>
+#include "fpioa.h"
 
 /****************************************************************************
  * Pre-processor Definitions
@@ -102,34 +103,6 @@
 #define K210_IOFLAG_GPIOHS (K210_IO_DS(0xf) | K210_IO_OUTPUT_ENABLE | \
                             K210_IO_INPUT_ENABLE | K210_IO_ST)
 
-typedef struct _fpioa_io_config
-{
-    uint32_t ch_sel : 8;  /* Channel select from 256 input. */
-    uint32_t ds : 4;      /* Driving selector. */
-    uint32_t oe_en : 1;   /* Static output enable, will AND with OE_INV. */
-    uint32_t oe_inv : 1;  /* Invert output enable. */
-    uint32_t do_sel : 1;  /* Data output select: 0 for DO, 1 for OE. */
-    uint32_t do_inv : 1;  /* Invert the result of data output select (DO_SEL). */
-    uint32_t pu : 1;      /* Pull up enable. 0 for nothing, 1 for pull up. */
-    uint32_t pd : 1;      /* Pull down enable. 0 for nothing, 1 for pull down. */
-    uint32_t resv0 : 1;   /* Reserved bits. */
-    uint32_t sl : 1;      /* Slew rate control enable. */
-    uint32_t ie_en : 1;   /* Static input enable, will AND with IE_INV. */
-    uint32_t ie_inv : 1;  /* Invert input enable. */
-    uint32_t di_inv : 1;  /* Invert Data input. */
-    uint32_t st : 1;      /* Schmitt trigger. */
-    uint32_t resv1 : 7;   /* Reserved bits. */
-    uint32_t pad_di : 1;  /* Read current IO's data input. */
-} __attribute__((packed, aligned(4))) fpioa_io_config_t;
-
-typedef enum _fpioa_pull
-{
-    FPIOA_PULL_NONE,      /* No Pull */
-    FPIOA_PULL_DOWN,      /* Pull Down */
-    FPIOA_PULL_UP,        /* Pull Up */
-    FPIOA_PULL_MAX        /* Count of pull settings */
-} fpioa_pull_t;
-
 
 /****************************************************************************
  * Public Functions Prototypes

Ubiquitous/Nuttx_Fusion_XiUOS/app_match_nuttx/nuttx/drivers/serial/Kconfig

@@ -0,0 +1,712 @@
+#
+# For a description of the syntax of this configuration file,
+# see the file kconfig-language.txt in the NuttX tools repository.
+#
+
+config ARCH_HAVE_SERIAL_TERMIOS
+	bool
+	default n
+
+menuconfig SERIAL
+	bool "Serial Driver Support"
+	default y
+	---help---
+		Front-end character drivers for chip-specific UARTs.  This provide
+		some TTY-like functionality and are commonly used (but not required
+		for) the NuttX system console.  See also include/nuttx/serial/serial.h
+
+if SERIAL
+
+config SERIAL_PM_ACTIVITY_DOMAIN
+	int "PM activity domain"
+	default 0
+	depends on PM
+	---help---
+		When characters are received on a console device, pm_activity()
+		will be called with this PM domain.
+
+config SERIAL_PM_ACTIVITY_PRIORITY
+	int "PM activity priority when receive character"
+	default 6
+	depends on PM
+	---help---
+		When characters are received on a console device, pm_activity()
+		will be called with this PM priority.
+
+config SERIAL_REMOVABLE
+	bool
+	default n
+
+config SERIAL_CONSOLE
+	bool
+	default n
+
+menuconfig U16550_UART
+	bool "16550 UART Chip support"
+	select ARCH_HAVE_SERIAL_TERMIOS
+	default n
+
+if U16550_UART
+source "drivers/serial/Kconfig-16550"
+endif
+
+#
+# MCU serial peripheral driver?
+#
+
+config OTHER_UART_SERIALDRIVER
+	bool
+	default n
+	select MCU_SERIAL
+
+config MCU_SERIAL
+	bool
+	default n
+
+config RPMSG_UART
+	bool "UART rpmsg support"
+	default n
+	depends on OPENAMP
+	select ARCH_HAVE_SERIAL_TERMIOS
+	select SERIAL_RXDMA
+	select SERIAL_TXDMA
+	select SERIAL_REMOVABLE
+	select SERIAL_IFLOWCONTROL
+
+config RPMSG_SERIALINIT
+	bool "Add dummy up_serialinit for UART rpmsg"
+	default y if !U16550_UART && !MCU_SERIAL
+	depends on RPMSG_UART
+
+#
+# Standard serial driver configuration
+#
+
+config STANDARD_SERIAL
+	bool "Enable standard \"upper-half\" serial driver"
+	default y if MCU_SERIAL
+	default n if !MCU_SERIAL
+	---help---
+		Enable the standard, upper-half serial driver used by most MCU serial peripherals.
+
+config SERIAL_NPOLLWAITERS
+	int "Number of poll threads"
+	default 4
+	---help---
+		Maximum number of threads than can be waiting for POLL events.
+		Default: 4
+
+config SERIAL_IFLOWCONTROL
+	bool
+	default n
+
+config SERIAL_RS485CONTROL
+	bool
+	default n
+	---help---
+		Use RTS pin to control RS485 direction (Asserted while transmitting).
+
+config SERIAL_OFLOWCONTROL
+	bool
+	default n
+
+config SERIAL_TXDMA
+	bool
+	default n
+
+config SERIAL_RXDMA
+	bool
+	default n
+
+config SERIAL_IFLOWCONTROL_WATERMARKS
+	bool "RX flow control watermarks"
+	default n
+	depends on SERIAL_IFLOWCONTROL
+	---help---
+		Call the "lower half" rxflowcontrol method whenever the number of
+		characters in the serial RX buffer falls above an upper water mark
+		level or below a lower watermark level.  The default behavior is to
+		call the rxflowcontrol method only when the RX buffer is empty or
+		full.
+
+if SERIAL_IFLOWCONTROL_WATERMARKS
+
+config SERIAL_IFLOWCONTROL_LOWER_WATERMARK
+	int "RX lower Watermark (percent)"
+	default 10
+	range 1 99
+	---help---
+		Call the rxflowcontrol method then there are this amount (or or less)
+		data buffered in the serial drivers RX buffer.  This is expressed
+		as a percentage of the total size of the RX buffer which may vary
+		from instance-to-instance.
+
+config SERIAL_IFLOWCONTROL_UPPER_WATERMARK
+	int "RX upper Watermark (percent)"
+	default 90
+	range 1 99
+	---help---
+		Call the rxflowcontrol method then there are this amount (or more)
+		data buffered in the serial drivers RX buffer.  This is expressed
+		as a percentage of the total size of the RX buffer which may vary
+		from instance-to-instance.
+
+endif # SERIAL_IFLOWCONTROL_WATERMARKS
+
+config SERIAL_TIOCSERGSTRUCT
+	bool "Support TIOCSERGSTRUCT"
+	default n
+	depends on DEBUG_FEATURES && (MCU_SERIAL || U16550_UART)
+	---help---
+		As a debug option, many serial bottom half drivers support the TIOCSERGSTRUCT
+		that allows you to get the internal driver data structure.  By default, this
+		IOCTL is not supported in order to reduce footprint.  But if (1) the driver
+		supports the TIOCSERGSTRUCT ioctl, and (2) this option is selected, then
+		support for the TIOCSERGSTRUCT will be enabled.
+
+config SERIAL_TERMIOS
+	bool "Serial TERMIOS support"
+	depends on ARCH_HAVE_SERIAL_TERMIOS
+	default n
+	---help---
+		Serial driver supports termios.h interfaces (tcsetattr, tcflush, etc.).
+		If this is not defined, then the terminal settings (baud, parity, etc).
+		are not configurable at runtime; serial streams cannot be flushed, etc..
+
+config TTY_LAUNCH
+	bool "Enable feature TTY launch program"
+	default n
+	---help---
+		If select this, then user can launch a program with a special input.
+
+if TTY_LAUNCH
+
+config TTY_LAUNCH_CHAR
+	hex "TTY launch program characters"
+	default 0x12
+	---help---
+		Use Ctrl-R 0x12 inputs to determine whether launch a program
+
+config TTY_LAUNCH_ARGS
+	string "TTY launch argument list"
+	default INIT_ARGS
+	---help---
+		The argument list for user applications. e.g.:
+		  "\"arg1\",\"arg2\",\"arg3\""
+
+config TTY_LAUNCH_PRIORITY
+	int "TTY launch program priority"
+	default INIT_PRIORITY
+
+config TTY_LAUNCH_STACKSIZE
+	hex "TTY launch program stack size"
+	default INIT_STACKSIZE
+
+choice
+	prompt "TTY launch method"
+	default TTY_LAUNCH_ENTRY
+
+config TTY_LAUNCH_ENTRY
+	bool "TTY launch program"
+
+config TTY_LAUNCH_FILE
+	bool "TTY launch file"
+	depends on !BINFMT_DISABLE
+
+endchoice
+
+config TTY_LAUNCH_ENTRYPOINT
+	string "TTY launch program entry"
+	depends on TTY_LAUNCH_ENTRY
+	default INIT_ENTRYPOINT
+
+config TTY_LAUNCH_ENTRYNAME
+	string "TTY launch program name"
+	depends on TTY_LAUNCH_ENTRY
+	default TTY_LAUNCH_ENTRYPOINT
+
+config TTY_LAUNCH_FILEPATH
+	string "TTY launch file path"
+	depends on TTY_LAUNCH_FILE
+	default INIT_FILEPATH
+	---help---
+		The name of the entry point for user applications.  For the example
+		applications this is of the form 'app_main' where 'app' is the application
+		name. If not defined, USER_ENTRYPOINT defaults to "main".
+
+endif # TTY_LAUNCH
+
+config TTY_FORCE_PANIC
+	bool "Enable TTY force crash"
+	default n
+	depends on DEBUG_FEATURES
+	---help---
+		This is for debugging system busyloop or deadlock, when the shell can't run,
+		then use this force crash the system to see the dumplog.
+
+config TTY_FORCE_PANIC_CHAR
+	hex "TTY force crash characters"
+	default 0x1F
+	depends on TTY_FORCE_PANIC
+	---help---
+		Use Ctrl-? 0x1F inputs to determine whether panic system
+
+config TTY_SIGINT
+	bool "Support SIGINT"
+	default n
+	---help---
+		Whether support Ctrl-c/x event.  Enabled automatically for console
+		devices.  May be enabled for other serial devices using the ISIG bit
+		in the Termios c_lflag.
+
+		REVISIT:  This implementation is compliant but incomplete.  The
+		c_lflag ISIG bit normally enables/disables INTR, QUIT, SUSP, and
+		DSUSP character processing.  The relationship between these names,
+		standard signals, and typical key presses are as follows:
+
+		  INTR   SIGINT   Ctrl-C  ETX(0x03) Interrupt
+		  KILL   SIGKILL  Ctrl-U  NAK(0x15) Kill
+		  QUIT   SIGQUIT  Ctrl-\  FS (0x1c) Quit
+		  SUSP   SIGTSTP  Ctrl-Z  SUB(0x1a) Suspend
+		  DSUSP  SIGTSTP  Ctrl-Y  EM (0x19) Delayed suspend
+
+		Additional requirements:
+		  - SIGKILL cannot be caught or ignored.  Compared to SIGTERM which
+		    is like SIGKILL but can be caught or ignored.
+		  - SIGQUIT is like SIGINT but causes generation of a core dump
+		  - SIGSTOP cannot be caught or ignored.  SIGTSTP is like SIGSTOP but
+		    can be caught or ignored.
+		  - The delayed suspend (DSUSD) is like suspend (SUPD), except that
+		    the suspension is delayed until the next read operation
+
+		Ctrl-D (EOT 0x04) normally should not generate a signal but, instead,
+		should cause an immediate End-of-File result.
+
+config TTY_SIGINT_CHAR
+	hex "Serial parse SIGINT characters"
+	default 0x03 if SERIAL_CONSOLE
+	default 0x04 if !SERIAL_CONSOLE
+	depends on TTY_SIGINT
+	---help---
+		Use ASCII 0x03 (Ctrl-c) or 0x04 (ctrl-d) inputs to determine whether
+		to send a SIGINT event.  Other characters may also be selected.
+
+		REVISIT:  Traditionally Ctrl-C would generate SIGINT.  Ctrl-D is the
+		End-of-File character that should close the stream.
+
+config TTY_SIGTSTP
+	bool "Support SIGTSTP"
+	default n
+	---help---
+		Whether support Ctrl-z event.  Enabled automatically for console
+		devices.  May be enabled for other serial devices using the ISIG bit
+		in the Termios c_lflag.
+
+		REVISIT:  This implementation is compliant but incomplete.  The
+		c_lflag ISIG bit normally enables/disables INTR, QUIT, SUSP, and
+		DSUSP character processing.  The relationship between these names,
+		standard signals, and typical key presses are as follows:
+
+		  INTR   SIGINT   Ctrl-C  ETX(0x03) Interrupt
+		  KILL   SIGKILL  Ctrl-U  NAK(0x15) Kill
+		  QUIT   SIGQUIT  Ctrl-\  FS (0x1c) Quit
+		  SUSP   SIGTSTP  Ctrl-Z  SUB(0x1a) Suspend
+		  DSUSP  SIGTSTP  Ctrl-Y  EM (0x19) Delayed suspend
+
+		Additional requirements:
+		  - SIGKILL cannot be caught or ignored.  Compared to SIGTERM which
+		    is like SIGKILL but can be caught or ignored.
+		  - SIGQUIT is like SIGINT but causes generation of a core dump
+		  - SIGSTOP cannot be caught or ignored.  SIGTSTP is like SIGSTOP but
+		    can be caught or ignored.
+		  - The delayed suspend (DSUSD) is like suspend (SUPD), except that
+		    the suspension is delayed until the next read operation
+
+config TTY_SIGTSTP_CHAR
+	hex "Serial parse SIGTSTP characters"
+	default 0x1a
+	depends on TTY_SIGTSTP
+	---help---
+		Use ASCII 0x1a (Ctrl-z) input to determine whether to send a SIGTSTP
+		event.  Other characters may also be selected.
+
+#
+# Serial console selection
+#
+
+choice
+	prompt "Serial console"
+	default NO_SERIAL_CONSOLE if !OTHER_UART_SERIALDRIVER
+	default OTHER_SERIAL_CONSOLE if OTHER_UART_SERIALDRIVER
+	depends on MCU_SERIAL
+	#depends on DEV_CONSOLE - We may have serial console with no file system at all
+
+config UART_SERIAL_CONSOLE
+	bool "UART"
+	depends on UART_SERIALDRIVER
+	select SERIAL_CONSOLE
+
+config UART0_SERIAL_CONSOLE
+	bool "UART0"
+	depends on UART0_SERIALDRIVER
+	select SERIAL_CONSOLE
+
+config USART0_SERIAL_CONSOLE
+	bool "USART0"
+	depends on USART0_SERIALDRIVER
+	select SERIAL_CONSOLE
+
+config UART1_SERIAL_CONSOLE
+	bool "UART1"
+	depends on UART1_SERIALDRIVER
+	select SERIAL_CONSOLE
+
+config USART1_SERIAL_CONSOLE
+	bool "USART1"
+	depends on USART1_SERIALDRIVER
+	select SERIAL_CONSOLE
+
+config UART2_SERIAL_CONSOLE
+	bool "UART2"
+	depends on UART2_SERIALDRIVER
+	select SERIAL_CONSOLE
+
+config USART2_SERIAL_CONSOLE
+	bool "USART2"
+	depends on USART2_SERIALDRIVER
+	select SERIAL_CONSOLE
+
+config UART3_SERIAL_CONSOLE
+	bool "UART3"
+	depends on UART3_SERIALDRIVER
+	select SERIAL_CONSOLE
+
+config USART3_SERIAL_CONSOLE
+	bool "USART3"
+	depends on USART3_SERIALDRIVER
+	select SERIAL_CONSOLE
+
+config UART4_SERIAL_CONSOLE
+	bool "UART4"
+	depends on UART4_SERIALDRIVER
+	select SERIAL_CONSOLE
+
+config USART4_SERIAL_CONSOLE
+	bool "USART4"
+	depends on USART4_SERIALDRIVER
+	select SERIAL_CONSOLE
+
+config UART5_SERIAL_CONSOLE
+	bool "UART5"
+	depends on UART5_SERIALDRIVER
+	select SERIAL_CONSOLE
+
+config USART5_SERIAL_CONSOLE
+	bool "USART5"
+	depends on USART5_SERIALDRIVER
+	select SERIAL_CONSOLE
+
+config UART6_SERIAL_CONSOLE
+	bool "UART6"
+	depends on UART6_SERIALDRIVER
+	select SERIAL_CONSOLE
+
+config USART6_SERIAL_CONSOLE
+	bool "USART6"
+	depends on USART6_SERIALDRIVER
+	select SERIAL_CONSOLE
+
+config UART7_SERIAL_CONSOLE
+	bool "UART7"
+	depends on UART7_SERIALDRIVER
+	select SERIAL_CONSOLE
+
+config USART7_SERIAL_CONSOLE
+	bool "USART7"
+	depends on USART7_SERIALDRIVER
+	select SERIAL_CONSOLE
+
+config UART8_SERIAL_CONSOLE
+	bool "UART8"
+	depends on UART8_SERIALDRIVER
+	select SERIAL_CONSOLE
+
+config USART8_SERIAL_CONSOLE
+	bool "USART8"
+	depends on USART8_SERIALDRIVER
+	select SERIAL_CONSOLE
+
+config USART9_SERIAL_CONSOLE
+	bool "USART8"
+	depends on USART9_SERIALDRIVER
+	select SERIAL_CONSOLE
+
+config LPUART0_SERIAL_CONSOLE
+	bool "LPUART0"
+	depends on LPUART0_SERIALDRIVER
+	select SERIAL_CONSOLE
+
+config LPUART1_SERIAL_CONSOLE
+	bool "LPUART1"
+	depends on LPUART1_SERIALDRIVER
+	select SERIAL_CONSOLE
+
+config LPUART2_SERIAL_CONSOLE
+	bool "LPUART2"
+	depends on LPUART2_SERIALDRIVER
+	select SERIAL_CONSOLE
+
+config LPUART3_SERIAL_CONSOLE
+	bool "LPUART3"
+	depends on LPUART3_SERIALDRIVER
+	select SERIAL_CONSOLE
+
+config LPUART4_SERIAL_CONSOLE
+	bool "LPUART4"
+	depends on LPUART4_SERIALDRIVER
+	select SERIAL_CONSOLE
+
+config LPUART5_SERIAL_CONSOLE
+	bool "LPUART5"
+	depends on LPUART5_SERIALDRIVER
+	select SERIAL_CONSOLE
+
+config LPUART6_SERIAL_CONSOLE
+	bool "LPUART6"
+	depends on LPUART6_SERIALDRIVER
+	select SERIAL_CONSOLE
+
+config LPUART7_SERIAL_CONSOLE
+	bool "LPUART7"
+	depends on LPUART7_SERIALDRIVER
+	select SERIAL_CONSOLE
+
+config LPUART8_SERIAL_CONSOLE
+	bool "LPUART8"
+	depends on LPUART8_SERIALDRIVER
+	select SERIAL_CONSOLE
+
+config SCI0_SERIAL_CONSOLE
+	bool "SCI0"
+	depends on SCI0_SERIALDRIVER
+	select SERIAL_CONSOLE
+
+config SCI1_SERIAL_CONSOLE
+	bool "SCI1"
+	depends on SCI1_SERIALDRIVER
+	select SERIAL_CONSOLE
+
+config SCI2_SERIAL_CONSOLE
+	bool "SCI2"
+	depends on SCI2_SERIALDRIVER
+	select SERIAL_CONSOLE
+
+config SCI3_SERIAL_CONSOLE
+	bool "SCI3"
+	depends on SCI3_SERIALDRIVER
+	select SERIAL_CONSOLE
+
+config SCI4_SERIAL_CONSOLE
+	bool "SCI4"
+	depends on SCI4_SERIALDRIVER
+	select SERIAL_CONSOLE
+
+config SCI5_SERIAL_CONSOLE
+	bool "SCI5"
+	depends on SCI5_SERIALDRIVER
+	select SERIAL_CONSOLE
+
+config SCI6_SERIAL_CONSOLE
+	bool "SCI6"
+	depends on SCI6_SERIALDRIVER
+	select SERIAL_CONSOLE
+
+config SCI7_SERIAL_CONSOLE
+	bool "SCI7"
+	depends on SCI7_SERIALDRIVER
+	select SERIAL_CONSOLE
+
+config SCI8_SERIAL_CONSOLE
+	bool "SCI8"
+	depends on SCI8_SERIALDRIVER
+	select SERIAL_CONSOLE
+
+config SCI9_SERIAL_CONSOLE
+	bool "SCI9"
+	depends on SCI9_SERIALDRIVER
+	select SERIAL_CONSOLE
+
+config SCI10_SERIAL_CONSOLE
+	bool "SCI10"
+	depends on SCI10_SERIALDRIVER
+	select SERIAL_CONSOLE
+
+config SCI11_SERIAL_CONSOLE
+	bool "SCI11"
+	depends on SCI11_SERIALDRIVER
+	select SERIAL_CONSOLE
+
+config SCI12_SERIAL_CONSOLE
+	bool "SCI12"
+	depends on SCI12_SERIALDRIVER
+	select SERIAL_CONSOLE
+
+config OTHER_SERIAL_CONSOLE
+	bool "Other serial console"
+	select SERIAL_CONSOLE
+
+config NO_SERIAL_CONSOLE
+	bool "No serial console"
+
+endchoice
+
+#
+# U[S]ARTn_XYZ settings for MCU serial drivers
+#
+
+menu "UART Configuration"
+	depends on UART_SERIALDRIVER
+
+config UART_RXBUFSIZE
+	int "Receive buffer size"
+	default 256
+	---help---
+		Characters are buffered as they are received. This specifies
+		the size of the receive buffer.
+
+config UART_TXBUFSIZE
+	int "Transmit buffer size"
+	default 256
+	---help---
+		Characters are buffered before being sent.  This specifies
+		the size of the transmit buffer.
+
+config UART_BAUD
+	int "BAUD rate"
+	default 115200
+	---help---
+		The configured BAUD of the UART.
+
+config UART_BITS
+	int "Character size"
+	default 8
+	---help---
+		The number of bits.  Must be either 7 or 8.
+
+config UART_PARITY
+	int "Parity setting"
+	default 0
+	range 0 2
+	---help---
+		0=no parity, 1=odd parity, 2=even parity
+
+config UART_2STOP
+	int "use 2 stop bits"
+	default 0
+	---help---
+		1=Two stop bits
+
+config UART_IFLOWCONTROL
+	bool "UART RTS flow control"
+	default n
+	select SERIAL_IFLOWCONTROL
+	---help---
+		Enable UART RTS flow control
+
+config UART_OFLOWCONTROL
+	bool "UART CTS flow control"
+	default n
+	select SERIAL_OFLOWCONTROL
+	---help---
+		Enable UART CTS flow control
+
+config UART_TXDMA
+	bool "UART Tx DMA support"
+	default n
+	select SERIAL_TXDMA
+	---help---
+		Enable Tx DMA transfers on UART
+
+config UART_RXDMA
+	bool "UART Rx DMA support"
+	default n
+	select SERIAL_RXDMA
+	---help---
+		Enable Rx DMA transfers on UART
+
+endmenu
+
+source "drivers/serial/Kconfig-uart"
+source "drivers/serial/Kconfig-lpuart"
+source "drivers/serial/Kconfig-usart"
+source "drivers/serial/Kconfig-sci"
+
+menuconfig PSEUDOTERM
+	bool "Pseudo-Terminal (PTY) support"
+	default n
+	select PIPES
+	select ARCH_HAVE_SERIAL_TERMIOS
+	---help---
+		Enable support support for master and slave pseudo-terminal devices.
+
+if PSEUDOTERM
+
+config PSEUDOTERM_SUSV1
+	bool "SUSv1 style"
+	default y
+	---help---
+		PTYs as specified in the Single Unix Specification (SUSv1).
+
+		Master: /dev/ptmx (multiplexor)
+		Slave: /dev/pts/N
+
+		Where N is the minor number
+
+config PSEUDOTERM_RXBUFSIZE
+	int "Pseudo-Terminal Rx buffer size"
+	default 256
+	---help---
+		Master-to-slave pipe buffer size.  Default: 256
+
+config PSEUDOTERM_TXBUFSIZE
+	int "Pseudo-Terminal Tx buffer size"
+	default 256
+	---help---
+		Slave-to-master pipe buffer size.  Default: 256
+
+endif # PSEUDOTERM
+
+menuconfig UART_BTH4
+	bool "BT H4 uart pseudo device"
+	default n
+	select MM_CIRCBUF
+	---help---
+		Enable support for Bluetooth H4 UART Pseudo Device(eg. /dev/ttyHCI).
+		This instantiates a serial-like interface over an existing bluetooth
+		controller via HCI interface. Useful for external Bluetooth
+		stacks working this way instead of the socket based interface.
+
+if UART_BTH4
+
+config UART_BTH4_TXBUFSIZE
+	int "BT H4 uart TX buffer size"
+	default 1024
+	---help---
+		H4 UART TX buffer size.  Default: 1024
+
+config UART_BTH4_RXBUFSIZE
+	int "BT H4 uart RX buffer size"
+	default 1024
+	---help---
+		H4 UART RX buffer size.  Default: 1024
+
+config UART_BTH4_NPOLLWAITERS
+	int "Number of poll threads"
+	default 2
+	---help---
+		Maximum number of threads than can be waiting for POLL events.
+		Default: 2
+
+endif # UART_BTH4
+
+endif # SERIAL

Ubiquitous/Nuttx_Fusion_XiUOS/app_match_nuttx/nuttx/drivers/serial/Kconfig-16550

@@ -0,0 +1,363 @@
+#
+# For a description of the syntax of this configuration file,
+# see the file kconfig-language.txt in the NuttX tools repository.
+#
+
+if U16550_UART
+
+config U16550_SERIAL_DISABLE_REORDERING
+	bool "Disable reordering of ttySx devices."
+	default n
+	---help---
+		NuttX per default reorders the serial ports (/dev/ttySx) so that the
+		console is always on /dev/ttyS0. If more than one UART is in use this
+		can, however, have the side-effect that all port mappings
+		(hardware USART1 -> /dev/ttyS0) change if the console is moved to another
+		UART.  This option disables that re-ordering for 16550 UARTs.
+
+config U16550_UART0
+	bool "16550 UART0"
+	default n
+
+if U16550_UART0
+
+config U16550_UART0_BASE
+	hex "16550 UART0 base address"
+
+config U16550_UART0_CLOCK
+	int "16550 UART0 clock"
+
+config U16550_UART0_IRQ
+	int "16550 UART0 IRQ number"
+
+config U16550_UART0_BAUD
+	int "16550 UART0 BAUD"
+	default 115200
+
+config U16550_UART0_PARITY
+	int "16550 UART0 parity"
+	default 0
+	range 0 2
+	---help---
+		16550 UART0 parity.  0=None, 1=Odd, 2=Even.  Default: None
+
+config U16550_UART0_BITS
+	int "16550 UART0 number of bits"
+	default 8
+	---help---
+		16550 UART0 number of bits.  Default: 8
+
+config U16550_UART0_2STOP
+	int "16550 UART0 two stop bits"
+	default 0
+	---help---
+		0=1 stop bit, 1=Two stop bits.  Default: 1 stop bit
+
+config U16550_UART0_RXBUFSIZE
+	int "16550 UART0 Rx buffer size"
+	default 256
+	---help---
+		16550 UART0 Rx buffer size.  Default: 256
+
+config U16550_UART0_TXBUFSIZE
+	int "16550 UART0 Tx buffer size"
+	default 256
+	---help---
+		16550 UART0 Tx buffer size.  Default: 256
+
+config U16550_UART0_IFLOWCONTROL
+	bool "16550 UART0 RTS flow control"
+	default n
+	select SERIAL_IFLOWCONTROL
+	---help---
+		Enable 16550 UART0 RTS flow control
+
+config U16550_UART0_OFLOWCONTROL
+	bool "16550 UART0 CTS flow control"
+	default n
+	select SERIAL_OFLOWCONTROL
+	---help---
+		Enable 16550 UART0 CTS flow control
+
+endif # U16550_UART0
+
+config U16550_UART1
+	bool "16550 UART1"
+	default n
+
+if U16550_UART1
+
+config U16550_UART1_BASE
+	hex "16550 UART1 base address"
+	default 0x50210000
+
+config U16550_UART1_CLOCK
+	int "16550 UART1 clock"
+	default 195000000
+
+config U16550_UART1_IRQ
+	int "16550 UART1 IRQ number"
+	default 38
+
+config U16550_UART1_BAUD
+	int "16550 UART1 BAUD"
+	default 9600
+
+config U16550_UART1_PARITY
+	int "16550 UART1 parity"
+	default 0
+	range 0 2
+	---help---
+		16550 UART1 parity.  0=None, 1=Odd, 2=Even.  Default: None
+
+config U16550_UART1_BITS
+	int "16550 UART1 number of bits"
+	default 8
+	---help---
+		16550 UART1 number of bits.  Default: 8
+
+config U16550_UART1_2STOP
+	int "16550 UART1 two stop bits"
+	default 0
+	---help---
+		0=1 stop bit, 1=Two stop bits.  Default: 1 stop bit
+
+config U16550_UART1_RXBUFSIZE
+	int "16550 UART1 Rx buffer size"
+	default 256
+	---help---
+		16550 UART1 Rx buffer size.  Default: 256
+
+config U16550_UART1_TXBUFSIZE
+	int "16550 UART1 Tx buffer size"
+	default 256
+	---help---
+		16550 UART1 Tx buffer size.  Default: 256
+
+config U16550_UART1_IFLOWCONTROL
+	bool "16550 UART1 RTS flow control"
+	default n
+	select SERIAL_IFLOWCONTROL
+	---help---
+		Enable 16550 UART1 RTS flow control
+
+config U16550_UART1_OFLOWCONTROL
+	bool "16550 UART1 CTS flow control"
+	default n
+	select SERIAL_OFLOWCONTROL
+	---help---
+		Enable 16550 UART1 CTS flow control
+
+endif # U16550_UART1
+
+config U16550_UART2
+	bool "16550 UART2"
+	default n
+
+if U16550_UART2
+
+config U16550_UART2_BASE
+	hex "16550 UART2 base address"
+	default 0x50220000
+
+config U16550_UART2_CLOCK
+	int "16550 UART2 clock"
+	default 195000000
+
+config U16550_UART2_IRQ
+	int "16550 UART2 IRQ number"
+	default 39
+
+config U16550_UART2_BAUD
+	int "16550 UART2 BAUD"
+	default 115200
+
+config U16550_UART2_PARITY
+	int "16550 UART2 parity"
+	default 0
+	range 0 2
+	---help---
+		16550 UART2 parity.  0=None, 1=Odd, 2=Even.  Default: None
+
+config U16550_UART2_BITS
+	int "16550 UART2 number of bits"
+	default 8
+	---help---
+		16550 UART2 number of bits.  Default: 8
+
+config U16550_UART2_2STOP
+	int "16550 UART2 two stop bits"
+	default 0
+	---help---
+		0=1 stop bit, 1=Two stop bits.  Default: 1 stop bit
+
+config U16550_UART2_RXBUFSIZE
+	int "16550 UART2 Rx buffer size"
+	default 256
+	---help---
+		16550 UART2 Rx buffer size.  Default: 256
+
+config U16550_UART2_TXBUFSIZE
+	int "16550 UART2 Tx buffer size"
+	default 256
+	---help---
+		16550 UART2 Tx buffer size.  Default: 256
+
+config U16550_UART2_IFLOWCONTROL
+	bool "16550 UART2 RTS flow control"
+	default n
+	select SERIAL_IFLOWCONTROL
+	---help---
+		Enable 16550 UART2 RTS flow control
+
+config U16550_UART2_OFLOWCONTROL
+	bool "16550 UART2 CTS flow control"
+	default n
+	select SERIAL_OFLOWCONTROL
+	---help---
+		Enable 16550 UART2 CTS flow control
+
+endif # U16550_UART2
+
+config U16550_UART3
+	bool "16550 UART3"
+	default n
+
+if U16550_UART3
+
+config U16550_UART3_BASE
+	hex "16550 UART3 base address"
+	default 0x50230000
+
+config U16550_UART3_CLOCK
+	int "16550 UART3 clock"
+	default 195000000
+
+config U16550_UART3_IRQ
+	int "16550 UART3 IRQ number"
+	default 40
+
+config U16550_UART3_BAUD
+	int "16550 UART3 BAUD"
+	default 115200
+
+config U16550_UART3_PARITY
+	int "16550 UART3 parity"
+	default 0
+	range 0 2
+	---help---
+		16550 UART3 parity.  0=None, 1=Odd, 2=Even.  Default: None
+
+config U16550_UART3_BITS
+	int "16550 UART3 number of bits"
+	default 8
+	---help---
+		16550 UART3 number of bits.  Default: 8
+
+config U16550_UART3_2STOP
+	int "16550 UART3 two stop bits"
+	default 0
+	---help---
+		0=1 stop bit, 1=Two stop bits.  Default: 1 stop bit
+
+config U16550_UART3_RXBUFSIZE
+	int "16550 UART3 Rx buffer size"
+	default 256
+	---help---
+		16550 UART3 Rx buffer size.  Default: 256
+
+config U16550_UART3_TXBUFSIZE
+	int "16550 UART3 Tx buffer size"
+	default 256
+	---help---
+		16550 UART3 Tx buffer size.  Default: 256
+
+config U16550_UART3_IFLOWCONTROL
+	bool "16550 UART3 RTS flow control"
+	default n
+	select SERIAL_IFLOWCONTROL
+	---help---
+		Enable 16550 UART3 RTS flow control
+
+config U16550_UART3_OFLOWCONTROL
+	bool "16550 UART3 CTS flow control"
+	default n
+	select SERIAL_OFLOWCONTROL
+	---help---
+		Enable 16550 UART3 CTS flow control
+
+endif # U16550_UART3
+
+choice
+	prompt "16550 Serial Console"
+	default U16550_NO_SERIAL_CONSOLE
+	depends on DEV_CONSOLE
+
+config U16550_UART_SERIAL_CONSOLE
+	bool "16550 UART0 serial console"
+	depends on U16550_UART
+	select SERIAL_CONSOLE
+
+config U16550_UART1_SERIAL_CONSOLE
+	bool "16550 UART1 serial console"
+	depends on U16550_UART1
+	select SERIAL_CONSOLE
+
+config U16550_UART2_SERIAL_CONSOLE
+	bool "16550 UART2 serial console"
+	depends on U16550_UART2
+	select SERIAL_CONSOLE
+
+config U16550_UART3_SERIAL_CONSOLE
+	bool "16550 UART3 serial console"
+	depends on U16550_UART3
+	select SERIAL_CONSOLE
+
+config U16550_NO_SERIAL_CONSOLE
+	bool "No 16550 serial console"
+
+endchoice # 16550 Serial Console
+
+config U16550_SUPRESS_CONFIG
+	bool "Suppress 16550 configuration"
+	default n
+
+config U16550_SUPRESS_INITIAL_CONFIG
+	bool "Suppress initial 16550 configuration"
+	depends on !16550_SUPRESS_CONFIG
+	default y
+	---help---
+		This option is useful, for example, if you are using a bootloader
+		that configures the U16550_UART.  In that case, you may want to
+		just leave the existing console configuration in place.  Default: n
+
+config SERIAL_UART_ARCH_MMIO
+	bool "Platform access register through the memory mapping"
+	default y
+
+config SERIAL_UART_ARCH_IOCTL
+	bool "Platform has own custom IOCTL"
+	default n
+
+config U16550_REGINCR
+	int "Address increment between 16550 registers"
+	default 4
+	---help---
+		The address increment between 16550 registers.  Options are 1, 2, or 4.
+		Default: 1
+
+config U16550_REGWIDTH
+	int "Bit width of 16550 registers"
+	default 32
+	---help---
+		The bit width of registers.  Options are 8, 16, or 32. Default: 8
+
+config U16550_ADDRWIDTH
+	int "Address width of 16550 registers"
+	default 32
+	---help---
+		The bit width of registers.  Options are 0, 8, 16, or 32.
+		Default: 32
+		Note: 0 means auto detect address size (uintptr_t)
+
+endif # U16550_UART

Ubiquitous/Nuttx_Fusion_XiUOS/app_match_nuttx/nuttx/drivers/serial/Make.defs

@@ -0,0 +1,57 @@
+############################################################################
+# drivers/serial/Make.defs
+#
+# Licensed to the Apache Software Foundation (ASF) under one or more
+# contributor license agreements.  See the NOTICE file distributed with
+# this work for additional information regarding copyright ownership.  The
+# ASF licenses this file to you under the Apache License, Version 2.0 (the
+# "License"); you may not use this file except in compliance with the
+# License.  You may obtain a copy of the License at
+#
+#   http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.  See the
+# License for the specific language governing permissions and limitations
+# under the License.
+#
+############################################################################
+
+# Include serial drivers
+
+CSRCS += serial.c serial_io.c
+
+ifeq ($(CONFIG_SERIAL_RXDMA),y)
+  CSRCS += serial_dma.c
+else ifeq ($(CONFIG_SERIAL_TXDMA),y)
+  CSRCS += serial_dma.c
+endif
+
+ifeq ($(CONFIG_U16550_UART),y)
+  CSRCS += uart_16550.c
+endif
+
+ifeq ($(CONFIG_RPMSG_UART),y)
+  CSRCS += uart_rpmsg.c
+endif
+
+# Pseudo-terminal support
+
+ifeq ($(CONFIG_PSEUDOTERM),y)
+  CSRCS += pty.c
+ifeq ($(CONFIG_PSEUDOTERM_SUSV1),y)
+  CSRCS += ptmx.c
+endif
+endif
+
+# Bluetooth H:4 UART driver
+
+ifeq ($(CONFIG_UART_BTH4),y)
+  CSRCS += uart_bth4.c
+endif
+
+# Include serial build support
+
+DEPPATH += --dep-path serial
+VPATH += :serial

Ubiquitous/Nuttx_Fusion_XiUOS/app_match_nuttx/nuttx/include/nuttx/serial/uart_16550.h

@@ -0,0 +1,380 @@
+/****************************************************************************
+ * include/nuttx/serial/uart_16550.h
+ * Serial driver for 16550 UART
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements.  See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership.  The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License.  You may obtain a copy of the License at
+ *
+ *   http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.  See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+#ifndef __INCLUDE_NUTTX_SERIAL_UART_16550_H
+#define __INCLUDE_NUTTX_SERIAL_UART_16550_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#ifdef CONFIG_U16550_UART
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/* CONFIGURATION ************************************************************/
+
+/* Are any UARTs enabled? */
+
+#undef HAVE_UART
+#if defined(CONFIG_U16550_UART0) || defined(CONFIG_U16550_UART1) || \
+    defined(CONFIG_U16550_UART2) || defined(CONFIG_U16550_UART3)
+#  define HAVE_UART 1
+#endif
+
+/* We need to be told the address increment between registers and the
+ * register bit width.
+ */
+
+#ifndef CONFIG_U16550_REGINCR
+#  error "CONFIG_U16550_REGINCR not defined"
+#endif
+
+#if CONFIG_U16550_REGINCR != 1 && CONFIG_U16550_REGINCR != 2 && CONFIG_U16550_REGINCR != 4
+#  error "CONFIG_U16550_REGINCR not supported"
+#endif
+
+#ifndef CONFIG_U16550_REGWIDTH
+#  error "CONFIG_U16550_REGWIDTH not defined"
+#endif
+
+#if CONFIG_U16550_REGWIDTH != 8 && CONFIG_U16550_REGWIDTH != 16 && CONFIG_U16550_REGWIDTH != 32
+#  error "CONFIG_U16550_REGWIDTH not supported"
+#endif
+
+#ifndef CONFIG_U16550_ADDRWIDTH
+#  error "CONFIG_U16550_ADDRWIDTH not defined"
+#endif
+
+#if CONFIG_U16550_ADDRWIDTH != 0 && CONFIG_U16550_ADDRWIDTH != 8 && \
+    CONFIG_U16550_ADDRWIDTH != 16 && CONFIG_U16550_ADDRWIDTH != 32 && \
+    CONFIG_U16550_ADDRWIDTH != 64
+#  error "CONFIG_U16550_ADDRWIDTH not supported"
+#endif
+
+/* If a UART is enabled, then its base address, clock, and IRQ
+ * must also be provided
+ */
+
+#ifdef CONFIG_U16550_UART0
+#  ifndef CONFIG_U16550_UART0_BASE
+#    error "CONFIG_U16550_UART0_BASE not provided"
+#    undef CONFIG_U16550_UART0
+#  endif
+#  ifndef CONFIG_U16550_UART0_CLOCK
+#    error "CONFIG_U16550_UART0_CLOCK not provided"
+#    undef CONFIG_U16550_UART0
+#  endif
+#  ifndef CONFIG_U16550_UART0_IRQ
+#    error "CONFIG_U16550_UART0_IRQ not provided"
+#    undef CONFIG_U16550_UART0
+#  endif
+#endif
+
+#ifdef CONFIG_U16550_UART1
+#  ifndef CONFIG_U16550_UART1_BASE
+#    error "CONFIG_U16550_UART1_BASE not provided"
+#    undef CONFIG_U16550_UART1
+#  endif
+#  ifndef CONFIG_U16550_UART1_CLOCK
+#    error "CONFIG_U16550_UART1_CLOCK not provided"
+#    undef CONFIG_U16550_UART1
+#  endif
+#  ifndef CONFIG_U16550_UART1_IRQ
+#    error "CONFIG_U16550_UART1_IRQ not provided"
+#    undef CONFIG_U16550_UART1
+#  endif
+#endif
+
+#ifdef CONFIG_U16550_UART2
+#  ifndef CONFIG_U16550_UART2_BASE
+#    error "CONFIG_U16550_UART2_BASE not provided"
+#    undef CONFIG_U16550_UART2
+#  endif
+#  ifndef CONFIG_U16550_UART2_CLOCK
+#    error "CONFIG_U16550_UART2_CLOCK not provided"
+#    undef CONFIG_U16550_UART2
+#  endif
+#  ifndef CONFIG_U16550_UART2_IRQ
+#    error "CONFIG_U16550_UART2_IRQ not provided"
+#    undef CONFIG_U16550_UART2
+#  endif
+#endif
+
+#ifdef CONFIG_U16550_UART3
+#  ifndef CONFIG_U16550_UART3_BASE
+#    error "CONFIG_U16550_UART3_BASE not provided"
+#    undef CONFIG_U16550_UART3
+#  endif
+#  ifndef CONFIG_U16550_UART3_CLOCK
+#    error "CONFIG_U16550_UART3_CLOCK not provided"
+#    undef CONFIG_U16550_UART3
+#  endif
+#  ifndef CONFIG_U16550_UART3_IRQ
+#    error "CONFIG_U16550_UART3_IRQ not provided"
+#    undef CONFIG_U16550_UART3
+#  endif
+#endif
+
+/* Is there a serial console? There should be at most one defined.
+ * It could be on any UARTn, n=0,1,2,3
+ */
+
+#if defined(CONFIG_U16550_UART0_SERIAL_CONSOLE) && defined(CONFIG_U16550_UART0)
+#  undef CONFIG_U16550_UART1_SERIAL_CONSOLE
+#  undef CONFIG_U16550_UART2_SERIAL_CONSOLE
+#  undef CONFIG_U16550_UART3_SERIAL_CONSOLE
+#  define HAVE_16550_CONSOLE 1
+#elif defined(CONFIG_U16550_UART1_SERIAL_CONSOLE) && defined(CONFIG_U16550_UART1)
+#  undef CONFIG_U16550_UART0_SERIAL_CONSOLE
+#  undef CONFIG_U16550_UART2_SERIAL_CONSOLE
+#  undef CONFIG_U16550_UART3_SERIAL_CONSOLE
+#  define HAVE_16550_CONSOLE 1
+#elif defined(CONFIG_U16550_UART2_SERIAL_CONSOLE) && defined(CONFIG_U16550_UART2)
+#  undef CONFIG_U16550_UART0_SERIAL_CONSOLE
+#  undef CONFIG_U16550_UART1_SERIAL_CONSOLE
+#  undef CONFIG_U16550_UART3_SERIAL_CONSOLE
+#  define HAVE_16550_CONSOLE 1
+#elif defined(CONFIG_U16550_UART3_SERIAL_CONSOLE) && defined(CONFIG_U16550_UART3)
+#  undef CONFIG_U16550_UART0_SERIAL_CONSOLE
+#  undef CONFIG_U16550_UART1_SERIAL_CONSOLE
+#  undef CONFIG_U16550_UART2_SERIAL_CONSOLE
+#  define HAVE_16550_CONSOLE 1
+#else
+#  undef CONFIG_U16550_UART0_SERIAL_CONSOLE
+#  undef CONFIG_U16550_UART1_SERIAL_CONSOLE
+#  undef CONFIG_U16550_UART2_SERIAL_CONSOLE
+#  undef CONFIG_U16550_UART3_SERIAL_CONSOLE
+#  undef HAVE_16550_CONSOLE
+#endif
+
+/* Register offsets *********************************************************/
+
+#define UART_RBR_INCR          0 /* (DLAB =0) Receiver Buffer Register */
+#define UART_THR_INCR          0 /* (DLAB =0) Transmit Holding Register */
+#define UART_DLL_INCR          0 /* (DLAB =1) Divisor Latch LSB */
+#define UART_DLM_INCR          1 /* (DLAB =1) Divisor Latch MSB */
+#define UART_IER_INCR          1 /* (DLAB =0) Interrupt Enable Register */
+#define UART_IIR_INCR          2 /* Interrupt ID Register */
+#define UART_FCR_INCR          2 /* FIFO Control Register */
+#define UART_LCR_INCR          3 /* Line Control Register */
+#define UART_MCR_INCR          4 /* Modem Control Register */
+#define UART_LSR_INCR          5 /* Line Status Register */
+#define UART_MSR_INCR          6 /* Modem Status Register */
+#define UART_SCR_INCR          7 /* Scratch Pad Register */
+#define UART_SRT_INCR          39 /* Receive Fifo Trigger Register*/
+#define UART_DLF_INCR          48 /* Divisor factor Register*/
+#define UART_CPR_INCR          61 /* Component Register */
+
+#define UART_RBR_OFFSET        (CONFIG_U16550_REGINCR*UART_RBR_INCR)
+#define UART_THR_OFFSET        (CONFIG_U16550_REGINCR*UART_THR_INCR)
+#define UART_DLL_OFFSET        (CONFIG_U16550_REGINCR*UART_DLL_INCR)
+#define UART_DLM_OFFSET        (CONFIG_U16550_REGINCR*UART_DLM_INCR)
+#define UART_IER_OFFSET        (CONFIG_U16550_REGINCR*UART_IER_INCR)
+#define UART_IIR_OFFSET        (CONFIG_U16550_REGINCR*UART_IIR_INCR)
+#define UART_FCR_OFFSET        (CONFIG_U16550_REGINCR*UART_FCR_INCR)
+#define UART_LCR_OFFSET        (CONFIG_U16550_REGINCR*UART_LCR_INCR)
+#define UART_MCR_OFFSET        (CONFIG_U16550_REGINCR*UART_MCR_INCR)
+#define UART_LSR_OFFSET        (CONFIG_U16550_REGINCR*UART_LSR_INCR)
+#define UART_MSR_OFFSET        (CONFIG_U16550_REGINCR*UART_MSR_INCR)
+#define UART_SCR_OFFSET        (CONFIG_U16550_REGINCR*UART_SCR_INCR)
+#define UART_SRT_OFFSET        (CONFIG_U16550_REGINCR*UART_SRT_INCR)
+#define UART_DLF_OFFSET        (CONFIG_U16550_REGINCR*UART_DLF_INCR)
+#define UART_CPR_OFFSET        (CONFIG_U16550_REGINCR*UART_CPR_INCR)
+
+/* Register bit definitions *************************************************/
+
+/* RBR (DLAB =0) Receiver Buffer Register */
+
+#define UART_RBR_MASK                (0xff)    /* Bits 0-7: Oldest received byte in RX FIFO */
+                                               /* Bits 8-31: Reserved */
+
+/* THR (DLAB =0) Transmit Holding Register */
+
+#define UART_THR_MASK                (0xff)    /* Bits 0-7: Adds byte to TX FIFO */
+                                               /* Bits 8-31: Reserved */
+
+/* DLL (DLAB =1) Divisor Latch LSB */
+
+#define UART_DLL_MASK                (0xff)    /* Bits 0-7: DLL */
+                                               /* Bits 8-31: Reserved */
+
+/* DLM (DLAB =1) Divisor Latch MSB */
+
+#define UART_DLM_MASK                (0xff)    /* Bits 0-7: DLM */
+                                               /* Bits 8-31: Reserved */
+
+/* IER (DLAB =0) Interrupt Enable Register */
+
+#define UART_IER_ERBFI               (1 << 0)  /* Bit 0: Enable received data available interrupt */
+#define UART_IER_ETBEI               (1 << 1)  /* Bit 1: Enable THR empty interrupt */
+#define UART_IER_ELSI                (1 << 2)  /* Bit 2: Enable receiver line status interrupt */
+#define UART_IER_EDSSI               (1 << 3)  /* Bit 3: Enable MODEM status interrupt */
+                                               /* Bits 4-7: Reserved */
+#define UART_IER_ALLIE               (0x0f)
+
+/* IIR Interrupt ID Register */
+
+#define UART_IIR_INTSTATUS           (1 << 0)  /* Bit 0:  Interrupt status (active low) */
+#define UART_IIR_INTID_SHIFT         (1)       /* Bits 1-3: Interrupt identification */
+#define UART_IIR_INTID_MASK          (7 << UART_IIR_INTID_SHIFT)
+#  define UART_IIR_INTID_MSI         (0 << UART_IIR_INTID_SHIFT) /* Modem Status */
+#  define UART_IIR_INTID_THRE        (1 << UART_IIR_INTID_SHIFT) /* THR Empty Interrupt */
+#  define UART_IIR_INTID_RDA         (2 << UART_IIR_INTID_SHIFT) /* Receive Data Available (RDA) */
+#  define UART_IIR_INTID_RLS         (3 << UART_IIR_INTID_SHIFT) /* Receiver Line Status (RLS) */
+#  define UART_IIR_INTID_CTI         (6 << UART_IIR_INTID_SHIFT) /* Character Time-out Indicator (CTI) */
+
+                                               /* Bits 4-5: Reserved */
+#define UART_IIR_FIFOEN_SHIFT        (6)       /* Bits 6-7: RCVR FIFO interrupt */
+#define UART_IIR_FIFOEN_MASK         (3 << UART_IIR_FIFOEN_SHIFT)
+
+/* FCR FIFO Control Register */
+
+#define UART_FCR_FIFOEN              (1 << 0)  /* Bit 0:  Enable FIFOs */
+#define UART_FCR_RXRST               (1 << 1)  /* Bit 1:  RX FIFO Reset */
+#define UART_FCR_TXRST               (1 << 2)  /* Bit 2:  TX FIFO Reset */
+#define UART_FCR_DMAMODE             (1 << 3)  /* Bit 3:  DMA Mode Select */
+                                               /* Bits 4-5: Reserved */
+#define UART_FCR_RXTRIGGER_SHIFT     (6)       /* Bits 6-7: RX Trigger Level */
+#define UART_FCR_RXTRIGGER_MASK      (3 << UART_FCR_RXTRIGGER_SHIFT)
+#  define UART_FCR_RXTRIGGER_1       (0 << UART_FCR_RXTRIGGER_SHIFT) /*  Trigger level 0 (1 character) */
+#  define UART_FCR_RXTRIGGER_4       (1 << UART_FCR_RXTRIGGER_SHIFT) /* Trigger level 1 (4 characters) */
+#  define UART_FCR_RXTRIGGER_8       (2 << UART_FCR_RXTRIGGER_SHIFT) /* Trigger level 2 (8 characters) */
+#  define UART_FCR_RXTRIGGER_14      (3 << UART_FCR_RXTRIGGER_SHIFT) /* Trigger level 3 (14 characters) */
+
+/* LCR Line Control Register */
+
+#define UART_LCR_WLS_SHIFT           (0)       /* Bit 0-1: Word Length Select */
+#define UART_LCR_WLS_MASK            (3 << UART_LCR_WLS_SHIFT)
+#  define UART_LCR_WLS_5BIT          (0 << UART_LCR_WLS_SHIFT)
+#  define UART_LCR_WLS_6BIT          (1 << UART_LCR_WLS_SHIFT)
+#  define UART_LCR_WLS_7BIT          (2 << UART_LCR_WLS_SHIFT)
+#  define UART_LCR_WLS_8BIT          (3 << UART_LCR_WLS_SHIFT)
+#define UART_LCR_STB                 (1 << 2)  /* Bit 2:  Number of Stop Bits */
+#define UART_LCR_PEN                 (1 << 3)  /* Bit 3:  Parity Enable */
+#define UART_LCR_EPS                 (1 << 4)  /* Bit 4:  Even Parity Select */
+#define UART_LCR_STICKY              (1 << 5)  /* Bit 5:  Stick Parity */
+#define UART_LCR_BRK                 (1 << 6)  /* Bit 6: Break Control */
+#define UART_LCR_DLAB                (1 << 7)  /* Bit 7: Divisor Latch Access Bit (DLAB) */
+
+/* MCR Modem Control Register */
+
+#define UART_MCR_DTR                 (1 << 0)  /* Bit 0:  DTR Control Source for DTR output */
+#define UART_MCR_RTS                 (1 << 1)  /* Bit 1:  Control Source for  RTS output */
+#define UART_MCR_OUT1                (1 << 2)  /* Bit 2:  Auxiliary user-defined output 1 */
+#define UART_MCR_OUT2                (1 << 3)  /* Bit 3:  Auxiliary user-defined output 2 */
+#define UART_MCR_LPBK                (1 << 4)  /* Bit 4:  Loopback Mode Select */
+#define UART_MCR_AFCE                (1 << 5)  /* Bit 5:  Auto Flow Control Enable */
+                                               /* Bit 6-7: Reserved */
+
+/* LSR Line Status Register */
+
+#define UART_LSR_DR                  (1 << 0)  /* Bit 0:  Data Ready */
+#define UART_LSR_OE                  (1 << 1)  /* Bit 1:  Overrun Error */
+#define UART_LSR_PE                  (1 << 2)  /* Bit 2:  Parity Error */
+#define UART_LSR_FE                  (1 << 3)  /* Bit 3:  Framing Error */
+#define UART_LSR_BI                  (1 << 4)  /* Bit 4:  Break Interrupt */
+#define UART_LSR_THRE                (1 << 5)  /* Bit 5:  Transmitter Holding Register Empty */
+#define UART_LSR_TEMT                (1 << 6)  /* Bit 6:  Transmitter Empty */
+#define UART_LSR_RXFE                (1 << 7)  /* Bit 7:  Error in RX FIFO (RXFE) */
+
+/* SCR Scratch Pad Register */
+
+#define UART_SCR_MASK                (0xff)    /* Bits 0-7: SCR data */
+
+/****************************************************************************
+ * Public Types
+ ****************************************************************************/
+
+#if CONFIG_U16550_REGWIDTH == 8
+typedef uint8_t uart_datawidth_t;
+#elif CONFIG_U16550_REGWIDTH == 16
+typedef uint16_t uart_datawidth_t;
+#elif CONFIG_U16550_REGWIDTH == 32
+typedef uint32_t uart_datawidth_t;
+#endif
+
+#if CONFIG_U16550_ADDRWIDTH == 0
+typedef uintptr_t uart_addrwidth_t;
+#elif CONFIG_U16550_ADDRWIDTH == 8
+typedef uint8_t uart_addrwidth_t;
+#elif CONFIG_U16550_ADDRWIDTH == 16
+typedef uint16_t uart_addrwidth_t;
+#elif CONFIG_U16550_ADDRWIDTH == 32
+typedef uint32_t uart_addrwidth_t;
+#elif CONFIG_U16550_ADDRWIDTH == 64
+typedef uint64_t uart_addrwidth_t;
+#endif
+
+struct u16550_s
+{
+  uart_addrwidth_t uartbase;  /* Base address of UART registers */
+#ifndef CONFIG_U16550_SUPRESS_CONFIG
+  uint32_t         baud;      /* Configured baud */
+  uint32_t         uartclk;   /* UART clock frequency */
+#endif
+  uart_datawidth_t ier;       /* Saved IER value */
+  uint8_t          irq;       /* IRQ associated with this UART */
+#ifndef CONFIG_U16550_SUPRESS_CONFIG
+  uint8_t          parity;    /* 0=none, 1=odd, 2=even */
+  uint8_t          bits;      /* Number of bits (7 or 8) */
+  bool             stopbits2; /* true: Configure with 2 stop bits instead of 1 */
+#if defined(CONFIG_SERIAL_IFLOWCONTROL) || defined(CONFIG_SERIAL_OFLOWCONTROL)
+  bool             flow;      /* flow control (RTS/CTS) enabled */
+#endif
+#endif
+};
+
+/****************************************************************************
+ * Public Data
+ ****************************************************************************/
+
+/****************************************************************************
+ * Public Functions Definitions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: uart_getreg(), uart_putreg(), uart_ioctl()
+ *
+ * Description:
+ *   These functions must be provided by the processor-specific code in order
+ *   to correctly access 16550 registers
+ *   uart_ioctl() is optional to provide custom IOCTLs
+ *
+ ****************************************************************************/
+
+#ifndef CONFIG_SERIAL_UART_ARCH_MMIO
+uart_datawidth_t uart_getreg(uart_addrwidth_t base, unsigned int offset);
+void uart_putreg(uart_addrwidth_t base,
+                 unsigned int offset,
+                 uart_datawidth_t value);
+#endif
+
+struct file;  /* Forward reference */
+int uart_ioctl(struct file *filep, int cmd, unsigned long arg);
+
+void u16550_register(uart_dev_t **dev, int uart_index);
+#endif /* CONFIG_U16550_UART */
+#endif /* __INCLUDE_NUTTX_SERIAL_UART_16550_H */