diff --git a/Ubiquitous/Nuttx_Fusion_XiUOS/aiit_board/xidatong-riscv64/Kconfig b/Ubiquitous/Nuttx_Fusion_XiUOS/aiit_board/xidatong-riscv64/Kconfig index 56405367b..8b4ca4204 100644 --- a/Ubiquitous/Nuttx_Fusion_XiUOS/aiit_board/xidatong-riscv64/Kconfig +++ b/Ubiquitous/Nuttx_Fusion_XiUOS/aiit_board/xidatong-riscv64/Kconfig @@ -5,6 +5,11 @@ if ARCH_BOARD_XIDATONG_RISCV64 +menuconfig BSP_USING_CH376 + depends on U16550_UART3 + bool "Using CH376 device" + default n + menuconfig BSP_USING_CH438 bool "Using CH438 device" default n @@ -123,4 +128,20 @@ menu "Ch438 Port 7 Configuration" endmenu endif # BSP_USING_CH438 + +menuconfig BSP_USING_EC200 + depends on U16550_UART2 + bool "Using EC200 device" + default n + +menuconfig BSP_USING_CAN + depends on U16550_UART1 + bool "Using CAN device" + default n + +menuconfig BSP_USING_ESP8266 + depends on U16550_UART3 + bool "Using ESP8266 device" + default n + endif # ARCH_BOARD_XIDATONG_RISCV64 diff --git a/Ubiquitous/Nuttx_Fusion_XiUOS/aiit_board/xidatong-riscv64/configs/cannsh/defconfig b/Ubiquitous/Nuttx_Fusion_XiUOS/aiit_board/xidatong-riscv64/configs/cannsh/defconfig new file mode 100755 index 000000000..7bcf451da --- /dev/null +++ b/Ubiquitous/Nuttx_Fusion_XiUOS/aiit_board/xidatong-riscv64/configs/cannsh/defconfig @@ -0,0 +1,78 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_NSH_DISABLE_LOSMART is not set +# CONFIG_STANDARD_SERIAL is not set +CONFIG_ADD_NUTTX_FETURES=y +CONFIG_ARCH="risc-v" +CONFIG_ARCH_BOARD="xidatong-riscv64" +CONFIG_ARCH_BOARD_XIDATONG_RISCV64=y +CONFIG_ARCH_CHIP="k210" +CONFIG_ARCH_CHIP_K210=y +CONFIG_ARCH_INTERRUPTSTACK=2048 +CONFIG_ARCH_RISCV=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BINFMT_DISABLE=y +CONFIG_BOARD_LOOPSPERMSEC=46000 +CONFIG_BUILTIN=y +CONFIG_DEBUG_FULLOPT=y +CONFIG_DEBUG_SYMBOLS=y +CONFIG_EXAMPLES_HELLO=y +CONFIG_IDLETHREAD_STACKSIZE=2048 +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INIT_STACKSIZE=3072 +CONFIG_INTELHEX_BINARY=y +CONFIG_LIBC_PERROR_STDOUT=y +CONFIG_LIBC_STRERROR=y +CONFIG_NSH_ARCHINIT=y +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_DISABLE_IFUPDOWN=y +CONFIG_NSH_DISABLE_MKDIR=y +CONFIG_NSH_DISABLE_RM=y +CONFIG_NSH_DISABLE_RMDIR=y +CONFIG_NSH_DISABLE_UMOUNT=y +CONFIG_NSH_READLINE=y +CONFIG_NSH_STRERROR=y +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAM_SIZE=2097152 +CONFIG_RAM_START=0x80400000 +CONFIG_RAW_BINARY=y +CONFIG_READLINE_CMD_HISTORY=y +CONFIG_READLINE_CMD_HISTORY_LEN=100 +CONFIG_READLINE_CMD_HISTORY_LINELEN=120 +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_WAITPID=y +CONFIG_STACK_COLORATION=y +CONFIG_START_DAY=28 +CONFIG_START_MONTH=12 +CONFIG_START_YEAR=2019 +CONFIG_SYSTEM_NSH=y +CONFIG_TASK_NAME_SIZE=20 +CONFIG_TESTING_GETPRIME=y +CONFIG_UART0_SERIAL_CONSOLE=y +CONFIG_READLINE_TABCOMPLETION=y +CONFIG_SCHED_HPWORK=y +CONFIG_DEV_GPIO=y +CONFIG_BOARDCTL_RESET=y +CONFIG_U16550_UART=y +CONFIG_U16550_UART1=y +CONFIG_U16550_UART1_BASE=0x50230000 +CONFIG_U16550_UART1_CLOCK=195000000 +CONFIG_U16550_UART1_IRQ=38 +CONFIG_U16550_UART1_BAUD=9600 +CONFIG_U16550_UART1_PARITY=0 +CONFIG_U16550_UART1_BITS=8 +CONFIG_U16550_UART1_2STOP=0 +CONFIG_U16550_UART1_RXBUFSIZE=256 +CONFIG_U16550_UART1_TXBUFSIZE=256 +CONFIG_U16550_NO_SERIAL_CONSOLE=y +CONFIG_U16550_SUPRESS_INITIAL_CONFIG=y +CONFIG_SERIAL_UART_ARCH_MMIO=y +CONFIG_U16550_REGINCR=4 +CONFIG_U16550_REGWIDTH=32 +CONFIG_U16550_ADDRWIDTH=32 +CONFIG_BSP_USING_CAN=y \ No newline at end of file diff --git a/Ubiquitous/Nuttx_Fusion_XiUOS/aiit_board/xidatong-riscv64/configs/ch376nsh/defconfig b/Ubiquitous/Nuttx_Fusion_XiUOS/aiit_board/xidatong-riscv64/configs/ch376nsh/defconfig new file mode 100755 index 000000000..278f5d4c6 --- /dev/null +++ b/Ubiquitous/Nuttx_Fusion_XiUOS/aiit_board/xidatong-riscv64/configs/ch376nsh/defconfig @@ -0,0 +1,78 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_NSH_DISABLE_LOSMART is not set +# CONFIG_STANDARD_SERIAL is not set +CONFIG_ADD_NUTTX_FETURES=y +CONFIG_ARCH="risc-v" +CONFIG_ARCH_BOARD="xidatong-riscv64" +CONFIG_ARCH_BOARD_XIDATONG_RISCV64=y +CONFIG_ARCH_CHIP="k210" +CONFIG_ARCH_CHIP_K210=y +CONFIG_ARCH_INTERRUPTSTACK=2048 +CONFIG_ARCH_RISCV=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BINFMT_DISABLE=y +CONFIG_BOARD_LOOPSPERMSEC=46000 +CONFIG_BUILTIN=y +CONFIG_DEBUG_FULLOPT=y +CONFIG_DEBUG_SYMBOLS=y +CONFIG_EXAMPLES_HELLO=y +CONFIG_IDLETHREAD_STACKSIZE=2048 +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INIT_STACKSIZE=3072 +CONFIG_INTELHEX_BINARY=y +CONFIG_LIBC_PERROR_STDOUT=y +CONFIG_LIBC_STRERROR=y +CONFIG_NSH_ARCHINIT=y +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_DISABLE_IFUPDOWN=y +CONFIG_NSH_DISABLE_MKDIR=y +CONFIG_NSH_DISABLE_RM=y +CONFIG_NSH_DISABLE_RMDIR=y +CONFIG_NSH_DISABLE_UMOUNT=y +CONFIG_NSH_READLINE=y +CONFIG_NSH_STRERROR=y +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAM_SIZE=2097152 +CONFIG_RAM_START=0x80400000 +CONFIG_RAW_BINARY=y +CONFIG_READLINE_CMD_HISTORY=y +CONFIG_READLINE_CMD_HISTORY_LEN=100 +CONFIG_READLINE_CMD_HISTORY_LINELEN=120 +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_WAITPID=y +CONFIG_STACK_COLORATION=y +CONFIG_START_DAY=28 +CONFIG_START_MONTH=12 +CONFIG_START_YEAR=2019 +CONFIG_SYSTEM_NSH=y +CONFIG_TASK_NAME_SIZE=20 +CONFIG_TESTING_GETPRIME=y +CONFIG_UART0_SERIAL_CONSOLE=y +CONFIG_READLINE_TABCOMPLETION=y +CONFIG_SCHED_HPWORK=y +CONFIG_DEV_GPIO=y +CONFIG_BOARDCTL_RESET=y +CONFIG_U16550_UART=y +CONFIG_U16550_UART3=y +CONFIG_U16550_UART3_BASE=0x50230000 +CONFIG_U16550_UART3_CLOCK=195000000 +CONFIG_U16550_UART3_IRQ=40 +CONFIG_U16550_UART3_BAUD=115200 +CONFIG_U16550_UART3_PARITY=0 +CONFIG_U16550_UART3_BITS=8 +CONFIG_U16550_UART3_2STOP=0 +CONFIG_U16550_UART3_RXBUFSIZE=256 +CONFIG_U16550_UART3_TXBUFSIZE=256 +CONFIG_U16550_NO_SERIAL_CONSOLE=y +CONFIG_U16550_SUPRESS_INITIAL_CONFIG=y +CONFIG_SERIAL_UART_ARCH_MMIO=y +CONFIG_U16550_REGINCR=4 +CONFIG_U16550_REGWIDTH=32 +CONFIG_U16550_ADDRWIDTH=32 +CONFIG_BSP_USING_CH376=y \ No newline at end of file diff --git a/Ubiquitous/Nuttx_Fusion_XiUOS/aiit_board/xidatong-riscv64/configs/ec200nsh/defconfig b/Ubiquitous/Nuttx_Fusion_XiUOS/aiit_board/xidatong-riscv64/configs/ec200nsh/defconfig new file mode 100755 index 000000000..4415550c6 --- /dev/null +++ b/Ubiquitous/Nuttx_Fusion_XiUOS/aiit_board/xidatong-riscv64/configs/ec200nsh/defconfig @@ -0,0 +1,78 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_NSH_DISABLE_LOSMART is not set +# CONFIG_STANDARD_SERIAL is not set +CONFIG_ADD_NUTTX_FETURES=y +CONFIG_ARCH="risc-v" +CONFIG_ARCH_BOARD="xidatong-riscv64" +CONFIG_ARCH_BOARD_XIDATONG_RISCV64=y +CONFIG_ARCH_CHIP="k210" +CONFIG_ARCH_CHIP_K210=y +CONFIG_ARCH_INTERRUPTSTACK=2048 +CONFIG_ARCH_RISCV=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BINFMT_DISABLE=y +CONFIG_BOARD_LOOPSPERMSEC=46000 +CONFIG_BUILTIN=y +CONFIG_DEBUG_FULLOPT=y +CONFIG_DEBUG_SYMBOLS=y +CONFIG_EXAMPLES_HELLO=y +CONFIG_IDLETHREAD_STACKSIZE=2048 +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INIT_STACKSIZE=3072 +CONFIG_INTELHEX_BINARY=y +CONFIG_LIBC_PERROR_STDOUT=y +CONFIG_LIBC_STRERROR=y +CONFIG_NSH_ARCHINIT=y +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_DISABLE_IFUPDOWN=y +CONFIG_NSH_DISABLE_MKDIR=y +CONFIG_NSH_DISABLE_RM=y +CONFIG_NSH_DISABLE_RMDIR=y +CONFIG_NSH_DISABLE_UMOUNT=y +CONFIG_NSH_READLINE=y +CONFIG_NSH_STRERROR=y +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAM_SIZE=2097152 +CONFIG_RAM_START=0x80400000 +CONFIG_RAW_BINARY=y +CONFIG_READLINE_CMD_HISTORY=y +CONFIG_READLINE_CMD_HISTORY_LEN=100 +CONFIG_READLINE_CMD_HISTORY_LINELEN=120 +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_WAITPID=y +CONFIG_STACK_COLORATION=y +CONFIG_START_DAY=28 +CONFIG_START_MONTH=12 +CONFIG_START_YEAR=2019 +CONFIG_SYSTEM_NSH=y +CONFIG_TASK_NAME_SIZE=20 +CONFIG_TESTING_GETPRIME=y +CONFIG_UART0_SERIAL_CONSOLE=y +CONFIG_READLINE_TABCOMPLETION=y +CONFIG_SCHED_HPWORK=y +CONFIG_DEV_GPIO=y +CONFIG_BOARDCTL_RESET=y +CONFIG_U16550_UART=y +CONFIG_U16550_UART2=y +CONFIG_U16550_UART2_BASE=0x50220000 +CONFIG_U16550_UART2_CLOCK=195000000 +CONFIG_U16550_UART2_IRQ=39 +CONFIG_U16550_UART2_BAUD=115200 +CONFIG_U16550_UART2_PARITY=0 +CONFIG_U16550_UART2_BITS=8 +CONFIG_U16550_UART2_2STOP=0 +CONFIG_U16550_UART2_RXBUFSIZE=256 +CONFIG_U16550_UART2_TXBUFSIZE=256 +CONFIG_U16550_NO_SERIAL_CONSOLE=y +CONFIG_U16550_SUPRESS_INITIAL_CONFIG=y +CONFIG_SERIAL_UART_ARCH_MMIO=y +CONFIG_U16550_REGINCR=4 +CONFIG_U16550_REGWIDTH=32 +CONFIG_U16550_ADDRWIDTH=32 +CONFIG_BSP_USING_EC200=y \ No newline at end of file diff --git a/Ubiquitous/Nuttx_Fusion_XiUOS/aiit_board/xidatong-riscv64/src/Makefile b/Ubiquitous/Nuttx_Fusion_XiUOS/aiit_board/xidatong-riscv64/src/Makefile index d6fa521c7..11551cefc 100644 --- a/Ubiquitous/Nuttx_Fusion_XiUOS/aiit_board/xidatong-riscv64/src/Makefile +++ b/Ubiquitous/Nuttx_Fusion_XiUOS/aiit_board/xidatong-riscv64/src/Makefile @@ -46,4 +46,16 @@ ifeq ($(CONFIG_BSP_USING_CH438),y) CSRCS += k210_ch438.c ch438_demo.c endif +ifeq ($(CONFIG_BSP_USING_CH376),y) +CSRCS += k210_ch376.c ch376_demo.c +endif + +ifeq ($(CONFIG_BSP_USING_EC200),y) +CSRCS += k210_ec200.c ec200_demo.c +endif + +ifeq ($(CONFIG_BSP_USING_CAN),y) +CSRCS += k210_can.c can_demo.c +endif + include $(TOPDIR)/boards/Board.mk diff --git a/Ubiquitous/Nuttx_Fusion_XiUOS/aiit_board/xidatong-riscv64/src/can_demo.c b/Ubiquitous/Nuttx_Fusion_XiUOS/aiit_board/xidatong-riscv64/src/can_demo.c new file mode 100755 index 000000000..b4307393e --- /dev/null +++ b/Ubiquitous/Nuttx_Fusion_XiUOS/aiit_board/xidatong-riscv64/src/can_demo.c @@ -0,0 +1,172 @@ +/* +* Copyright (c) 2022 AIIT XUOS Lab +* XiUOS is licensed under Mulan PSL v2. +* You can use this software according to the terms and conditions of the Mulan PSL v2. +* You may obtain a copy of Mulan PSL v2 at: +* http://license.coscl.org.cn/MulanPSL2 +* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, +* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, +* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. +* See the Mulan PSL v2 for more details. +*/ + +/** + * @file can_demo.c + * @brief xidatong-riscv64 can demo + * @version 1.0 + * @author AIIT XUOS Lab + * @date 2022.9.9 + */ + +/**************************************************************************** + * Included Files + ****************************************************************************/ +#include "k210_can.h" +#include +#include "time.h" + +#define can_print printf +#define CAN_DEMO_TIMEOUT 10 +#define CAN_NAME "/dev/can" + + +static int can_read_with_time(int fd, char *buffer, int seconds) +{ + int read_size = 0; + time_t cur_time = time(NULL); + time_t last_time = cur_time; + + while(cur_time < last_time + seconds) + { + read_size = read(fd, buffer, 256); + + if(read_size < 0) + { + can_print("can read failed %d\n", read_size); + return -ETIME; + } + else if(read_size) + { + can_print("can read size %d ok!\n", read_size); + break; + } + cur_time = time(NULL); + } + return read_size; +} + +static int can_cfg_start(int fd) +{ + int ret = OK; + + //cmd[3]: can speed = 100K + //cmd[4]: 1 Byte + //cmd[5]: 100K + uint8_t cmd1[] = {0xAA, 0x55, 0xFD, 0x32, 0x01, 0x0B, 0xC4, 0x29}; + + //cmd[3] = 0xc8; //serial parameter + //cmd[4] = 0x04; //4 Bytes + //cmd[5] = 0x09; //115200 + //cmd[6] = 0x01; //8 + //cmd[7] = 0x00; //N + //cmd[8] = 0x00; //1 + uint8_t cmd2[] = {0xAA, 0x55, 0xFD, 0xC8, 0x04, 0x09, 0x01, 0x00, 0x00, 0xD6, 0x4F}; + + // start config + k210_gpiohs_set_value(FPIOA_CAN_CFG, GPIO_PV_LOW); + ret = close(fd); + up_mdelay(1000); + + // open with 9600 baudrate + ret = open(CAN_NAME, O_RDWR); + if (ret != OK) + { + can_print("Open %s device failed!\n", CAN_NAME); + return ret; + } + + //initialization and config parameter + k210_gpiohs_set_direction(FPIOA_CAN_CFG, GPIO_DM_OUTPUT); + k210_gpiohs_set_value(FPIOA_CAN_CFG, GPIO_PV_LOW); + up_mdelay(200); + + write(fd, cmd1, 8); + up_mdelay(1000); + + write(fd, cmd2, 11); + return ret; +} + +static int can_cfg_end(int fd) +{ + int ret = OK; + + // manual exit configuration + k210_gpiohs_set_value(FPIOA_CAN_CFG, GPIO_PV_HIGH); + + // close firstly + ret = close(fd); + up_mdelay(1000); + + fd = open(CAN_NAME, O_RDWR); + if (fd < 0) + { + can_print("Open %s device failed!\n", CAN_NAME); + return ret; + } + + return ret; +} + +static void can_test(int fd) +{ + uint8_t cmd[16]; + + for(int i = 0; i < 5; i++) + { + cmd[0] = 0x55; + cmd[1] = 0x77; + write(fd, cmd, 2); + up_mdelay(200); + + cmd[0] = 0x99; + cmd[1] = 0xBB; + write(fd, cmd, 2); + up_mdelay(200); + } +} + +static void can_read_para(int fd) +{ + uint8_t cmd[] = {0xAA, 0x55, 0xFE}; + char recv_buf[256] = {0}; + + k210_gpiohs_set_value(FPIOA_CAN_CFG, GPIO_PV_LOW); + up_mdelay(100); + + write(fd, cmd, 3); + can_read_with_time(fd, recv_buf, CAN_DEMO_TIMEOUT); + up_mdelay(200); +} + +void CanDemo(void) +{ + int fd; + + can_print("start %s\n", __func__); + + fd = open(CAN_NAME, O_RDWR); + if(fd < 0) + { + can_print("can open failed %d\n", fd); + return; + } + + can_print("open can fd = %d ok!\n", fd); + can_read_para(fd); + + up_mdelay(1000); + close(fd); + + can_print("end %s\n", __func__); +} diff --git a/Ubiquitous/Nuttx_Fusion_XiUOS/aiit_board/xidatong-riscv64/src/ch376_demo.c b/Ubiquitous/Nuttx_Fusion_XiUOS/aiit_board/xidatong-riscv64/src/ch376_demo.c new file mode 100755 index 000000000..9aa91e653 --- /dev/null +++ b/Ubiquitous/Nuttx_Fusion_XiUOS/aiit_board/xidatong-riscv64/src/ch376_demo.c @@ -0,0 +1,100 @@ +/* +* Copyright (c) 2022 AIIT XUOS Lab +* XiUOS is licensed under Mulan PSL v2. +* You can use this software according to the terms and conditions of the Mulan PSL v2. +* You may obtain a copy of Mulan PSL v2 at: +* http://license.coscl.org.cn/MulanPSL2 +* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, +* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, +* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. +* See the Mulan PSL v2 for more details. +*/ + +/** + * @file ch376_demo.c + * @brief xidatong-riscv64 ch376_demo.c + * @version 1.0 + * @author AIIT XUOS Lab + * @date 2022.08.22 + */ + +/**************************************************************************** + * Included Files + ****************************************************************************/ +#include "k210_ch376.h" +#include + +#define CONFIG_DEBUG_CH376_INFO 1 +#define ch376_print printf + +static int ch376_test_fd = 0; + +void ch376_show_buf(char *str, int size, uint8_t *buf) +{ + ch376_print("%s size %d: ", str, size); + for(int i = 0; i < size; i++) + { + ch376_print("[%x] ", buf[i]); + } + ch376_print("\n"); +} + +static void ch376_cmd_demo(void) +{ + uint8_t cmd[16] = CH376_CMD_HEADER; + uint8_t buf[256] = {0}; + + cmd[2] = CH376_CMD_SET_MODE; + cmd[3] = CH376_CMD_USB_MODE; + ch376_show_buf("sending", 4, cmd); + write(ch376_test_fd, cmd, 4); + read(ch376_test_fd, buf, 1); + ch376_show_buf("received", 1, buf); + up_mdelay(1000); + + cmd[2] = CH376_CMD_DISK_CONN; + ch376_show_buf("sending", 3, cmd); + write(ch376_test_fd, cmd, 3); + read(ch376_test_fd, buf, 1); + ch376_show_buf("received", 1, buf); + up_mdelay(1000); + + cmd[2] = CH376_CMD_DISK_MOUNT; + ch376_show_buf("sending", 3, cmd); + write(ch376_test_fd, cmd, 3); + read(ch376_test_fd, buf, 1); + ch376_show_buf("received", 1, buf); + up_mdelay(1000); + + cmd[2] = CH376_CMD_OPEN_FILE; + ch376_show_buf("sending", 3, cmd); + write(ch376_test_fd, cmd, 3); + read(ch376_test_fd, buf, 1); + ch376_show_buf("received", 1, buf); + up_mdelay(1000); + + cmd[2] = CH376_CMD_DISK_QUERY; + ch376_show_buf("sending", 3, cmd); + write(ch376_test_fd, cmd, 3); + read(ch376_test_fd, buf, 1); + ch376_show_buf("received", 1, buf); + up_mdelay(1000); + + cmd[2] = CH376_CMD_RD_USB; + ch376_show_buf("sending", 3, cmd); + write(ch376_test_fd, cmd, 3); + read(ch376_test_fd, buf, 1); + ch376_show_buf("received", 1, buf); + up_mdelay(1000); +} + +void CH376Demo(void) +{ + ch376_test_fd = open("/dev/ch376", O_RDWR); + + ch376_print("open ch376 fd = %d\n", ch376_test_fd); + ch376_print("start demo ...\n"); + ch376_cmd_demo(); + ch376_print("end demo...\n"); +} + diff --git a/Ubiquitous/Nuttx_Fusion_XiUOS/aiit_board/xidatong-riscv64/src/ec200_demo.c b/Ubiquitous/Nuttx_Fusion_XiUOS/aiit_board/xidatong-riscv64/src/ec200_demo.c new file mode 100755 index 000000000..92b6c9a03 --- /dev/null +++ b/Ubiquitous/Nuttx_Fusion_XiUOS/aiit_board/xidatong-riscv64/src/ec200_demo.c @@ -0,0 +1,138 @@ +/* +* Copyright (c) 2022 AIIT XUOS Lab +* XiUOS is licensed under Mulan PSL v2. +* You can use this software according to the terms and conditions of the Mulan PSL v2. +* You may obtain a copy of Mulan PSL v2 at: +* http://license.coscl.org.cn/MulanPSL2 +* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, +* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, +* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. +* See the Mulan PSL v2 for more details. +*/ + +/** + * @file ec200_demo.c + * @brief xidatong-riscv64 ec200_demo.c + * @version 1.0 + * @author AIIT XUOS Lab + * @date 2022.08.22 + */ + +/**************************************************************************** + * Included Files + ****************************************************************************/ +#include "k210_ec200.h" +#include +#include "time.h" + +#define ec_print printf +#define EC200_DEMO_TIMEOUT 10 + + +// first: receive \n\rRDY\n\r +// second: AT -> OK + +// APN configuration "CTNET"(中国电信) +char *ec200_ctnet_cmd[] = +{ + + "AT\r\n", + "AT+QICSGP=1,1,\"CTNET\",\"\",\"\",1\r\n", + "AT+QIACT=1\r\n", + "AT+QIOPEN=1,0,\"TCP\",\"121.41.20.48\",8840,0,2\r\n" +}; + +// APN configuration "CMNET"(中国移动) +char *ec200_cmnet_cmd[] = +{ + "AT\r\n", + "AT+QICSGP=1,1,\"CMNET\",\"\",\"\",1\r\n", + "AT+QIACT=1\r\n", + "AT+QIOPEN=1,0,\"TCP\",\"121.41.20.48\",8840,0,2\r\n" +}; + +static int ec200_read_with_time(int fd, char *buffer, int seconds) +{ + int read_size = 0; + time_t cur_time = time(NULL); + time_t last_time = cur_time; + + while(cur_time < last_time + seconds) + { + read_size = read(fd, buffer, 256); + + if(read_size < 0) + { + ec_print("ec200 read failed %d\n", read_size); + return -ETIME; + } + else if(read_size) + { + ec_print("ec200 read size %d ok!\n", read_size); + break; + } + cur_time = time(NULL); + } + return read_size; +} + +int ec200_check_demo(int fd, char *send_str, char *recv_str) +{ + int ret; + char buf[EC200_RECV_BUF_SIZE] = {0}; + + if(send_str) + { + ret = write(fd, send_str, strlen(send_str)); + + if(ret < 0) + { + ec_print("ec200 write failed %d\n", ret); + return ret; + } + + ec_print("write %s ret = %d\n", send_str, ret); + } + + ret = ec200_read_with_time(fd, buf, EC200_DEMO_TIMEOUT); + if(ret < 0) + { + ec_print("ec200 read failed %d\n", ret); + return ret; + } + + ec_print("ec200 read: %s!\n", buf); + + if(strstr(buf, recv_str)) + { + ec_print("ec200 %s found!\n", recv_str); + } + + return ret; +} + + +void EC200Demo(void) +{ + int fd; + + ec_print("start %s\n", __func__); + + fd = open("/dev/ec200", O_RDWR); + if(fd < 0) + { + ec_print("ec200 open failed %d\n", fd); + return; + } + + ec200_check_demo(fd, NULL, "RDY"); + ec200_check_demo(fd, "AT\r\n", "OK"); + ec200_check_demo(fd, "AT+QICSGP=1,1,\"CTNET\",\"\",\"\",1\r\n", "OK"); + ec200_check_demo(fd, "AT+QIACT=1\r\n", "OK"); + ec200_check_demo(fd, "AT+QIOPEN=1,0,\"TCP\",\"121.41.20.48\",8840,0,2\r\n", "OK"); + + up_mdelay(2000); + close(fd); + + ec_print("end %s\n", __func__); +} diff --git a/Ubiquitous/Nuttx_Fusion_XiUOS/aiit_board/xidatong-riscv64/src/k210_bringup.c b/Ubiquitous/Nuttx_Fusion_XiUOS/aiit_board/xidatong-riscv64/src/k210_bringup.c index bc90e372b..2514b194a 100644 --- a/Ubiquitous/Nuttx_Fusion_XiUOS/aiit_board/xidatong-riscv64/src/k210_bringup.c +++ b/Ubiquitous/Nuttx_Fusion_XiUOS/aiit_board/xidatong-riscv64/src/k210_bringup.c @@ -41,6 +41,24 @@ # include "k210_ch438.h" #endif +#ifdef CONFIG_BSP_USING_CH376 +# include "k210_ch376.h" +#endif + +#ifdef CONFIG_BSP_USING_EC200 +# include "k210_ec200.h" +#endif + +#ifdef CONFIG_BSP_USING_CAN +# include "k210_can.h" +#endif + +#ifdef CONFIG_BSP_USING_ESP8266 +# include "k210_esp8266.h" +#endif + +#include "k210_sysctl.h" + /**************************************************************************** * Public Functions ****************************************************************************/ @@ -85,5 +103,33 @@ int k210_bringup(void) } #endif +#ifdef CONFIG_BSP_USING_CH376 + sysctl_clock_enable(SYSCTL_CLOCK_UART3); + sysctl_reset(SYSCTL_RESET_UART3); + + board_ch376_initialize(); +#endif + +#ifdef CONFIG_BSP_USING_EC200 + k210_sysctl_init(); + sysctl_clock_enable(SYSCTL_CLOCK_UART2); + sysctl_reset(SYSCTL_RESET_UART2); + board_ec200_initialize(); +#endif + +#ifdef CONFIG_BSP_USING_CAN + k210_sysctl_init(); + sysctl_clock_enable(SYSCTL_CLOCK_UART1); + sysctl_reset(SYSCTL_RESET_UART1); + board_can_initialize(); +#endif + +#ifdef CONFIG_BSP_USING_ESP8266 + k210_sysctl_init(); + sysctl_clock_enable(SYSCTL_CLOCK_UART3); + sysctl_reset(SYSCTL_RESET_UART3); + board_esp8266_initialize(); +#endif + return ret; } diff --git a/Ubiquitous/Nuttx_Fusion_XiUOS/aiit_board/xidatong-riscv64/src/k210_can.c b/Ubiquitous/Nuttx_Fusion_XiUOS/aiit_board/xidatong-riscv64/src/k210_can.c new file mode 100755 index 000000000..7e1bc1587 --- /dev/null +++ b/Ubiquitous/Nuttx_Fusion_XiUOS/aiit_board/xidatong-riscv64/src/k210_can.c @@ -0,0 +1,461 @@ +/* +* Copyright (c) 2022 AIIT XUOS Lab +* XiUOS is licensed under Mulan PSL v2. +* You can use this software according to the terms and conditions of the Mulan PSL v2. +* You may obtain a copy of Mulan PSL v2 at: +* http://license.coscl.org.cn/MulanPSL2 +* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, +* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, +* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. +* See the Mulan PSL v2 for more details. +*/ + +/** +* @file k210_can.c +* @brief support to register can pointer and function +* @version 1.0 +* @author AIIT XUOS Lab +* @date 2022-07-20 +*/ + +#include +#include +#include +#include "ctype.h" +#include "k210_can.h" + +#define ec_print printf + +/******************************************************************************/ + +struct can_dev_s g_candev; +static char *can_dev_name = "/dev/can"; + +/******************************************************************************/ + +void can_print_buf(int size, uint8_t *buf) +{ + char ch[10] = {0}; + char temp[256] = {0}; + + if(size >= 256) + size = 256; + + for(int i = 0; i < size; i++) + { + if(buf[i] == '\r') + { + strcat(temp, "\\r"); + } + else if(buf[i] == '\n') + { + strcat(temp, "\\n"); + } + else if(isascii(buf[i])) + { + snprintf(ch, sizeof(ch), "%c", buf[i]); + strcat(temp, ch); + } + else + { + snprintf(ch, sizeof(ch), "%#x ", buf[i]); + strcat(temp, ch); + } + } + if(size) + ec_print("can read %d data: %s\n", size, temp); +} + +int can_read_buf(void *dev, int *size, uint8_t *buf) +{ + uart_dev_t *uart_dev = (uart_dev_t *)dev; + int cur_size = uart_dev->recv.head - uart_dev->recv.tail; + *size = *size > cur_size ? cur_size : *size; + memcpy(buf, uart_dev->recv.buffer, *size); + uart_dev->recv.head = uart_dev->recv.tail; + can_print_buf(*size, buf); + return *size; +} + +/**************************************************************************** + * Name: can_data_work + * + * Description: + * thread task can_data_work + * + ****************************************************************************/ +static FAR void can_data_work(FAR void *arg) +{ + struct can_dev_s *can_dev = (struct can_dev_s *)arg; + uart_dev_t *uart_dev = can_dev->uart_dev; + nxsem_wait(&can_dev->waitsem); + can_dev->recv_size = CAN_RECV_BUF_SIZE; + can_read_buf(uart_dev, &can_dev->recv_size, can_dev->recv_buf); + work_queue(HPWORK, &can_dev->irqwork, can_data_work, can_dev, CAN_INCREMENT); +// caninfo("uart size %d ok!\n", can_dev->recv_size); +} + +static int can_bringup(struct can_dev_s *dev) +{ +// struct can_dev_s *can_dev = &g_candev; + + dev->uart_fd = open(dev->dev_name, O_RDWR); + + caninfo("open %s fd = %d\n", dev->dev_name, dev->uart_fd); + + work_queue(HPWORK, &dev->irqwork, can_data_work, dev, CAN_INCREMENT); + return OK; +} + +static int can_write_config(struct can_dev_s *dev) +{ + return OK; +} + +static int can_shutdown(struct can_dev_s *dev) +{ + close(dev->uart_fd); + return OK; +} + +static int can_open(FAR struct file *filep) +{ + FAR struct inode *inode; + FAR struct can_dev_s *priv; + + uint8_t ref_cnt; + + int ret; + + DEBUGASSERT(filep); + inode = filep->f_inode; + DEBUGASSERT(inode && inode->i_private); + + priv = (FAR struct can_dev_s *)inode->i_private; + + /* Get exclusive access to the driver data structure */ + ret = nxsem_wait(&priv->devsem); + + if(ret < 0) + { + canerr("ERROR: nxsem_wait failed: %d\n", ret); + return ret; + } + + /* Increment the reference count */ + ref_cnt = priv->crefs + 1; + + if(ref_cnt == 0) + { + /* More than 255 opens; uint8_t overflows to zero */ + nxsem_post(&priv->devsem); + return -EMFILE; + } + + /* When the reference increments to 1, this is the first open event + * on the driver.. and the time when we must initialize the driver. + */ + + if(ref_cnt == 1) + { + ret = can_bringup(priv); + + if(ret < 0) + { + canerr("ERROR: can_bringup failed: %d\n", ret); + nxsem_post(&priv->devsem); + return ret; + } + + ret = can_write_config(priv); + + if(ret < 0) + { + canerr("ERROR: can_write_config failed: %d\n", ret); + nxsem_post(&priv->devsem); + return ret; + } + } + + /* Save the new open count on success */ + priv->crefs = ref_cnt; + + nxsem_post(&priv->devsem); + return ret; +} + +/**************************************************************************** + * Name: can_close + ****************************************************************************/ + +static int can_close(FAR struct file *filep) +{ + FAR struct inode *inode; + FAR struct can_dev_s *priv; + + int ret; + + DEBUGASSERT(filep); + inode = filep->f_inode; + DEBUGASSERT(inode && inode->i_private); + + priv = (FAR struct can_dev_s *)inode->i_private; + + /* Get exclusive access to the driver data structure */ + ret = nxsem_wait(&priv->devsem); + + if(ret < 0) + { + canerr("ERROR: nxsem_wait failed: %d\n", ret); + return ret; + } + + /* Decrement the reference count unless it would decrement a negative + * value. + */ + + if(priv->crefs >= 1) + { + priv->crefs--; + } + + /* When the count decrements to zero, there are no further open references + * to the driver and it can be uninitialized. + */ + + if(priv->crefs == 0) + { + can_shutdown(priv); + } + + nxsem_post(&priv->devsem); + return OK; +} + +/**************************************************************************** + * Name: can_read + ****************************************************************************/ + +static ssize_t can_read(FAR struct file *filep, FAR char *buffer, size_t len) +{ + FAR struct inode *inode; + FAR struct can_dev_s *priv; + int ret, buf_size = len; + + DEBUGASSERT(filep); + inode = filep->f_inode; + DEBUGASSERT(inode && inode->i_private); + + priv = (FAR struct can_dev_s *)inode->i_private; + + ret = nxsem_wait(&priv->devsem); + + if(ret < 0) + { + canerr("ERROR: nxsem_wait failed: %d\n", ret); + return ret; + } + + buf_size = len > priv->recv_size ? priv->recv_size : len; + memcpy(buffer, priv->recv_buf, buf_size); + nxsem_post(&priv->devsem); + return ret; +} + + +/**************************************************************************** + * Name: can_write + ****************************************************************************/ + +static ssize_t can_write(FAR struct file *filep, FAR const char *buffer, size_t len) +{ + FAR struct inode *inode; + FAR struct can_dev_s *priv; + int ret; + DEBUGASSERT(filep); + inode = filep->f_inode; + DEBUGASSERT(inode && inode->i_private); + priv = (FAR struct can_dev_s *)inode->i_private; + + /* Get exclusive access to the driver data structure */ + ret = nxsem_wait(&priv->devsem); + + if(ret < 0) + { + canerr("ERROR: nxsem_wait failed: %d\n", ret); + return ret; + } + + ret = write(priv->uart_fd, buffer, len); + caninfo("write fd %d len %ld ret = %d\n", priv->uart_fd, len, ret); + nxsem_post(&priv->devsem); + return ret; +} + +/**************************************************************************** + * Name: can_ioctl + ****************************************************************************/ + +static int can_ioctl(FAR struct file *filep, int cmd, unsigned long arg) +{ + FAR struct inode *inode; + FAR struct can_dev_s *priv; + FAR uint32_t *ptr; + + int ret; + + DEBUGASSERT(filep); + inode = filep->f_inode; + DEBUGASSERT(inode && inode->i_private); + + priv = (FAR struct can_dev_s *)inode->i_private; + + /* Get exclusive access to the driver data structure */ + ret = nxsem_wait(&priv->devsem); + + if(ret < 0) + { + canerr("ERROR: nxsem_wait failed: %d\n", ret); + return ret; + } + + /* Process the IOCTL by command */ + + switch(cmd) + { + case CANIOC_SETFREQUENCY: /* arg: Pointer to uint32_t frequency value */ + ptr = (FAR uint32_t *)((uintptr_t)arg); + DEBUGASSERT(priv->config != NULL && ptr != NULL); + break; + + default: + ret = -ENOTTY; + break; + } + + nxsem_post(&priv->devsem); + return ret; +} + +/**************************************************************************** + * Name: can_poll + ****************************************************************************/ + +static int can_poll(FAR struct file *filep, FAR struct pollfd *fds, bool setup) +{ + FAR struct inode *inode; + FAR struct can_dev_s *priv; + + int ret; + + caninfo("setup: %d\n", (int)setup); + + DEBUGASSERT(filep && fds); + inode = filep->f_inode; + DEBUGASSERT(inode && inode->i_private); + + priv = (FAR struct can_dev_s *)inode->i_private; + + /* Are we setting up the poll? Or tearing it down? */ + ret = nxsem_wait(&priv->devsem); + + if(ret < 0) + { + canerr("ERROR: nxsem_wait failed: %d\n", ret); + return ret; + } + + if(setup) + { + /* Ignore waits that do not include POLLIN */ + if((fds->events & POLLIN) == 0) + { + canerr("ERROR: Missing POLLIN: revents: %08x\n", fds->revents); + nxsem_post(&priv->devsem); + return -EDEADLK; + } + can_notify(priv->uart_dev); + } + else if(fds->priv) + { + /* This is a request to tear down the poll. */ + struct pollfd **slot = (struct pollfd **)fds->priv; + DEBUGASSERT(slot != NULL); + /* Remove all memory of the poll setup */ + *slot = NULL; + fds->priv = NULL; + } + + nxsem_post(&priv->devsem); + return ret; +} + + +static const struct file_operations can_fops = +{ + can_open, /* open */ + can_close, /* close */ + can_read, /* read */ + can_write, /* write */ + NULL, /* seek */ + can_ioctl, /* ioctl */ + can_poll /* poll */ +}; + + +/**************************************************************************** + * Name: can_register + * + * Description: + * Register /dev/ext_uartN + * + ****************************************************************************/ +static int can_register(FAR const char *devpath) +{ + FAR struct can_dev_s *priv = &g_candev; + int ret = 0; + + nxsem_init(&priv->devsem, 0, 1); + nxsem_init(&priv->waitsem, 0, 0); + nxsem_set_protocol(&priv->waitsem, SEM_PRIO_NONE); + + /* Register the driver */ + ret = register_driver(devpath, &can_fops, 0666, priv); + if(ret < 0) + { + kmm_free(priv); + } + + return ret; +} + +void can_notify(uart_dev_t *dev) +{ + if(dev == g_candev.uart_dev) + nxsem_post(&g_candev.waitsem); +} + +/**************************************************************************** + * Name: can_init + * + * Description: + * Ch376 default initialization function + * + ****************************************************************************/ + +void board_can_initialize(void) +{ + k210_fpioa_config(CAN_CFG_PIN, CAN_FUNC_GPIO(FPIOA_CAN_CFG)); + k210_gpiohs_set_direction(FPIOA_CAN_CFG, GPIO_DM_OUTPUT); + + fpioa_set_function(CAN_RX_PIN, FPIOA_CAN_RX); + fpioa_set_function(CAN_TX_PIN, FPIOA_CAN_TX); + +#if defined(CONFIG_U16550_UART1) + g_candev.dev_name = "/dev/uart1"; + u16550_register(&g_candev.uart_dev, 1); + can_register(can_dev_name); + caninfo("dev %p ok!\n", g_candev.uart_dev); +#endif +} + diff --git a/Ubiquitous/Nuttx_Fusion_XiUOS/aiit_board/xidatong-riscv64/src/k210_can.h b/Ubiquitous/Nuttx_Fusion_XiUOS/aiit_board/xidatong-riscv64/src/k210_can.h new file mode 100755 index 000000000..775a503f1 --- /dev/null +++ b/Ubiquitous/Nuttx_Fusion_XiUOS/aiit_board/xidatong-riscv64/src/k210_can.h @@ -0,0 +1,137 @@ +/* +* Copyright (c) 2022 AIIT XUOS Lab +* XiUOS is licensed under Mulan PSL v2. +* You can use this software according to the terms and conditions of the Mulan PSL v2. +* You may obtain a copy of Mulan PSL v2 at: +* http://license.coscl.org.cn/MulanPSL2 +* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, +* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, +* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. +* See the Mulan PSL v2 for more details. +*/ + +/** +* @file k210_can.h +* @brief define aiit-riscv64-board can function and struct +* @version 1.0 +* @author AIIT XUOS Lab +* @date 2022-09-7 +*/ + +#ifndef __K210_CAN_H_ +#define __K210_CAN_H_ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include "riscv_internal.h" + +#include "k210_config.h" +#include "k210_fpioa.h" +#include "k210_gpiohs.h" +#include "xidatong-riscv64.h" +#include "nuttx/serial/serial.h" +#include "nuttx/serial/uart_16550.h" + + +/* Define CH438 PIN NUM */ +#define CAN_RX_PIN 18 +#define CAN_TX_PIN 19 +#define CAN_CFG_PIN 43 + +/* Define ch438 FPIOA NUMBER */ +#define FPIOA_CAN_RX 64 +#define FPIOA_CAN_TX 65 +#define FPIOA_CAN_CFG 4 + +#define CAN_FUNC_GPIO(n) ((K210_IO_FUNC_GPIOHS0 + n) | K210_IOFLAG_GPIOHS) + +#define CANIOC_SETFREQUENCY _CANIOC(0x0001) /* arg: Pointer to uint32_t frequency value */ +#define CANIOC_GETFREQUENCY _CANIOC(0x0002) /* arg: Pointer to uint32_t frequency value */ + +/* can debug */ +#ifdef CONFIG_DEBUG_CAN_ERROR +# define canerr _err +#else +# define canerr _none +#endif + +#ifdef CONFIG_DEBUG_CAN_WARN +# define canwarn _warn +#else +# define canwarn _none +#endif + +#ifdef CONFIG_DEBUG_CAN_INFO +# define caninfo _info +#else +# define caninfo _none +#endif + +#define CAN_RECV_BUF_SIZE 256 +#define CAN_INCREMENT MSEC2TICK(33) + +struct can_config_s +{ + int (*attach)(FAR const struct can_config_s *config, xcpt_t isr, + FAR void *arg); + void (*enable)(FAR const struct can_config_s *config, bool enable); + void (*clear)(FAR const struct can_config_s *config); + + void (*wakeup)(FAR const struct can_config_s *config); + void (*nreset)(FAR const struct can_config_s *config, bool state); +}; + + +struct can_dev_s +{ + uint8_t crefs; /* Number of times the device + * has been opened */ + uint8_t nwaiters; /* Number of threads waiting for + * data */ + sem_t devsem; /* Manages exclusive access to + * this structure */ + sem_t waitsem; /* Used to wait for the + * availability of data */ + FAR const struct can_config_s *config; /* Board configuration data */ + struct work_s irqwork; /* Supports the interrupt + * handling "bottom half" */ + char *dev_name; + int uart_fd; + uart_dev_t *uart_dev; + int recv_size; + uint8_t recv_buf[CAN_RECV_BUF_SIZE]; +}; + + +void can_notify(uart_dev_t *dev); +void board_can_initialize(void); + +#endif diff --git a/Ubiquitous/Nuttx_Fusion_XiUOS/aiit_board/xidatong-riscv64/src/k210_ch376.c b/Ubiquitous/Nuttx_Fusion_XiUOS/aiit_board/xidatong-riscv64/src/k210_ch376.c new file mode 100755 index 000000000..b5be91fee --- /dev/null +++ b/Ubiquitous/Nuttx_Fusion_XiUOS/aiit_board/xidatong-riscv64/src/k210_ch376.c @@ -0,0 +1,455 @@ +/* +* Copyright (c) 2022 AIIT XUOS Lab +* XiUOS is licensed under Mulan PSL v2. +* You can use this software according to the terms and conditions of the Mulan PSL v2. +* You may obtain a copy of Mulan PSL v2 at: +* http://license.coscl.org.cn/MulanPSL2 +* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, +* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, +* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. +* See the Mulan PSL v2 for more details. +*/ + +/** +* @file k210_ch376.c +* @brief support to register ch376 pointer and function +* @version 1.0 +* @author AIIT XUOS Lab +* @date 2022-07-20 +*/ + +#include +#include +#include +#include "k210_ch376.h" + +/******************************************************************************/ + +#define CH376_INCREMENT MSEC2TICK(33) + +struct ch376_config_s +{ + int (*attach)(FAR const struct ch376_config_s *config, xcpt_t isr, + FAR void *arg); + void (*enable)(FAR const struct ch376_config_s *config, bool enable); + void (*clear)(FAR const struct ch376_config_s *config); + + void (*wakeup)(FAR const struct ch376_config_s *config); + void (*nreset)(FAR const struct ch376_config_s *config, bool state); +}; + +#define CH376_RECV_BUF_SIZE 256 + +struct ch376_dev_s +{ + uint8_t crefs; /* Number of times the device + * has been opened */ + uint8_t nwaiters; /* Number of threads waiting for + * data */ + sem_t devsem; /* Manages exclusive access to + * this structure */ + sem_t waitsem; /* Used to wait for the + * availability of data */ + + FAR const struct ch376_config_s *config;/* Board configuration data */ + struct work_s irqwork; /* Supports the interrupt + * handling "bottom half" */ + char *dev_name; + int uart_fd; + uart_dev_t *uart_dev; + int recv_size; + uint8_t recv_buf[CH376_RECV_BUF_SIZE]; +}; + + +struct ch376_dev_s g_ch376dev; +static char *ch376_dev_name = "/dev/ch376"; + +/******************************************************************************/ + +int ch376_read_buf(void *dev, int *size, uint8_t *buf) +{ + uart_dev_t *uart_dev = (uart_dev_t *)dev; + int cur_size = uart_dev->recv.head - uart_dev->recv.tail; + *size = *size > cur_size ? cur_size : *size; + ch376info("%s received %d\n", __func__, *size); + for(int i = 0; i < *size; i++) + { + ch376info("%x ", uart_dev->recv.buffer[i]); + buf[i] = uart_dev->recv.buffer[i]; + } + ch376info("\n"); + uart_dev->recv.head = uart_dev->recv.tail; + return *size; +} + +/**************************************************************************** + * Name: ch376_data_work + * + * Description: + * thread task ch376_data_work + * + ****************************************************************************/ +static FAR void ch376_data_work(FAR void *arg) +{ + struct ch376_dev_s *ch376_dev = (struct ch376_dev_s *)arg; + uart_dev_t *uart_dev = ch376_dev->uart_dev; + nxsem_wait(&ch376_dev->waitsem); + ch376_dev->recv_size = CH376_RECV_BUF_SIZE; + ch376_read_buf(uart_dev, &ch376_dev->recv_size, ch376_dev->recv_buf); + work_queue(HPWORK, &ch376_dev->irqwork, ch376_data_work, ch376_dev, CH376_INCREMENT); + ch376info("recv size %d!\n", ch376_dev->recv_size); +} + +static int ch376_bringup(struct ch376_dev_s *dev) +{ + dev->uart_fd = open(dev->dev_name, O_RDWR); + work_queue(HPWORK, &dev->irqwork, ch376_data_work, dev, CH376_INCREMENT); + return OK; +} + +static int ch376_write_config(struct ch376_dev_s *dev) +{ + return OK; +} + +static int ch376_shutdown(struct ch376_dev_s *dev) +{ + close(dev->uart_fd); + return OK; +} + +static int ch376_open(FAR struct file *filep) +{ + FAR struct inode *inode; + FAR struct ch376_dev_s *priv; + + uint8_t ref_cnt; + + int ret; + + DEBUGASSERT(filep); + inode = filep->f_inode; + DEBUGASSERT(inode && inode->i_private); + + priv = (FAR struct ch376_dev_s *)inode->i_private; + + /* Get exclusive access to the driver data structure */ + ret = nxsem_wait(&priv->devsem); + + if(ret < 0) + { + ch376err("ERROR: nxsem_wait failed: %d\n", ret); + return ret; + } + + /* Increment the reference count */ + ref_cnt = priv->crefs + 1; + + if(ref_cnt == 0) + { + /* More than 255 opens; uint8_t overflows to zero */ + nxsem_post(&priv->devsem); + return -EMFILE; + } + + /* When the reference increments to 1, this is the first open event + * on the driver.. and the time when we must initialize the driver. + */ + + if(ref_cnt == 1) + { + ret = ch376_bringup(priv); + + if(ret < 0) + { + ch376err("ERROR: ch376_bringup failed: %d\n", ret); + nxsem_post(&priv->devsem); + return ret; + } + + ret = ch376_write_config(priv); + + if(ret < 0) + { + ch376err("ERROR: ch376_write_config failed: %d\n", ret); + nxsem_post(&priv->devsem); + return ret; + } + } + + /* Save the new open count on success */ + priv->crefs = ref_cnt; + + nxsem_post(&priv->devsem); + return ret; +} + +/**************************************************************************** + * Name: ch376_close + ****************************************************************************/ + +static int ch376_close(FAR struct file *filep) +{ + FAR struct inode *inode; + FAR struct ch376_dev_s *priv; + + int ret; + + DEBUGASSERT(filep); + inode = filep->f_inode; + DEBUGASSERT(inode && inode->i_private); + + priv = (FAR struct ch376_dev_s *)inode->i_private; + + /* Get exclusive access to the driver data structure */ + ret = nxsem_wait(&priv->devsem); + + if(ret < 0) + { + ch376err("ERROR: nxsem_wait failed: %d\n", ret); + return ret; + } + + /* Decrement the reference count unless it would decrement a negative + * value. + */ + + if(priv->crefs >= 1) + { + priv->crefs--; + } + + /* When the count decrements to zero, there are no further open references + * to the driver and it can be uninitialized. + */ + + if(priv->crefs == 0) + { + ch376_shutdown(priv); + } + + nxsem_post(&priv->devsem); + return OK; +} + +/**************************************************************************** + * Name: ch376_read + ****************************************************************************/ + +static ssize_t ch376_read(FAR struct file *filep, FAR char *buffer, size_t len) +{ + FAR struct inode *inode; + FAR struct ch376_dev_s *priv; + int ret, buf_size = len; + + DEBUGASSERT(filep); + inode = filep->f_inode; + DEBUGASSERT(inode && inode->i_private); + + priv = (FAR struct ch376_dev_s *)inode->i_private; + + ret = nxsem_wait(&priv->devsem); + + if(ret < 0) + { + ch376err("ERROR: nxsem_wait failed: %d\n", ret); + return ret; + } + + buf_size = len > priv->recv_size ? priv->recv_size : len; + memcpy(buffer, priv->recv_buf, buf_size); + nxsem_post(&priv->devsem); + return ret; +} + + +/**************************************************************************** + * Name: ch376_write + ****************************************************************************/ + +static ssize_t ch376_write(FAR struct file *filep, FAR const char *buffer, size_t len) +{ + FAR struct inode *inode; + FAR struct ch376_dev_s *priv; + int ret; + DEBUGASSERT(filep); + inode = filep->f_inode; + DEBUGASSERT(inode && inode->i_private); + priv = (FAR struct ch376_dev_s *)inode->i_private; + + /* Get exclusive access to the driver data structure */ + ret = nxsem_wait(&priv->devsem); + + if(ret < 0) + { + ch376err("ERROR: nxsem_wait failed: %d\n", ret); + return ret; + } + + ret = write(priv->uart_fd, buffer, len); + + nxsem_post(&priv->devsem); + return ret; +} + +/**************************************************************************** + * Name: ch376_ioctl + ****************************************************************************/ + +static int ch376_ioctl(FAR struct file *filep, int cmd, unsigned long arg) +{ + FAR struct inode *inode; + FAR struct ch376_dev_s *priv; + + int ret; + + DEBUGASSERT(filep); + inode = filep->f_inode; + DEBUGASSERT(inode && inode->i_private); + + priv = (FAR struct ch376_dev_s *)inode->i_private; + + /* Get exclusive access to the driver data structure */ + ret = nxsem_wait(&priv->devsem); + + if(ret < 0) + { + ch376err("ERROR: nxsem_wait failed: %d\n", ret); + return ret; + } + + /* Process the IOCTL by command */ + + switch(cmd) + { + default: + ret = -ENOTTY; + break; + } + + nxsem_post(&priv->devsem); + return ret; +} + +/**************************************************************************** + * Name: ch376_poll + ****************************************************************************/ + +static int ch376_poll(FAR struct file *filep, FAR struct pollfd *fds, bool setup) +{ + FAR struct inode *inode; + FAR struct ch376_dev_s *priv; + + int ret; + + ch376info("setup: %d\n", (int)setup); + + DEBUGASSERT(filep && fds); + inode = filep->f_inode; + DEBUGASSERT(inode && inode->i_private); + + priv = (FAR struct ch376_dev_s *)inode->i_private; + + /* Are we setting up the poll? Or tearing it down? */ + ret = nxsem_wait(&priv->devsem); + + if(ret < 0) + { + ch376err("ERROR: nxsem_wait failed: %d\n", ret); + return ret; + } + + if(setup) + { + /* Ignore waits that do not include POLLIN */ + if((fds->events & POLLIN) == 0) + { + ch376err("ERROR: Missing POLLIN: revents: %08x\n", fds->revents); + nxsem_post(&priv->devsem); + return -EDEADLK; + } + + /* Should we immediately notify on any of the requested events? */ + ch376_notify(priv->uart_dev); + } + else if(fds->priv) + { + /* This is a request to tear down the poll. */ + struct pollfd **slot = (struct pollfd **)fds->priv; + DEBUGASSERT(slot != NULL); + /* Remove all memory of the poll setup */ + *slot = NULL; + fds->priv = NULL; + } + + nxsem_post(&priv->devsem); + return ret; +} + + +static const struct file_operations ch376_fops = +{ + ch376_open, /* open */ + ch376_close, /* close */ + ch376_read, /* read */ + ch376_write, /* write */ + NULL, /* seek */ + ch376_ioctl, /* ioctl */ + ch376_poll /* poll */ +}; + + +/**************************************************************************** + * Name: ch376_register + * + * Description: + * Register /dev/ext_uartN + * + ****************************************************************************/ +static int ch376_register(FAR const char *devpath) +{ + FAR struct ch376_dev_s *priv = &g_ch376dev; + int ret = 0; + + nxsem_init(&priv->devsem, 0, 1); + nxsem_init(&priv->waitsem, 0, 0); + nxsem_set_protocol(&priv->waitsem, SEM_PRIO_NONE); + + /* Register the driver */ + ret = register_driver(devpath, &ch376_fops, 0666, priv); + if(ret < 0) + { + kmm_free(priv); + } + + return ret; +} + +void ch376_notify(uart_dev_t *dev) +{ + if(dev == g_ch376dev.uart_dev) + nxsem_post(&g_ch376dev.waitsem); +} + +/**************************************************************************** + * Name: ch376_init + * + * Description: + * Ch376 default initialization function + * + ****************************************************************************/ + +void board_ch376_initialize(void) +{ + fpioa_set_function(CH376_TX_PIN, FPIOA_CH376_TX); + fpioa_set_function(CH376_RX_PIN, FPIOA_CH376_RX); + +#if defined(CONFIG_U16550_UART3) + g_ch376dev.dev_name = "/dev/uart3"; + u16550_register(&g_ch376dev.uart_dev, 3); + ch376_register(ch376_dev_name); + ch376info("dev %p ok!\n", g_ch376dev.uart_dev); +#endif +} + diff --git a/Ubiquitous/Nuttx_Fusion_XiUOS/aiit_board/xidatong-riscv64/src/k210_ch376.h b/Ubiquitous/Nuttx_Fusion_XiUOS/aiit_board/xidatong-riscv64/src/k210_ch376.h new file mode 100755 index 000000000..26e4da599 --- /dev/null +++ b/Ubiquitous/Nuttx_Fusion_XiUOS/aiit_board/xidatong-riscv64/src/k210_ch376.h @@ -0,0 +1,111 @@ +/* +* Copyright (c) 2022 AIIT XUOS Lab +* XiUOS is licensed under Mulan PSL v2. +* You can use this software according to the terms and conditions of the Mulan PSL v2. +* You may obtain a copy of Mulan PSL v2 at: +* http://license.coscl.org.cn/MulanPSL2 +* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, +* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, +* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. +* See the Mulan PSL v2 for more details. +*/ + +/** +* @file k210_ch376.h +* @brief define aiit-riscv64-board ch376 function and struct +* @version 1.0 +* @author AIIT XUOS Lab +* @date 2022-07-19 +*/ + +#ifndef __K210_CH376_H_ +#define __K210_CH376_H_ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include "riscv_internal.h" + +#include "k210_config.h" +#include "k210_fpioa.h" +#include "k210_gpiohs.h" +#include "xidatong-riscv64.h" +#include "nuttx/serial/serial.h" +#include "nuttx/serial/uart_16550.h" + + +/* Define CH438 PIN NUM */ +#define CH376_RX_PIN 22 +#define CH376_TX_PIN 23 + +/* Define ch438 FPIOA NUMBER */ +#define FPIOA_CH376_RX 68 +#define FPIOA_CH376_TX 69 + +#define CH376_CMD_HEADER {0x57, 0xAB} + +#define CH376_CMD_SIZE 256 + +#define CH376_CMD_SET_MODE 0x15 +#define CH376_CMD_USB_MODE 0x5 +#define CH376_CMD_SDC_MODE 0x3 + +#define CH376_CMD_RD_USB 0x27 + +#define CH376_CMD_DISK_CONN 0x30 +#define CH376_CMD_DISK_MOUNT 0x31 +#define CH376_CMD_DISK_QUERY 0x3F + +#define CH376_CMD_OPEN_FILE 0x32 + + +/* ch376 debug */ +#ifdef CONFIG_DEBUG_CH376_ERROR +# define ch376err _err +#else +# define ch376err _none +#endif + +#ifdef CONFIG_DEBUG_CH376_WARN +# define ch376warn _warn +#else +# define ch376warn _none +#endif + +#ifdef CONFIG_DEBUG_CH376_INFO +# define ch376info _info +#else +# define ch376info _none +#endif + +void ch376_notify(uart_dev_t *dev); +void board_ch376_initialize(void); + +#endif diff --git a/Ubiquitous/Nuttx_Fusion_XiUOS/aiit_board/xidatong-riscv64/src/k210_ec200.c b/Ubiquitous/Nuttx_Fusion_XiUOS/aiit_board/xidatong-riscv64/src/k210_ec200.c new file mode 100755 index 000000000..e73cafd37 --- /dev/null +++ b/Ubiquitous/Nuttx_Fusion_XiUOS/aiit_board/xidatong-riscv64/src/k210_ec200.c @@ -0,0 +1,458 @@ +/* +* Copyright (c) 2022 AIIT XUOS Lab +* XiUOS is licensed under Mulan PSL v2. +* You can use this software according to the terms and conditions of the Mulan PSL v2. +* You may obtain a copy of Mulan PSL v2 at: +* http://license.coscl.org.cn/MulanPSL2 +* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, +* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, +* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. +* See the Mulan PSL v2 for more details. +*/ + +/** +* @file k210_ec200.c +* @brief support to register ch436 pointer and function +* @version 1.0 +* @author AIIT XUOS Lab +* @date 2022-07-20 +*/ + +#include +#include +#include +#include "ctype.h" +#include "k210_ec200.h" + +#define ec_print printf + +/******************************************************************************/ + +struct ec200_dev_s g_ec200dev; +static char *ec200_dev_name = "/dev/ec200"; + +/******************************************************************************/ + +void ec200_print_buf(int size, uint8_t *buf) +{ + char ch[10] = {0}; + char temp[256] = {0}; + + if(size >= 256) + size = 256; + + for(int i = 0; i < size; i++) + { + if(buf[i] == '\r') + { + strcat(temp, "\\r"); + } + else if(buf[i] == '\n') + { + strcat(temp, "\\n"); + } + else if(isascii(buf[i])) + { + snprintf(ch, sizeof(ch), "%c", buf[i]); + strcat(temp, ch); + } + else + { + snprintf(ch, sizeof(ch), "%#x ", buf[i]); + strcat(temp, ch); + } + } + if(size) + ec_print("ec200 read %d data: %s\n", size, temp); +} + +int ec200_read_buf(void *dev, int *size, uint8_t *buf) +{ + uart_dev_t *uart_dev = (uart_dev_t *)dev; + int cur_size = uart_dev->recv.head - uart_dev->recv.tail; + *size = *size > cur_size ? cur_size : *size; + memcpy(buf, uart_dev->recv.buffer, *size); + uart_dev->recv.head = uart_dev->recv.tail; + ec200_print_buf(*size, buf); + return *size; +} + +/**************************************************************************** + * Name: ec200_data_work + * + * Description: + * thread task ec200_data_work + * + ****************************************************************************/ +static FAR void ec200_data_work(FAR void *arg) +{ + struct ec200_dev_s *ec200_dev = (struct ec200_dev_s *)arg; + uart_dev_t *uart_dev = ec200_dev->uart_dev; + nxsem_wait(&ec200_dev->waitsem); + ec200_dev->recv_size = EC200_RECV_BUF_SIZE; + ec200_read_buf(uart_dev, &ec200_dev->recv_size, ec200_dev->recv_buf); + work_queue(HPWORK, &ec200_dev->irqwork, ec200_data_work, ec200_dev, EC200_INCREMENT); +// ec200info("uart size %d ok!\n", ec200_dev->recv_size); +} + +static int ec200_bringup(struct ec200_dev_s *dev) +{ +// struct ec200_dev_s *ec200_dev = &g_ec200dev; + + dev->uart_fd = open(dev->dev_name, O_RDWR); + + ec200info("open %s fd = %d\n", dev->dev_name, dev->uart_fd); + + work_queue(HPWORK, &dev->irqwork, ec200_data_work, dev, EC200_INCREMENT); + return OK; +} + +static int ec200_write_config(struct ec200_dev_s *dev) +{ + return OK; +} + +static int ec200_shutdown(struct ec200_dev_s *dev) +{ + close(dev->uart_fd); + return OK; +} + +static int ec200_open(FAR struct file *filep) +{ + FAR struct inode *inode; + FAR struct ec200_dev_s *priv; + + uint8_t ref_cnt; + + int ret; + + DEBUGASSERT(filep); + inode = filep->f_inode; + DEBUGASSERT(inode && inode->i_private); + + priv = (FAR struct ec200_dev_s *)inode->i_private; + + /* Get exclusive access to the driver data structure */ + ret = nxsem_wait(&priv->devsem); + + if(ret < 0) + { + ec200err("ERROR: nxsem_wait failed: %d\n", ret); + return ret; + } + + /* Increment the reference count */ + ref_cnt = priv->crefs + 1; + + if(ref_cnt == 0) + { + /* More than 255 opens; uint8_t overflows to zero */ + nxsem_post(&priv->devsem); + return -EMFILE; + } + + /* When the reference increments to 1, this is the first open event + * on the driver.. and the time when we must initialize the driver. + */ + + if(ref_cnt == 1) + { + ret = ec200_bringup(priv); + + if(ret < 0) + { + ec200err("ERROR: ec200_bringup failed: %d\n", ret); + nxsem_post(&priv->devsem); + return ret; + } + + ret = ec200_write_config(priv); + + if(ret < 0) + { + ec200err("ERROR: ec200_write_config failed: %d\n", ret); + nxsem_post(&priv->devsem); + return ret; + } + } + + /* Save the new open count on success */ + priv->crefs = ref_cnt; + + nxsem_post(&priv->devsem); + return ret; +} + +/**************************************************************************** + * Name: ec200_close + ****************************************************************************/ + +static int ec200_close(FAR struct file *filep) +{ + FAR struct inode *inode; + FAR struct ec200_dev_s *priv; + + int ret; + + DEBUGASSERT(filep); + inode = filep->f_inode; + DEBUGASSERT(inode && inode->i_private); + + priv = (FAR struct ec200_dev_s *)inode->i_private; + + /* Get exclusive access to the driver data structure */ + ret = nxsem_wait(&priv->devsem); + + if(ret < 0) + { + ec200err("ERROR: nxsem_wait failed: %d\n", ret); + return ret; + } + + /* Decrement the reference count unless it would decrement a negative + * value. + */ + + if(priv->crefs >= 1) + { + priv->crefs--; + } + + /* When the count decrements to zero, there are no further open references + * to the driver and it can be uninitialized. + */ + + if(priv->crefs == 0) + { + ec200_shutdown(priv); + } + + nxsem_post(&priv->devsem); + return OK; +} + +/**************************************************************************** + * Name: ec200_read + ****************************************************************************/ + +static ssize_t ec200_read(FAR struct file *filep, FAR char *buffer, size_t len) +{ + FAR struct inode *inode; + FAR struct ec200_dev_s *priv; + int ret, buf_size = len; + + DEBUGASSERT(filep); + inode = filep->f_inode; + DEBUGASSERT(inode && inode->i_private); + + priv = (FAR struct ec200_dev_s *)inode->i_private; + + ret = nxsem_wait(&priv->devsem); + + if(ret < 0) + { + ec200err("ERROR: nxsem_wait failed: %d\n", ret); + return ret; + } + + buf_size = len > priv->recv_size ? priv->recv_size : len; + memcpy(buffer, priv->recv_buf, buf_size); + nxsem_post(&priv->devsem); + return ret; +} + + +/**************************************************************************** + * Name: ec200_write + ****************************************************************************/ + +static ssize_t ec200_write(FAR struct file *filep, FAR const char *buffer, size_t len) +{ + FAR struct inode *inode; + FAR struct ec200_dev_s *priv; + int ret; + DEBUGASSERT(filep); + inode = filep->f_inode; + DEBUGASSERT(inode && inode->i_private); + priv = (FAR struct ec200_dev_s *)inode->i_private; + + /* Get exclusive access to the driver data structure */ + ret = nxsem_wait(&priv->devsem); + + if(ret < 0) + { + ec200err("ERROR: nxsem_wait failed: %d\n", ret); + return ret; + } + + ret = write(priv->uart_fd, buffer, len); + ec200info("write fd %d len %ld ret = %d\n", priv->uart_fd, len, ret); + nxsem_post(&priv->devsem); + return ret; +} + +/**************************************************************************** + * Name: ec200_ioctl + ****************************************************************************/ + +static int ec200_ioctl(FAR struct file *filep, int cmd, unsigned long arg) +{ + FAR struct inode *inode; + FAR struct ec200_dev_s *priv; + + int ret; + + DEBUGASSERT(filep); + inode = filep->f_inode; + DEBUGASSERT(inode && inode->i_private); + + priv = (FAR struct ec200_dev_s *)inode->i_private; + + /* Get exclusive access to the driver data structure */ + ret = nxsem_wait(&priv->devsem); + + if(ret < 0) + { + ec200err("ERROR: nxsem_wait failed: %d\n", ret); + return ret; + } + + /* Process the IOCTL by command */ + + switch(cmd) + { +// case TSIOC_SETFREQUENCY: /* arg: Pointer to uint32_t frequency value */ +// FAR uint32_t *ptr = (FAR uint32_t *)((uintptr_t)arg); +// DEBUGASSERT(priv->config != NULL && ptr != NULL); +// break; + + default: + ret = -ENOTTY; + break; + } + + nxsem_post(&priv->devsem); + return ret; +} + +/**************************************************************************** + * Name: ec200_poll + ****************************************************************************/ + +static int ec200_poll(FAR struct file *filep, FAR struct pollfd *fds, bool setup) +{ + FAR struct inode *inode; + FAR struct ec200_dev_s *priv; + + int ret; + + ec200info("setup: %d\n", (int)setup); + + DEBUGASSERT(filep && fds); + inode = filep->f_inode; + DEBUGASSERT(inode && inode->i_private); + + priv = (FAR struct ec200_dev_s *)inode->i_private; + + /* Are we setting up the poll? Or tearing it down? */ + ret = nxsem_wait(&priv->devsem); + + if(ret < 0) + { + ec200err("ERROR: nxsem_wait failed: %d\n", ret); + return ret; + } + + if(setup) + { + /* Ignore waits that do not include POLLIN */ + if((fds->events & POLLIN) == 0) + { + ec200err("ERROR: Missing POLLIN: revents: %08x\n", fds->revents); + nxsem_post(&priv->devsem); + return -EDEADLK; + } + ec200_notify(priv->uart_dev); + } + else if(fds->priv) + { + /* This is a request to tear down the poll. */ + struct pollfd **slot = (struct pollfd **)fds->priv; + DEBUGASSERT(slot != NULL); + /* Remove all memory of the poll setup */ + *slot = NULL; + fds->priv = NULL; + } + + nxsem_post(&priv->devsem); + return ret; +} + + +static const struct file_operations ec200_fops = +{ + ec200_open, /* open */ + ec200_close, /* close */ + ec200_read, /* read */ + ec200_write, /* write */ + NULL, /* seek */ + ec200_ioctl, /* ioctl */ + ec200_poll /* poll */ +}; + + +/**************************************************************************** + * Name: ec200_register + * + * Description: + * Register /dev/ext_uartN + * + ****************************************************************************/ +static int ec200_register(FAR const char *devpath) +{ + FAR struct ec200_dev_s *priv = &g_ec200dev; + int ret = 0; + + nxsem_init(&priv->devsem, 0, 1); + nxsem_init(&priv->waitsem, 0, 0); + nxsem_set_protocol(&priv->waitsem, SEM_PRIO_NONE); + + /* Register the driver */ + ret = register_driver(devpath, &ec200_fops, 0666, priv); + if(ret < 0) + { + kmm_free(priv); + } + + return ret; +} + +void ec200_notify(uart_dev_t *dev) +{ + if(dev == g_ec200dev.uart_dev) + nxsem_post(&g_ec200dev.waitsem); +} + +/**************************************************************************** + * Name: ec200_init + * + * Description: + * Ch376 default initialization function + * + ****************************************************************************/ + +void board_ec200_initialize(void) +{ +#if defined(CONFIG_U16550_UART2) + + fpioa_set_function(EC200_RX_PIN, FPIOA_EC200_RX); + fpioa_set_function(EC200_TX_PIN, FPIOA_EC200_TX); + + g_ec200dev.dev_name = "/dev/uart2"; + u16550_register(&g_ec200dev.uart_dev, 2); + ec200_register(ec200_dev_name); + ec200info("dev %p ok!\n", g_ec200dev.uart_dev); +#endif +} + diff --git a/Ubiquitous/Nuttx_Fusion_XiUOS/aiit_board/xidatong-riscv64/src/k210_ec200.h b/Ubiquitous/Nuttx_Fusion_XiUOS/aiit_board/xidatong-riscv64/src/k210_ec200.h new file mode 100755 index 000000000..491af8b3c --- /dev/null +++ b/Ubiquitous/Nuttx_Fusion_XiUOS/aiit_board/xidatong-riscv64/src/k210_ec200.h @@ -0,0 +1,132 @@ +/* +* Copyright (c) 2022 AIIT XUOS Lab +* XiUOS is licensed under Mulan PSL v2. +* You can use this software according to the terms and conditions of the Mulan PSL v2. +* You may obtain a copy of Mulan PSL v2 at: +* http://license.coscl.org.cn/MulanPSL2 +* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, +* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, +* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. +* See the Mulan PSL v2 for more details. +*/ + +/** +* @file k210_ec200.h +* @brief define aiit-riscv64-board ec200 function and struct +* @version 1.0 +* @author AIIT XUOS Lab +* @date 2022-09-7 +*/ + +#ifndef __K210_EC200_H_ +#define __K210_EC200_H_ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include "riscv_internal.h" + +#include "k210_config.h" +#include "k210_fpioa.h" +#include "k210_gpiohs.h" +#include "xidatong-riscv64.h" +#include "nuttx/serial/serial.h" +#include "nuttx/serial/uart_16550.h" + + +/* Define CH438 PIN NUM */ +#define EC200_RX_PIN 21 +#define EC200_TX_PIN 20 + +/* Define ch438 FPIOA NUMBER */ +#define FPIOA_EC200_RX 66 +#define FPIOA_EC200_TX 67 + + +/* ec200 debug */ +#ifdef CONFIG_DEBUG_EC200_ERROR +# define ec200err _err +#else +# define ec200err _none +#endif + +#ifdef CONFIG_DEBUG_EC200_WARN +# define ec200warn _warn +#else +# define ec200warn _none +#endif + +#ifdef CONFIG_DEBUG_EC200_INFO +# define ec200info _info +#else +# define ec200info _none +#endif + +#define EC200_RECV_BUF_SIZE 256 +#define EC200_INCREMENT MSEC2TICK(33) + +struct ec200_config_s +{ + int (*attach)(FAR const struct ec200_config_s *config, xcpt_t isr, + FAR void *arg); + void (*enable)(FAR const struct ec200_config_s *config, bool enable); + void (*clear)(FAR const struct ec200_config_s *config); + + void (*wakeup)(FAR const struct ec200_config_s *config); + void (*nreset)(FAR const struct ec200_config_s *config, bool state); +}; + + +struct ec200_dev_s +{ + uint8_t crefs; /* Number of times the device + * has been opened */ + uint8_t nwaiters; /* Number of threads waiting for + * data */ + sem_t devsem; /* Manages exclusive access to + * this structure */ + sem_t waitsem; /* Used to wait for the + * availability of data */ + + FAR const struct ec200_config_s *config;/* Board configuration data */ + struct work_s irqwork; /* Supports the interrupt + * handling "bottom half" */ + char *dev_name; + int uart_fd; + uart_dev_t *uart_dev; + int recv_size; + uint8_t recv_buf[EC200_RECV_BUF_SIZE]; +}; + + +void ec200_notify(uart_dev_t *dev); +void board_ec200_initialize(void); + +#endif diff --git a/Ubiquitous/Nuttx_Fusion_XiUOS/app_match_nuttx/apps/nshlib/nsh.h b/Ubiquitous/Nuttx_Fusion_XiUOS/app_match_nuttx/apps/nshlib/nsh.h index df3e0f488..fade188ab 100644 --- a/Ubiquitous/Nuttx_Fusion_XiUOS/app_match_nuttx/apps/nshlib/nsh.h +++ b/Ubiquitous/Nuttx_Fusion_XiUOS/app_match_nuttx/apps/nshlib/nsh.h @@ -1454,6 +1454,22 @@ int nsh_foreach_var(FAR struct nsh_vtbl_s *vtbl, nsh_foreach_var_t cb, int cmd_Ch438(FAR struct nsh_vtbl_s *vtbl, int argc, char **argv); #endif +#if defined(CONFIG_BSP_USING_CH376) && !defined(CONFIG_NSH_DISABLE_CH376) + int cmd_Ch376(FAR struct nsh_vtbl_s *vtbl, int argc, char **argv); +#endif + +#if defined(CONFIG_BSP_USING_EC200) && !defined(CONFIG_NSH_DISABLE_EC200) + int cmd_EC200(FAR struct nsh_vtbl_s *vtbl, int argc, char **argv); +#endif + +#if defined(CONFIG_BSP_USING_CAN) && !defined(CONFIG_NSH_DISABLE_CAN) + int cmd_CAN(FAR struct nsh_vtbl_s *vtbl, int argc, char **argv); +#endif + +#if defined(CONFIG_BSP_USING_ESP8266) && !defined(CONFIG_NSH_DISABLE_ESP8266) + int cmd_Esp8266(FAR struct nsh_vtbl_s *vtbl, int argc, char **argv); +#endif + #if defined(CONFIG_K210_LCD) && !defined(CONFIG_NSH_DISABLE_LCD) int cmd_Lcd(FAR struct nsh_vtbl_s *vtbl, int argc, char **argv); #endif diff --git a/Ubiquitous/Nuttx_Fusion_XiUOS/app_match_nuttx/apps/nshlib/nsh_Applicationscmd.c b/Ubiquitous/Nuttx_Fusion_XiUOS/app_match_nuttx/apps/nshlib/nsh_Applicationscmd.c index ef6d6b2be..d076f1a1a 100644 --- a/Ubiquitous/Nuttx_Fusion_XiUOS/app_match_nuttx/apps/nshlib/nsh_Applicationscmd.c +++ b/Ubiquitous/Nuttx_Fusion_XiUOS/app_match_nuttx/apps/nshlib/nsh_Applicationscmd.c @@ -51,6 +51,58 @@ int cmd_Ch438(FAR struct nsh_vtbl_s *vtbl, int argc, char **argv) } #endif +/**************************************************************************** + * Name: cmd_Ch376 + ****************************************************************************/ +#if defined(CONFIG_BSP_USING_CH376) && !defined(CONFIG_NSH_DISABLE_CH376) +extern void CH376Demo(void); +int cmd_Ch376(FAR struct nsh_vtbl_s *vtbl, int argc, char **argv) +{ + nsh_output(vtbl, "Hello, ch376!\n"); + CH376Demo(); + return OK; +} +#endif + +/**************************************************************************** + * Name: cmd_Ch376 + ****************************************************************************/ +#if defined(CONFIG_BSP_USING_EC200) && !defined(CONFIG_NSH_DISABLE_EC200) +extern void EC200Demo(void); +int cmd_EC200(FAR struct nsh_vtbl_s *vtbl, int argc, char **argv) +{ + nsh_output(vtbl, "Hello, EC200!\n"); + EC200Demo(); + return OK; +} +#endif + +/**************************************************************************** + * Name: cmd_CAN + ****************************************************************************/ +#if defined(CONFIG_BSP_USING_CAN) && !defined(CONFIG_NSH_DISABLE_CAN) +extern void CanDemo(void); +int cmd_CAN(FAR struct nsh_vtbl_s *vtbl, int argc, char **argv) +{ + nsh_output(vtbl, "Hello, CAN!\n"); + CanDemo(); + return OK; +} +#endif + +/**************************************************************************** + * Name: cmd_Esp8266 + ****************************************************************************/ +#if defined(CONFIG_BSP_USING_ESP8266) && !defined(CONFIG_NSH_DISABLE_ESP8266) +extern void Esp8266Demo(void); +int cmd_Esp8266(FAR struct nsh_vtbl_s *vtbl, int argc, char **argv) +{ + nsh_output(vtbl, "Hello, Esp8266!\n"); + Esp8266Demo(); + return OK; +} +#endif + /**************************************************************************** * Name: cmd_lcd ****************************************************************************/ diff --git a/Ubiquitous/Nuttx_Fusion_XiUOS/app_match_nuttx/apps/nshlib/nsh_command.c b/Ubiquitous/Nuttx_Fusion_XiUOS/app_match_nuttx/apps/nshlib/nsh_command.c index 7f542859b..260c3ea62 100644 --- a/Ubiquitous/Nuttx_Fusion_XiUOS/app_match_nuttx/apps/nshlib/nsh_command.c +++ b/Ubiquitous/Nuttx_Fusion_XiUOS/app_match_nuttx/apps/nshlib/nsh_command.c @@ -597,11 +597,27 @@ static const struct cmdmap_s g_cmdmap[] = #endif #if defined(CONFIG_BSP_USING_CH438) && !defined(CONFIG_NSH_DISABLE_CH438) - { "ch438", cmd_Ch438, 1, 1, "[ch438 demo cmd.]" }, + { "ch438", cmd_Ch438, 1, 1, "[ch438 demo cmd.]" }, +#endif + +#if defined(CONFIG_BSP_USING_CH376) && !defined(CONFIG_NSH_DISABLE_CH376) + { "ch376", cmd_Ch376, 1, 1, "[ch376 demo cmd.]" }, +#endif + +#if defined(CONFIG_BSP_USING_EC200) && !defined(CONFIG_NSH_DISABLE_EC200) + { "ec200", cmd_EC200, 1, 1, "[ec200 demo cmd.]" }, +#endif + +#if defined(CONFIG_BSP_USING_CAN) && !defined(CONFIG_NSH_DISABLE_CAN) + { "can", cmd_CAN, 1, 1, "[can demo cmd.]" }, +#endif + +#if defined(CONFIG_BSP_USING_ESP8266) && !defined(CONFIG_NSH_DISABLE_ESP8266) + { "esp8266", cmd_Esp8266, 1, 1, "[can demo cmd.]" }, #endif #if defined(CONFIG_K210_LCD) && !defined(CONFIG_NSH_DISABLE_LCD) - { "lcd", cmd_Lcd, 1, 1, "[LCD demo cmd.]" }, + { "lcd", cmd_Lcd, 1, 1, "[LCD demo cmd.]" }, #endif #if defined(CONFIG_APPLICATION_SENSOR_HCHO_TB600B_WQ_HCHO1OS) && !defined(CONFIG_NSH_DISABLE_HCHO_TB600B_WQ_HCHO1OS) diff --git a/Ubiquitous/Nuttx_Fusion_XiUOS/app_match_nuttx/nuttx/arch/risc-v/include/k210/irq.h b/Ubiquitous/Nuttx_Fusion_XiUOS/app_match_nuttx/nuttx/arch/risc-v/include/k210/irq.h new file mode 100755 index 000000000..a800588bb --- /dev/null +++ b/Ubiquitous/Nuttx_Fusion_XiUOS/app_match_nuttx/nuttx/arch/risc-v/include/k210/irq.h @@ -0,0 +1,49 @@ +/**************************************************************************** + * arch/risc-v/include/k210/irq.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_RISCV_INCLUDE_K210_IRQ_H +#define __ARCH_RISCV_INCLUDE_K210_IRQ_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Map RISC-V exception code to NuttX IRQ */ + +#ifdef CONFIG_K210_WITH_QEMU +#define K210_IRQ_UART0 (RISCV_IRQ_MEXT + 4) +#else +#define K210_IRQ_UART0 (RISCV_IRQ_MEXT + 33) +#define K210_IRQ_UART1 (RISCV_IRQ_MEXT + 11) +#define K210_IRQ_UART2 (RISCV_IRQ_MEXT + 12) +#define K210_IRQ_UART3 (RISCV_IRQ_MEXT + 13) +#endif + +/* Total number of IRQs */ + +#define NR_IRQS (64 + 16 +16) + +#endif /* __ARCH_RISCV_INCLUDE_K210_IRQ_H */ diff --git a/Ubiquitous/Nuttx_Fusion_XiUOS/app_match_nuttx/nuttx/arch/risc-v/src/k210/Make.defs b/Ubiquitous/Nuttx_Fusion_XiUOS/app_match_nuttx/nuttx/arch/risc-v/src/k210/Make.defs index 63dbba19a..7eca47596 100644 --- a/Ubiquitous/Nuttx_Fusion_XiUOS/app_match_nuttx/nuttx/arch/risc-v/src/k210/Make.defs +++ b/Ubiquitous/Nuttx_Fusion_XiUOS/app_match_nuttx/nuttx/arch/risc-v/src/k210/Make.defs @@ -55,7 +55,7 @@ endif # Specify our C code within this directory to be included CHIP_CSRCS = k210_allocateheap.c k210_clockconfig.c CHIP_CSRCS += k210_irq.c k210_irq_dispatch.c k210_systemreset.c -CHIP_CSRCS += k210_lowputc.c k210_serial.c k210_fpioa.c +CHIP_CSRCS += k210_lowputc.c k210_serial.c k210_fpioa.c fpioa.c CHIP_CSRCS += k210_start.c k210_timerisr.c k210_gpiohs.c k210_gpio.c CHIP_CSRCS += k210_sysctl.c diff --git a/Ubiquitous/Nuttx_Fusion_XiUOS/app_match_nuttx/nuttx/arch/risc-v/src/k210/fpioa.c b/Ubiquitous/Nuttx_Fusion_XiUOS/app_match_nuttx/nuttx/arch/risc-v/src/k210/fpioa.c new file mode 100755 index 000000000..093ae74ec --- /dev/null +++ b/Ubiquitous/Nuttx_Fusion_XiUOS/app_match_nuttx/nuttx/arch/risc-v/src/k210/fpioa.c @@ -0,0 +1,4932 @@ +/* Copyright 2018 Canaan Inc. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include +#include +#include "fpioa.h" +#include "k210_fpioa.h" +#include "k210_sysctl.h" +#include "k210_memorymap.h" + +volatile fpioa_t *const fpioa = (volatile fpioa_t *)K210_FPIOA_BASE; + +/** + * @brief Internal used FPIOA function initialize cell + * + * This is NOT fpioa_io_config_t, can't assign directly + * + */ +typedef struct _fpioa_assign_t +{ + uint32_t ch_sel : 8; + /* Channel select from 256 input. */ + uint32_t ds : 4; + /* Driving selector. */ + uint32_t oe_en : 1; + /* Static output enable, will AND with OE_INV. */ + uint32_t oe_inv : 1; + /* Invert output enable. */ + uint32_t do_sel : 1; + /* Data output select: 0 for DO, 1 for OE. */ + uint32_t do_inv : 1; + /* Invert the result of data output select (DO_SEL). */ + uint32_t pu : 1; + /* Pull up enable. 0 for nothing, 1 for pull up. */ + uint32_t pd : 1; + /* Pull down enable. 0 for nothing, 1 for pull down. */ + uint32_t resv0 : 1; + /* Reserved bits. */ + uint32_t sl : 1; + /* Slew rate control enable. */ + uint32_t ie_en : 1; + /* Static input enable, will AND with IE_INV. */ + uint32_t ie_inv : 1; + /* Invert input enable. */ + uint32_t di_inv : 1; + /* Invert Data input. */ + uint32_t st : 1; + /* Schmitt trigger. */ + uint32_t tie_en : 1; + /* Input tie enable, 1 for enable, 0 for disable. */ + uint32_t tie_val : 1; + /* Input tie value, 1 for high, 0 for low. */ + uint32_t resv1 : 5; + /* Reserved bits. */ + uint32_t pad_di : 1; + /* Read current PAD's data input. */ +} __attribute__((packed, aligned(4))) fpioa_assign_t; + +/* Function list */ +static const fpioa_assign_t function_config[FUNC_MAX] = + { + {.ch_sel = FUNC_JTAG_TCLK, + .ds = 0x0, + .oe_en = 0, + .oe_inv = 0, + .do_sel = 0, + .do_inv = 0, + .pu = 0, + .pd = 0, + .resv1 = 0, + .sl = 0, + .ie_en = 1, + .ie_inv = 0, + .di_inv = 0, + .st = 1, + .tie_en = 0, + .tie_val = 0, + .resv0 = 0, + .pad_di = 0}, + {.ch_sel = FUNC_JTAG_TDI, + .ds = 0x0, + .oe_en = 0, + .oe_inv = 0, + .do_sel = 0, + .do_inv = 0, + .pu = 0, + .pd = 0, + .resv1 = 0, + .sl = 0, + .ie_en = 1, + .ie_inv = 0, + .di_inv = 0, + .st = 1, + .tie_en = 0, + .tie_val = 0, + .resv0 = 0, + .pad_di = 0}, + {.ch_sel = FUNC_JTAG_TMS, + .ds = 0x0, + .oe_en = 0, + .oe_inv = 0, + .do_sel = 0, + .do_inv = 0, + .pu = 0, + .pd = 0, + .resv1 = 0, + .sl = 0, + .ie_en = 1, + .ie_inv = 0, + .di_inv = 0, + .st = 1, + .tie_en = 0, + .tie_val = 0, + .resv0 = 0, + .pad_di = 0}, + {.ch_sel = FUNC_JTAG_TDO, + .ds = 0xf, + .oe_en = 1, + .oe_inv = 0, + .do_sel = 0, + .do_inv = 0, + .pu = 0, + .pd = 0, + .resv1 = 0, + .sl = 0, + .ie_en = 0, + .ie_inv = 0, + .di_inv = 0, + .st = 0, + .tie_en = 0, + .tie_val = 0, + .resv0 = 0, + .pad_di = 0}, + {.ch_sel = FUNC_SPI0_D0, + .ds = 0xf, + .oe_en = 1, + .oe_inv = 1, + .do_sel = 0, + .do_inv = 0, + .pu = 0, + .pd = 0, + .resv1 = 0, + .sl = 0, + .ie_en = 1, + .ie_inv = 1, + .di_inv = 0, + .st = 1, + .tie_en = 0, + .tie_val = 0, + .resv0 = 0, + .pad_di = 0}, + {.ch_sel = FUNC_SPI0_D1, + .ds = 0xf, + .oe_en = 1, + .oe_inv = 1, + .do_sel = 0, + .do_inv = 0, + .pu = 0, + .pd = 0, + .resv1 = 0, + .sl = 0, + .ie_en = 1, + .ie_inv = 1, + .di_inv = 0, + .st = 1, + .tie_en = 0, + .tie_val = 0, + .resv0 = 0, + .pad_di = 0}, + {.ch_sel = FUNC_SPI0_D2, + .ds = 0xf, + .oe_en = 1, + .oe_inv = 1, + .do_sel = 0, + .do_inv = 0, + .pu = 0, + .pd = 0, + .resv1 = 0, + .sl = 0, + .ie_en = 1, + .ie_inv = 1, + .di_inv = 0, + .st = 1, + .tie_en = 0, + .tie_val = 0, + .resv0 = 0, + .pad_di = 0}, + {.ch_sel = FUNC_SPI0_D3, + .ds = 0xf, + .oe_en = 1, + .oe_inv = 1, + .do_sel = 0, + .do_inv = 0, + .pu = 0, + .pd = 0, + .resv1 = 0, + .sl = 0, + .ie_en = 1, + .ie_inv = 1, + .di_inv = 0, + .st = 1, + .tie_en = 0, + .tie_val = 0, + .resv0 = 0, + .pad_di = 0}, + {.ch_sel = FUNC_SPI0_D4, + .ds = 0xf, + .oe_en = 1, + .oe_inv = 1, + .do_sel = 0, + .do_inv = 0, + .pu = 0, + .pd = 0, + .resv1 = 0, + .sl = 0, + .ie_en = 1, + .ie_inv = 1, + .di_inv = 0, + .st = 1, + .tie_en = 0, + .tie_val = 0, + .resv0 = 0, + .pad_di = 0}, + {.ch_sel = FUNC_SPI0_D5, + .ds = 0xf, + .oe_en = 1, + .oe_inv = 1, + .do_sel = 0, + .do_inv = 0, + .pu = 0, + .pd = 0, + .resv1 = 0, + .sl = 0, + .ie_en = 1, + .ie_inv = 1, + .di_inv = 0, + .st = 1, + .tie_en = 0, + .tie_val = 0, + .resv0 = 0, + .pad_di = 0}, + {.ch_sel = FUNC_SPI0_D6, + .ds = 0xf, + .oe_en = 1, + .oe_inv = 1, + .do_sel = 0, + .do_inv = 0, + .pu = 0, + .pd = 0, + .resv1 = 0, + .sl = 0, + .ie_en = 1, + .ie_inv = 1, + .di_inv = 0, + .st = 1, + .tie_en = 0, + .tie_val = 0, + .resv0 = 0, + .pad_di = 0}, + {.ch_sel = FUNC_SPI0_D7, + .ds = 0xf, + .oe_en = 1, + .oe_inv = 1, + .do_sel = 0, + .do_inv = 0, + .pu = 0, + .pd = 0, + .resv1 = 0, + .sl = 0, + .ie_en = 1, + .ie_inv = 1, + .di_inv = 0, + .st = 1, + .tie_en = 0, + .tie_val = 0, + .resv0 = 0, + .pad_di = 0}, + {.ch_sel = FUNC_SPI0_SS0, + .ds = 0xf, + .oe_en = 1, + .oe_inv = 0, + .do_sel = 0, + .do_inv = 0, + .pu = 0, + .pd = 0, + .resv1 = 0, + .sl = 0, + .ie_en = 0, + .ie_inv = 0, + .di_inv = 0, + .st = 0, + .tie_en = 0, + .tie_val = 0, + .resv0 = 0, + .pad_di = 0}, + {.ch_sel = FUNC_SPI0_SS1, + .ds = 0xf, + .oe_en = 1, + .oe_inv = 0, + .do_sel = 0, + .do_inv = 0, + .pu = 0, + .pd = 0, + .resv1 = 0, + .sl = 0, + .ie_en = 0, + .ie_inv = 0, + .di_inv = 0, + .st = 0, + .tie_en = 0, + .tie_val = 0, + .resv0 = 0, + .pad_di = 0}, + {.ch_sel = FUNC_SPI0_SS2, + .ds = 0xf, + .oe_en = 1, + .oe_inv = 0, + .do_sel = 0, + .do_inv = 0, + .pu = 0, + .pd = 0, + .resv1 = 0, + .sl = 0, + .ie_en = 0, + .ie_inv = 0, + .di_inv = 0, + .st = 0, + .tie_en = 0, + .tie_val = 0, + .resv0 = 0, + .pad_di = 0}, + {.ch_sel = FUNC_SPI0_SS3, + .ds = 0xf, + .oe_en = 1, + .oe_inv = 0, + .do_sel = 0, + .do_inv = 0, + .pu = 0, + .pd = 0, + .resv1 = 0, + .sl = 0, + .ie_en = 0, + .ie_inv = 0, + .di_inv = 0, + .st = 0, + .tie_en = 0, + .tie_val = 0, + .resv0 = 0, + .pad_di = 0}, + {.ch_sel = FUNC_SPI0_ARB, + .ds = 0x0, + .oe_en = 0, + .oe_inv = 0, + .do_sel = 0, + .do_inv = 0, + .pu = 0, + .pd = 0, + .resv1 = 0, + .sl = 0, + .ie_en = 1, + .ie_inv = 0, + .di_inv = 0, + .st = 1, + .tie_en = 1, + .tie_val = 1, + .resv0 = 0, + .pad_di = 0}, + {.ch_sel = FUNC_SPI0_SCLK, + .ds = 0xf, + .oe_en = 1, + .oe_inv = 0, + .do_sel = 0, + .do_inv = 0, + .pu = 0, + .pd = 0, + .resv1 = 0, + .sl = 0, + .ie_en = 0, + .ie_inv = 0, + .di_inv = 0, + .st = 0, + .tie_en = 0, + .tie_val = 0, + .resv0 = 0, + .pad_di = 0}, + {.ch_sel = FUNC_UARTHS_RX, + .ds = 0x0, + .oe_en = 0, + .oe_inv = 0, + .do_sel = 0, + .do_inv = 0, + .pu = 0, + .pd = 0, + .resv1 = 0, + .sl = 0, + .ie_en = 1, + .ie_inv = 0, + .di_inv = 0, + .st = 1, + .tie_en = 0, + .tie_val = 0, + .resv0 = 0, + .pad_di = 0}, + {.ch_sel = FUNC_UARTHS_TX, + .ds = 0xf, + .oe_en = 1, + .oe_inv = 0, + .do_sel = 0, + .do_inv = 0, + .pu = 0, + .pd = 0, + .resv1 = 0, + .sl = 0, + .ie_en = 0, + .ie_inv = 0, + .di_inv = 0, + .st = 0, + .tie_en = 0, + .tie_val = 0, + .resv0 = 0, + .pad_di = 0}, + {.ch_sel = FUNC_RESV6, + .ds = 0x0, + .oe_en = 0, + .oe_inv = 0, + .do_sel = 0, + .do_inv = 0, + .pu = 0, + .pd = 0, + .resv1 = 0, + .sl = 0, + .ie_en = 1, + .ie_inv = 0, + .di_inv = 0, + .st = 1, + .tie_en = 0, + .tie_val = 0, + .resv0 = 0, + .pad_di = 0}, + {.ch_sel = FUNC_RESV7, + .ds = 0x0, + .oe_en = 0, + .oe_inv = 0, + .do_sel = 0, + .do_inv = 0, + .pu = 0, + .pd = 0, + .resv1 = 0, + .sl = 0, + .ie_en = 1, + .ie_inv = 0, + .di_inv = 0, + .st = 1, + .tie_en = 0, + .tie_val = 0, + .resv0 = 0, + .pad_di = 0}, + {.ch_sel = FUNC_CLK_SPI1, + .ds = 0xf, + .oe_en = 1, + .oe_inv = 0, + .do_sel = 0, + .do_inv = 0, + .pu = 0, + .pd = 0, + .resv1 = 0, + .sl = 0, + .ie_en = 0, + .ie_inv = 0, + .di_inv = 0, + .st = 0, + .tie_en = 0, + .tie_val = 0, + .resv0 = 0, + .pad_di = 0}, + {.ch_sel = FUNC_CLK_I2C1, + .ds = 0xf, + .oe_en = 1, + .oe_inv = 0, + .do_sel = 0, + .do_inv = 0, + .pu = 0, + .pd = 0, + .resv1 = 0, + .sl = 0, + .ie_en = 0, + .ie_inv = 0, + .di_inv = 0, + .st = 0, + .tie_en = 0, + .tie_val = 0, + .resv0 = 0, + .pad_di = 0}, + {.ch_sel = FUNC_GPIOHS0, + .ds = 0xf, + .oe_en = 1, + .oe_inv = 0, + .do_sel = 0, + .do_inv = 0, + .pu = 0, + .pd = 0, + .resv1 = 0, + .sl = 0, + .ie_en = 1, + .ie_inv = 0, + .di_inv = 0, + .st = 1, + .tie_en = 0, + .tie_val = 0, + .resv0 = 0, + .pad_di = 0}, + {.ch_sel = FUNC_GPIOHS1, + .ds = 0xf, + .oe_en = 1, + .oe_inv = 0, + .do_sel = 0, + .do_inv = 0, + .pu = 0, + .pd = 0, + .resv1 = 0, + .sl = 0, + .ie_en = 1, + .ie_inv = 0, + .di_inv = 0, + .st = 1, + .tie_en = 0, + .tie_val = 0, + .resv0 = 0, + .pad_di = 0}, + {.ch_sel = FUNC_GPIOHS2, + .ds = 0xf, + .oe_en = 1, + .oe_inv = 0, + .do_sel = 0, + .do_inv = 0, + .pu = 0, + .pd = 0, + .resv1 = 0, + .sl = 0, + .ie_en = 1, + .ie_inv = 0, + .di_inv = 0, + .st = 1, + .tie_en = 0, + .tie_val = 0, + .resv0 = 0, + .pad_di = 0}, + {.ch_sel = FUNC_GPIOHS3, + .ds = 0xf, + .oe_en = 1, + .oe_inv = 0, + .do_sel = 0, + .do_inv = 0, + .pu = 0, + .pd = 0, + .resv1 = 0, + .sl = 0, + .ie_en = 1, + .ie_inv = 0, + .di_inv = 0, + .st = 1, + .tie_en = 0, + .tie_val = 0, + .resv0 = 0, + .pad_di = 0}, + {.ch_sel = FUNC_GPIOHS4, + .ds = 0xf, + .oe_en = 1, + .oe_inv = 0, + .do_sel = 0, + .do_inv = 0, + .pu = 0, + .pd = 0, + .resv1 = 0, + .sl = 0, + .ie_en = 1, + .ie_inv = 0, + .di_inv = 0, + .st = 1, + .tie_en = 0, + .tie_val = 0, + .resv0 = 0, + .pad_di = 0}, + {.ch_sel = FUNC_GPIOHS5, + .ds = 0xf, + .oe_en = 1, + .oe_inv = 0, + .do_sel = 0, + .do_inv = 0, + .pu = 0, + .pd = 0, + .resv1 = 0, + .sl = 0, + .ie_en = 1, + .ie_inv = 0, + .di_inv = 0, + .st = 1, + .tie_en = 0, + .tie_val = 0, + .resv0 = 0, + .pad_di = 0}, + {.ch_sel = FUNC_GPIOHS6, + .ds = 0xf, + .oe_en = 1, + .oe_inv = 0, + .do_sel = 0, + .do_inv = 0, + .pu = 0, + .pd = 0, + .resv1 = 0, + .sl = 0, + .ie_en = 1, + .ie_inv = 0, + .di_inv = 0, + .st = 1, + .tie_en = 0, + .tie_val = 0, + .resv0 = 0, + .pad_di = 0}, + {.ch_sel = FUNC_GPIOHS7, + .ds = 0xf, + .oe_en = 1, + .oe_inv = 0, + .do_sel = 0, + .do_inv = 0, + .pu = 0, + .pd = 0, + .resv1 = 0, + .sl = 0, + .ie_en = 1, + .ie_inv = 0, + .di_inv = 0, + .st = 1, + .tie_en = 0, + .tie_val = 0, + .resv0 = 0, + .pad_di = 0}, + {.ch_sel = FUNC_GPIOHS8, + .ds = 0xf, + .oe_en = 1, + .oe_inv = 0, + .do_sel = 0, + .do_inv = 0, + .pu = 0, + .pd = 0, + .resv1 = 0, + .sl = 0, + .ie_en = 1, + .ie_inv = 0, + .di_inv = 0, + .st = 1, + .tie_en = 0, + .tie_val = 0, + .resv0 = 0, + .pad_di = 0}, + {.ch_sel = FUNC_GPIOHS9, + .ds = 0xf, + .oe_en = 1, + .oe_inv = 0, + .do_sel = 0, + .do_inv = 0, + .pu = 0, + .pd = 0, + .resv1 = 0, + .sl = 0, + .ie_en = 1, + .ie_inv = 0, + .di_inv = 0, + .st = 1, + .tie_en = 0, + .tie_val = 0, + .resv0 = 0, + .pad_di = 0}, + {.ch_sel = FUNC_GPIOHS10, + .ds = 0xf, + .oe_en = 1, + .oe_inv = 0, + .do_sel = 0, + .do_inv = 0, + .pu = 0, + .pd = 0, + .resv1 = 0, + .sl = 0, + .ie_en = 1, + .ie_inv = 0, + .di_inv = 0, + .st = 1, + .tie_en = 0, + .tie_val = 0, + .resv0 = 0, + .pad_di = 0}, + {.ch_sel = FUNC_GPIOHS11, + .ds = 0xf, + .oe_en = 1, + .oe_inv = 0, + .do_sel = 0, + .do_inv = 0, + .pu = 0, + .pd = 0, + .resv1 = 0, + .sl = 0, + .ie_en = 1, + .ie_inv = 0, + .di_inv = 0, + .st = 1, + .tie_en = 0, + .tie_val = 0, + .resv0 = 0, + .pad_di = 0}, + {.ch_sel = FUNC_GPIOHS12, + .ds = 0xf, + .oe_en = 1, + .oe_inv = 0, + .do_sel = 0, + .do_inv = 0, + .pu = 0, + .pd = 0, + .resv1 = 0, + .sl = 0, + .ie_en = 1, + .ie_inv = 0, + .di_inv = 0, + .st = 1, + .tie_en = 0, + .tie_val = 0, + .resv0 = 0, + .pad_di = 0}, + {.ch_sel = FUNC_GPIOHS13, + .ds = 0xf, + .oe_en = 1, + .oe_inv = 0, + .do_sel = 0, + .do_inv = 0, + .pu = 0, + .pd = 0, + .resv1 = 0, + .sl = 0, + .ie_en = 1, + .ie_inv = 0, + .di_inv = 0, + .st = 1, + .tie_en = 0, + .tie_val = 0, + .resv0 = 0, + .pad_di = 0}, + {.ch_sel = FUNC_GPIOHS14, + .ds = 0xf, + .oe_en = 1, + .oe_inv = 0, + .do_sel = 0, + .do_inv = 0, + .pu = 0, + .pd = 0, + .resv1 = 0, + .sl = 0, + .ie_en = 1, + .ie_inv = 0, + .di_inv = 0, + .st = 1, + .tie_en = 0, + .tie_val = 0, + .resv0 = 0, + .pad_di = 0}, + {.ch_sel = FUNC_GPIOHS15, + .ds = 0xf, + .oe_en = 1, + .oe_inv = 0, + .do_sel = 0, + .do_inv = 0, + .pu = 0, + .pd = 0, + .resv1 = 0, + .sl = 0, + .ie_en = 1, + .ie_inv = 0, + .di_inv = 0, + .st = 1, + .tie_en = 0, + .tie_val = 0, + .resv0 = 0, + .pad_di = 0}, + {.ch_sel = FUNC_GPIOHS16, + .ds = 0xf, + .oe_en = 1, + .oe_inv = 0, + .do_sel = 0, + .do_inv = 0, + .pu = 0, + .pd = 0, + .resv1 = 0, + .sl = 0, + .ie_en = 1, + .ie_inv = 0, + .di_inv = 0, + .st = 1, + .tie_en = 0, + .tie_val = 0, + .resv0 = 0, + .pad_di = 0}, + {.ch_sel = FUNC_GPIOHS17, + .ds = 0xf, + .oe_en = 1, + .oe_inv = 0, + .do_sel = 0, + .do_inv = 0, + .pu = 0, + .pd = 0, + .resv1 = 0, + .sl = 0, + .ie_en = 1, + .ie_inv = 0, + .di_inv = 0, + .st = 1, + .tie_en = 0, + .tie_val = 0, + .resv0 = 0, + .pad_di = 0}, + {.ch_sel = FUNC_GPIOHS18, + .ds = 0xf, + .oe_en = 1, + .oe_inv = 0, + .do_sel = 0, + .do_inv = 0, + .pu = 0, + .pd = 0, + .resv1 = 0, + .sl = 0, + .ie_en = 1, + .ie_inv = 0, + .di_inv = 0, + .st = 1, + .tie_en = 0, + .tie_val = 0, + .resv0 = 0, + .pad_di = 0}, + {.ch_sel = FUNC_GPIOHS19, + .ds = 0xf, + .oe_en = 1, + .oe_inv = 0, + .do_sel = 0, + .do_inv = 0, + .pu = 0, + .pd = 0, + .resv1 = 0, + .sl = 0, + .ie_en = 1, + .ie_inv = 0, + .di_inv = 0, + .st = 1, + .tie_en = 0, + .tie_val = 0, + .resv0 = 0, + .pad_di = 0}, + {.ch_sel = FUNC_GPIOHS20, + .ds = 0xf, + .oe_en = 1, + .oe_inv = 0, + .do_sel = 0, + .do_inv = 0, + .pu = 0, + .pd = 0, + .resv1 = 0, + .sl = 0, + .ie_en = 1, + .ie_inv = 0, + .di_inv = 0, + .st = 1, + .tie_en = 0, + .tie_val = 0, + .resv0 = 0, + .pad_di = 0}, + {.ch_sel = FUNC_GPIOHS21, + .ds = 0xf, + .oe_en = 1, + .oe_inv = 0, + .do_sel = 0, + .do_inv = 0, + .pu = 0, + .pd = 0, + .resv1 = 0, + .sl = 0, + .ie_en = 1, + .ie_inv = 0, + .di_inv = 0, + .st = 1, + .tie_en = 0, + .tie_val = 0, + .resv0 = 0, + .pad_di = 0}, + {.ch_sel = FUNC_GPIOHS22, + .ds = 0xf, + .oe_en = 1, + .oe_inv = 0, + .do_sel = 0, + .do_inv = 0, + .pu = 0, + .pd = 0, + .resv1 = 0, + .sl = 0, + .ie_en = 1, + .ie_inv = 0, + .di_inv = 0, + .st = 1, + .tie_en = 0, + .tie_val = 0, + .resv0 = 0, + .pad_di = 0}, + {.ch_sel = FUNC_GPIOHS23, + .ds = 0xf, + .oe_en = 1, + .oe_inv = 0, + .do_sel = 0, + .do_inv = 0, + .pu = 0, + .pd = 0, + .resv1 = 0, + .sl = 0, + .ie_en = 1, + .ie_inv = 0, + .di_inv = 0, + .st = 1, + .tie_en = 0, + .tie_val = 0, + .resv0 = 0, + .pad_di = 0}, + {.ch_sel = FUNC_GPIOHS24, + .ds = 0xf, + .oe_en = 1, + .oe_inv = 0, + .do_sel = 0, + .do_inv = 0, + .pu = 0, + .pd = 0, + .resv1 = 0, + .sl = 0, + .ie_en = 1, + .ie_inv = 0, + .di_inv = 0, + .st = 1, + .tie_en = 0, + .tie_val = 0, + .resv0 = 0, + .pad_di = 0}, + {.ch_sel = FUNC_GPIOHS25, + .ds = 0xf, + .oe_en = 1, + .oe_inv = 0, + .do_sel = 0, + .do_inv = 0, + .pu = 0, + .pd = 0, + .resv1 = 0, + .sl = 0, + .ie_en = 1, + .ie_inv = 0, + .di_inv = 0, + .st = 1, + .tie_en = 0, + .tie_val = 0, + .resv0 = 0, + .pad_di = 0}, + {.ch_sel = FUNC_GPIOHS26, + .ds = 0xf, + .oe_en = 1, + .oe_inv = 0, + .do_sel = 0, + .do_inv = 0, + .pu = 0, + .pd = 0, + .resv1 = 0, + .sl = 0, + .ie_en = 1, + .ie_inv = 0, + .di_inv = 0, + .st = 1, + .tie_en = 0, + .tie_val = 0, + .resv0 = 0, + .pad_di = 0}, + {.ch_sel = FUNC_GPIOHS27, + .ds = 0xf, + .oe_en = 1, + .oe_inv = 0, + .do_sel = 0, + .do_inv = 0, + .pu = 0, + .pd = 0, + .resv1 = 0, + .sl = 0, + .ie_en = 1, + .ie_inv = 0, + .di_inv = 0, + .st = 1, + .tie_en = 0, + .tie_val = 0, + .resv0 = 0, + .pad_di = 0}, + {.ch_sel = FUNC_GPIOHS28, + .ds = 0xf, + .oe_en = 1, + .oe_inv = 0, + .do_sel = 0, + .do_inv = 0, + .pu = 0, + .pd = 0, + .resv1 = 0, + .sl = 0, + .ie_en = 1, + .ie_inv = 0, + .di_inv = 0, + .st = 1, + .tie_en = 0, + .tie_val = 0, + .resv0 = 0, + .pad_di = 0}, + {.ch_sel = FUNC_GPIOHS29, + .ds = 0xf, + .oe_en = 1, + .oe_inv = 0, + .do_sel = 0, + .do_inv = 0, + .pu = 0, + .pd = 0, + .resv1 = 0, + .sl = 0, + .ie_en = 1, + .ie_inv = 0, + .di_inv = 0, + .st = 1, + .tie_en = 0, + .tie_val = 0, + .resv0 = 0, + .pad_di = 0}, + {.ch_sel = FUNC_GPIOHS30, + .ds = 0xf, + .oe_en = 1, + .oe_inv = 0, + .do_sel = 0, + .do_inv = 0, + .pu = 0, + .pd = 0, + .resv1 = 0, + .sl = 0, + .ie_en = 1, + .ie_inv = 0, + .di_inv = 0, + .st = 1, + .tie_en = 0, + .tie_val = 0, + .resv0 = 0, + .pad_di = 0}, + {.ch_sel = FUNC_GPIOHS31, + .ds = 0xf, + .oe_en = 1, + .oe_inv = 0, + .do_sel = 0, + .do_inv = 0, + .pu = 0, + .pd = 0, + .resv1 = 0, + .sl = 0, + .ie_en = 1, + .ie_inv = 0, + .di_inv = 0, + .st = 1, + .tie_en = 0, + .tie_val = 0, + .resv0 = 0, + .pad_di = 0}, + {.ch_sel = FUNC_GPIO0, + .ds = 0xf, + .oe_en = 1, + .oe_inv = 0, + .do_sel = 0, + .do_inv = 0, + .pu = 0, + .pd = 0, + .resv1 = 0, + .sl = 0, + .ie_en = 1, + .ie_inv = 0, + .di_inv = 0, + .st = 1, + .tie_en = 0, + .tie_val = 0, + .resv0 = 0, + .pad_di = 0}, + {.ch_sel = FUNC_GPIO1, + .ds = 0xf, + .oe_en = 1, + .oe_inv = 0, + .do_sel = 0, + .do_inv = 0, + .pu = 0, + .pd = 0, + .resv1 = 0, + .sl = 0, + .ie_en = 1, + .ie_inv = 0, + .di_inv = 0, + .st = 1, + .tie_en = 0, + .tie_val = 0, + .resv0 = 0, + .pad_di = 0}, + {.ch_sel = FUNC_GPIO2, + .ds = 0xf, + .oe_en = 1, + .oe_inv = 0, + .do_sel = 0, + .do_inv = 0, + .pu = 0, + .pd = 0, + .resv1 = 0, + .sl = 0, + .ie_en = 1, + .ie_inv = 0, + .di_inv = 0, + .st = 1, + .tie_en = 0, + .tie_val = 0, + .resv0 = 0, + .pad_di = 0}, + {.ch_sel = FUNC_GPIO3, + .ds = 0xf, + .oe_en = 1, + .oe_inv = 0, + .do_sel = 0, + .do_inv = 0, + .pu = 0, + .pd = 0, + .resv1 = 0, + .sl = 0, + .ie_en = 1, + .ie_inv = 0, + .di_inv = 0, + .st = 1, + .tie_en = 0, + .tie_val = 0, + .resv0 = 0, + .pad_di = 0}, + {.ch_sel = FUNC_GPIO4, + .ds = 0xf, + .oe_en = 1, + .oe_inv = 0, + .do_sel = 0, + .do_inv = 0, + .pu = 0, + .pd = 0, + .resv1 = 0, + .sl = 0, + .ie_en = 1, + .ie_inv = 0, + .di_inv = 0, + .st = 1, + .tie_en = 0, + .tie_val = 0, + .resv0 = 0, + .pad_di = 0}, + {.ch_sel = FUNC_GPIO5, + .ds = 0xf, + .oe_en = 1, + .oe_inv = 0, + .do_sel = 0, + .do_inv = 0, + .pu = 0, + .pd = 0, + .resv1 = 0, + .sl = 0, + .ie_en = 1, + .ie_inv = 0, + .di_inv = 0, + .st = 1, + .tie_en = 0, + .tie_val = 0, + .resv0 = 0, + .pad_di = 0}, + {.ch_sel = FUNC_GPIO6, + .ds = 0xf, + .oe_en = 1, + .oe_inv = 0, + .do_sel = 0, + .do_inv = 0, + .pu = 0, + .pd = 0, + .resv1 = 0, + .sl = 0, + .ie_en = 1, + .ie_inv = 0, + .di_inv = 0, + .st = 1, + .tie_en = 0, + .tie_val = 0, + .resv0 = 0, + .pad_di = 0}, + {.ch_sel = FUNC_GPIO7, + .ds = 0xf, + .oe_en = 1, + .oe_inv = 0, + .do_sel = 0, + .do_inv = 0, + .pu = 0, + .pd = 0, + .resv1 = 0, + .sl = 0, + .ie_en = 1, + .ie_inv = 0, + .di_inv = 0, + .st = 1, + .tie_en = 0, + .tie_val = 0, + .resv0 = 0, + .pad_di = 0}, + {.ch_sel = FUNC_UART1_RX, + .ds = 0x0, + .oe_en = 0, + .oe_inv = 0, + .do_sel = 0, + .do_inv = 0, + .pu = 0, + .pd = 0, + .resv1 = 0, + .sl = 0, + .ie_en = 1, + .ie_inv = 0, + .di_inv = 0, + .st = 1, + .tie_en = 0, + .tie_val = 0, + .resv0 = 0, + .pad_di = 0}, + {.ch_sel = FUNC_UART1_TX, + .ds = 0xf, + .oe_en = 1, + .oe_inv = 0, + .do_sel = 0, + .do_inv = 0, + .pu = 0, + .pd = 0, + .resv1 = 0, + .sl = 0, + .ie_en = 0, + .ie_inv = 0, + .di_inv = 0, + .st = 0, + .tie_en = 0, + .tie_val = 0, + .resv0 = 0, + .pad_di = 0}, + {.ch_sel = FUNC_UART2_RX, + .ds = 0x0, + .oe_en = 0, + .oe_inv = 0, + .do_sel = 0, + .do_inv = 0, + .pu = 0, + .pd = 0, + .resv1 = 0, + .sl = 0, + .ie_en = 1, + .ie_inv = 0, + .di_inv = 0, + .st = 1, + .tie_en = 0, + .tie_val = 0, + .resv0 = 0, + .pad_di = 0}, + {.ch_sel = FUNC_UART2_TX, + .ds = 0xf, + .oe_en = 1, + .oe_inv = 0, + .do_sel = 0, + .do_inv = 0, + .pu = 0, + .pd = 0, + .resv1 = 0, + .sl = 0, + .ie_en = 0, + .ie_inv = 0, + .di_inv = 0, + .st = 0, + .tie_en = 0, + .tie_val = 0, + .resv0 = 0, + .pad_di = 0}, + {.ch_sel = FUNC_UART3_RX, + .ds = 0x0, + .oe_en = 0, + .oe_inv = 0, + .do_sel = 0, + .do_inv = 0, + .pu = 0, + .pd = 0, + .resv1 = 0, + .sl = 0, + .ie_en = 1, + .ie_inv = 0, + .di_inv = 0, + .st = 1, + .tie_en = 0, + .tie_val = 0, + .resv0 = 0, + .pad_di = 0}, + {.ch_sel = FUNC_UART3_TX, + .ds = 0xf, + .oe_en = 1, + .oe_inv = 0, + .do_sel = 0, + .do_inv = 0, + .pu = 0, + .pd = 0, + .resv1 = 0, + .sl = 0, + .ie_en = 0, + .ie_inv = 0, + .di_inv = 0, + .st = 0, + .tie_en = 0, + .tie_val = 0, + .resv0 = 0, + .pad_di = 0}, + {.ch_sel = FUNC_SPI1_D0, + .ds = 0xf, + .oe_en = 1, + .oe_inv = 1, + .do_sel = 0, + .do_inv = 0, + .pu = 0, + .pd = 0, + .resv1 = 0, + .sl = 0, + .ie_en = 1, + .ie_inv = 1, + .di_inv = 0, + .st = 1, + .tie_en = 0, + .tie_val = 0, + .resv0 = 0, + .pad_di = 0}, + {.ch_sel = FUNC_SPI1_D1, + .ds = 0xf, + .oe_en = 1, + .oe_inv = 1, + .do_sel = 0, + .do_inv = 0, + .pu = 0, + .pd = 0, + .resv1 = 0, + .sl = 0, + .ie_en = 1, + .ie_inv = 1, + .di_inv = 0, + .st = 1, + .tie_en = 0, + .tie_val = 0, + .resv0 = 0, + .pad_di = 0}, + {.ch_sel = FUNC_SPI1_D2, + .ds = 0xf, + .oe_en = 1, + .oe_inv = 1, + .do_sel = 0, + .do_inv = 0, + .pu = 0, + .pd = 0, + .resv1 = 0, + .sl = 0, + .ie_en = 1, + .ie_inv = 1, + .di_inv = 0, + .st = 1, + .tie_en = 0, + .tie_val = 0, + .resv0 = 0, + .pad_di = 0}, + {.ch_sel = FUNC_SPI1_D3, + .ds = 0xf, + .oe_en = 1, + .oe_inv = 1, + .do_sel = 0, + .do_inv = 0, + .pu = 0, + .pd = 0, + .resv1 = 0, + .sl = 0, + .ie_en = 1, + .ie_inv = 1, + .di_inv = 0, + .st = 1, + .tie_en = 0, + .tie_val = 0, + .resv0 = 0, + .pad_di = 0}, + {.ch_sel = FUNC_SPI1_D4, + .ds = 0xf, + .oe_en = 1, + .oe_inv = 1, + .do_sel = 0, + .do_inv = 0, + .pu = 0, + .pd = 0, + .resv1 = 0, + .sl = 0, + .ie_en = 1, + .ie_inv = 1, + .di_inv = 0, + .st = 1, + .tie_en = 0, + .tie_val = 0, + .resv0 = 0, + .pad_di = 0}, + {.ch_sel = FUNC_SPI1_D5, + .ds = 0xf, + .oe_en = 1, + .oe_inv = 1, + .do_sel = 0, + .do_inv = 0, + .pu = 0, + .pd = 0, + .resv1 = 0, + .sl = 0, + .ie_en = 1, + .ie_inv = 1, + .di_inv = 0, + .st = 1, + .tie_en = 0, + .tie_val = 0, + .resv0 = 0, + .pad_di = 0}, + {.ch_sel = FUNC_SPI1_D6, + .ds = 0xf, + .oe_en = 1, + .oe_inv = 1, + .do_sel = 0, + .do_inv = 0, + .pu = 0, + .pd = 0, + .resv1 = 0, + .sl = 0, + .ie_en = 1, + .ie_inv = 1, + .di_inv = 0, + .st = 1, + .tie_en = 0, + .tie_val = 0, + .resv0 = 0, + .pad_di = 0}, + {.ch_sel = FUNC_SPI1_D7, + .ds = 0xf, + .oe_en = 1, + .oe_inv = 1, + .do_sel = 0, + .do_inv = 0, + .pu = 0, + .pd = 0, + .resv1 = 0, + .sl = 0, + .ie_en = 1, + .ie_inv = 1, + .di_inv = 0, + .st = 1, + .tie_en = 0, + .tie_val = 0, + .resv0 = 0, + .pad_di = 0}, + {.ch_sel = FUNC_SPI1_SS0, + .ds = 0xf, + .oe_en = 1, + .oe_inv = 0, + .do_sel = 0, + .do_inv = 0, + .pu = 0, + .pd = 0, + .resv1 = 0, + .sl = 0, + .ie_en = 0, + .ie_inv = 0, + .di_inv = 0, + .st = 0, + .tie_en = 0, + .tie_val = 0, + .resv0 = 0, + .pad_di = 0}, + {.ch_sel = FUNC_SPI1_SS1, + .ds = 0xf, + .oe_en = 1, + .oe_inv = 0, + .do_sel = 0, + .do_inv = 0, + .pu = 0, + .pd = 0, + .resv1 = 0, + .sl = 0, + .ie_en = 0, + .ie_inv = 0, + .di_inv = 0, + .st = 0, + .tie_en = 0, + .tie_val = 0, + .resv0 = 0, + .pad_di = 0}, + {.ch_sel = FUNC_SPI1_SS2, + .ds = 0xf, + .oe_en = 1, + .oe_inv = 0, + .do_sel = 0, + .do_inv = 0, + .pu = 0, + .pd = 0, + .resv1 = 0, + .sl = 0, + .ie_en = 0, + .ie_inv = 0, + .di_inv = 0, + .st = 0, + .tie_en = 0, + .tie_val = 0, + .resv0 = 0, + .pad_di = 0}, + {.ch_sel = FUNC_SPI1_SS3, + .ds = 0xf, + .oe_en = 1, + .oe_inv = 0, + .do_sel = 0, + .do_inv = 0, + .pu = 0, + .pd = 0, + .resv1 = 0, + .sl = 0, + .ie_en = 0, + .ie_inv = 0, + .di_inv = 0, + .st = 0, + .tie_en = 0, + .tie_val = 0, + .resv0 = 0, + .pad_di = 0}, + {.ch_sel = FUNC_SPI1_ARB, + .ds = 0x0, + .oe_en = 0, + .oe_inv = 0, + .do_sel = 0, + .do_inv = 0, + .pu = 0, + .pd = 0, + .resv1 = 0, + .sl = 0, + .ie_en = 1, + .ie_inv = 0, + .di_inv = 0, + .st = 1, + .tie_en = 1, + .tie_val = 1, + .resv0 = 0, + .pad_di = 0}, + {.ch_sel = FUNC_SPI1_SCLK, + .ds = 0xf, + .oe_en = 1, + .oe_inv = 0, + .do_sel = 0, + .do_inv = 0, + .pu = 0, + .pd = 0, + .resv1 = 0, + .sl = 0, + .ie_en = 0, + .ie_inv = 0, + .di_inv = 0, + .st = 0, + .tie_en = 0, + .tie_val = 0, + .resv0 = 0, + .pad_di = 0}, + {.ch_sel = FUNC_SPI_SLAVE_D0, + .ds = 0xf, + .oe_en = 1, + .oe_inv = 1, + .do_sel = 0, + .do_inv = 0, + .pu = 0, + .pd = 0, + .resv1 = 0, + .sl = 0, + .ie_en = 1, + .ie_inv = 1, + .di_inv = 0, + .st = 1, + .tie_en = 0, + .tie_val = 0, + .resv0 = 0, + .pad_di = 0}, + {.ch_sel = FUNC_SPI_SLAVE_SS, + .ds = 0x0, + .oe_en = 0, + .oe_inv = 0, + .do_sel = 0, + .do_inv = 0, + .pu = 0, + .pd = 0, + .resv1 = 0, + .sl = 0, + .ie_en = 1, + .ie_inv = 0, + .di_inv = 0, + .st = 1, + .tie_en = 0, + .tie_val = 0, + .resv0 = 0, + .pad_di = 0}, + {.ch_sel = FUNC_SPI_SLAVE_SCLK, + .ds = 0x0, + .oe_en = 0, + .oe_inv = 0, + .do_sel = 0, + .do_inv = 0, + .pu = 0, + .pd = 0, + .resv1 = 0, + .sl = 0, + .ie_en = 1, + .ie_inv = 0, + .di_inv = 0, + .st = 1, + .tie_en = 0, + .tie_val = 0, + .resv0 = 0, + .pad_di = 0}, + {.ch_sel = FUNC_I2S0_MCLK, + .ds = 0xf, + .oe_en = 1, + .oe_inv = 0, + .do_sel = 0, + .do_inv = 0, + .pu = 0, + .pd = 0, + .resv1 = 0, + .sl = 0, + .ie_en = 0, + .ie_inv = 0, + .di_inv = 0, + .st = 0, + .tie_en = 0, + .tie_val = 0, + .resv0 = 0, + .pad_di = 0}, + {.ch_sel = FUNC_I2S0_SCLK, + .ds = 0xf, + .oe_en = 1, + .oe_inv = 0, + .do_sel = 0, + .do_inv = 0, + .pu = 0, + .pd = 0, + .resv1 = 0, + .sl = 0, + .ie_en = 0, + .ie_inv = 0, + .di_inv = 0, + .st = 0, + .tie_en = 0, + .tie_val = 0, + .resv0 = 0, + .pad_di = 0}, + {.ch_sel = FUNC_I2S0_WS, + .ds = 0xf, + .oe_en = 1, + .oe_inv = 0, + .do_sel = 0, + .do_inv = 0, + .pu = 0, + .pd = 0, + .resv1 = 0, + .sl = 0, + .ie_en = 0, + .ie_inv = 0, + .di_inv = 0, + .st = 0, + .tie_en = 0, + .tie_val = 0, + .resv0 = 0, + .pad_di = 0}, + {.ch_sel = FUNC_I2S0_IN_D0, + .ds = 0x0, + .oe_en = 0, + .oe_inv = 0, + .do_sel = 0, + .do_inv = 0, + .pu = 0, + .pd = 0, + .resv1 = 0, + .sl = 0, + .ie_en = 1, + .ie_inv = 0, + .di_inv = 0, + .st = 1, + .tie_en = 0, + .tie_val = 0, + .resv0 = 0, + .pad_di = 0}, + {.ch_sel = FUNC_I2S0_IN_D1, + .ds = 0x0, + .oe_en = 0, + .oe_inv = 0, + .do_sel = 0, + .do_inv = 0, + .pu = 0, + .pd = 0, + .resv1 = 0, + .sl = 0, + .ie_en = 1, + .ie_inv = 0, + .di_inv = 0, + .st = 1, + .tie_en = 0, + .tie_val = 0, + .resv0 = 0, + .pad_di = 0}, + {.ch_sel = FUNC_I2S0_IN_D2, + .ds = 0x0, + .oe_en = 0, + .oe_inv = 0, + .do_sel = 0, + .do_inv = 0, + .pu = 0, + .pd = 0, + .resv1 = 0, + .sl = 0, + .ie_en = 1, + .ie_inv = 0, + .di_inv = 0, + .st = 1, + .tie_en = 0, + .tie_val = 0, + .resv0 = 0, + .pad_di = 0}, + {.ch_sel = FUNC_I2S0_IN_D3, + .ds = 0x0, + .oe_en = 0, + .oe_inv = 0, + .do_sel = 0, + .do_inv = 0, + .pu = 0, + .pd = 0, + .resv1 = 0, + .sl = 0, + .ie_en = 1, + .ie_inv = 0, + .di_inv = 0, + .st = 1, + .tie_en = 0, + .tie_val = 0, + .resv0 = 0, + .pad_di = 0}, + {.ch_sel = FUNC_I2S0_OUT_D0, + .ds = 0xf, + .oe_en = 1, + .oe_inv = 0, + .do_sel = 0, + .do_inv = 0, + .pu = 0, + .pd = 0, + .resv1 = 0, + .sl = 0, + .ie_en = 0, + .ie_inv = 0, + .di_inv = 0, + .st = 0, + .tie_en = 0, + .tie_val = 0, + .resv0 = 0, + .pad_di = 0}, + {.ch_sel = FUNC_I2S0_OUT_D1, + .ds = 0xf, + .oe_en = 1, + .oe_inv = 0, + .do_sel = 0, + .do_inv = 0, + .pu = 0, + .pd = 0, + .resv1 = 0, + .sl = 0, + .ie_en = 0, + .ie_inv = 0, + .di_inv = 0, + .st = 0, + .tie_en = 0, + .tie_val = 0, + .resv0 = 0, + .pad_di = 0}, + {.ch_sel = FUNC_I2S0_OUT_D2, + .ds = 0xf, + .oe_en = 1, + .oe_inv = 0, + .do_sel = 0, + .do_inv = 0, + .pu = 0, + .pd = 0, + .resv1 = 0, + .sl = 0, + .ie_en = 0, + .ie_inv = 0, + .di_inv = 0, + .st = 0, + .tie_en = 0, + .tie_val = 0, + .resv0 = 0, + .pad_di = 0}, + {.ch_sel = FUNC_I2S0_OUT_D3, + .ds = 0xf, + .oe_en = 1, + .oe_inv = 0, + .do_sel = 0, + .do_inv = 0, + .pu = 0, + .pd = 0, + .resv1 = 0, + .sl = 0, + .ie_en = 0, + .ie_inv = 0, + .di_inv = 0, + .st = 0, + .tie_en = 0, + .tie_val = 0, + .resv0 = 0, + .pad_di = 0}, + {.ch_sel = FUNC_I2S1_MCLK, + .ds = 0xf, + .oe_en = 1, + .oe_inv = 0, + .do_sel = 0, + .do_inv = 0, + .pu = 0, + .pd = 0, + .resv1 = 0, + .sl = 0, + .ie_en = 0, + .ie_inv = 0, + .di_inv = 0, + .st = 0, + .tie_en = 0, + .tie_val = 0, + .resv0 = 0, + .pad_di = 0}, + {.ch_sel = FUNC_I2S1_SCLK, + .ds = 0xf, + .oe_en = 1, + .oe_inv = 0, + .do_sel = 0, + .do_inv = 0, + .pu = 0, + .pd = 0, + .resv1 = 0, + .sl = 0, + .ie_en = 0, + .ie_inv = 0, + .di_inv = 0, + .st = 0, + .tie_en = 0, + .tie_val = 0, + .resv0 = 0, + .pad_di = 0}, + {.ch_sel = FUNC_I2S1_WS, + .ds = 0xf, + .oe_en = 1, + .oe_inv = 0, + .do_sel = 0, + .do_inv = 0, + .pu = 0, + .pd = 0, + .resv1 = 0, + .sl = 0, + .ie_en = 0, + .ie_inv = 0, + .di_inv = 0, + .st = 0, + .tie_en = 0, + .tie_val = 0, + .resv0 = 0, + .pad_di = 0}, + {.ch_sel = FUNC_I2S1_IN_D0, + .ds = 0x0, + .oe_en = 0, + .oe_inv = 0, + .do_sel = 0, + .do_inv = 0, + .pu = 0, + .pd = 0, + .resv1 = 0, + .sl = 0, + .ie_en = 1, + .ie_inv = 0, + .di_inv = 0, + .st = 1, + .tie_en = 0, + .tie_val = 0, + .resv0 = 0, + .pad_di = 0}, + {.ch_sel = FUNC_I2S1_IN_D1, + .ds = 0x0, + .oe_en = 0, + .oe_inv = 0, + .do_sel = 0, + .do_inv = 0, + .pu = 0, + .pd = 0, + .resv1 = 0, + .sl = 0, + .ie_en = 1, + .ie_inv = 0, + .di_inv = 0, + .st = 1, + .tie_en = 0, + .tie_val = 0, + .resv0 = 0, + .pad_di = 0}, + {.ch_sel = FUNC_I2S1_IN_D2, + .ds = 0x0, + .oe_en = 0, + .oe_inv = 0, + .do_sel = 0, + .do_inv = 0, + .pu = 0, + .pd = 0, + .resv1 = 0, + .sl = 0, + .ie_en = 1, + .ie_inv = 0, + .di_inv = 0, + .st = 1, + .tie_en = 0, + .tie_val = 0, + .resv0 = 0, + .pad_di = 0}, + {.ch_sel = FUNC_I2S1_IN_D3, + .ds = 0x0, + .oe_en = 0, + .oe_inv = 0, + .do_sel = 0, + .do_inv = 0, + .pu = 0, + .pd = 0, + .resv1 = 0, + .sl = 0, + .ie_en = 1, + .ie_inv = 0, + .di_inv = 0, + .st = 1, + .tie_en = 0, + .tie_val = 0, + .resv0 = 0, + .pad_di = 0}, + {.ch_sel = FUNC_I2S1_OUT_D0, + .ds = 0xf, + .oe_en = 1, + .oe_inv = 0, + .do_sel = 0, + .do_inv = 0, + .pu = 0, + .pd = 0, + .resv1 = 0, + .sl = 0, + .ie_en = 0, + .ie_inv = 0, + .di_inv = 0, + .st = 0, + .tie_en = 0, + .tie_val = 0, + .resv0 = 0, + .pad_di = 0}, + {.ch_sel = FUNC_I2S1_OUT_D1, + .ds = 0xf, + .oe_en = 1, + .oe_inv = 0, + .do_sel = 0, + .do_inv = 0, + .pu = 0, + .pd = 0, + .resv1 = 0, + .sl = 0, + .ie_en = 0, + .ie_inv = 0, + .di_inv = 0, + .st = 0, + .tie_en = 0, + .tie_val = 0, + .resv0 = 0, + .pad_di = 0}, + {.ch_sel = FUNC_I2S1_OUT_D2, + .ds = 0xf, + .oe_en = 1, + .oe_inv = 0, + .do_sel = 0, + .do_inv = 0, + .pu = 0, + .pd = 0, + .resv1 = 0, + .sl = 0, + .ie_en = 0, + .ie_inv = 0, + .di_inv = 0, + .st = 0, + .tie_en = 0, + .tie_val = 0, + .resv0 = 0, + .pad_di = 0}, + {.ch_sel = FUNC_I2S1_OUT_D3, + .ds = 0xf, + .oe_en = 1, + .oe_inv = 0, + .do_sel = 0, + .do_inv = 0, + .pu = 0, + .pd = 0, + .resv1 = 0, + .sl = 0, + .ie_en = 0, + .ie_inv = 0, + .di_inv = 0, + .st = 0, + .tie_en = 0, + .tie_val = 0, + .resv0 = 0, + .pad_di = 0}, + {.ch_sel = FUNC_I2S2_MCLK, + .ds = 0xf, + .oe_en = 1, + .oe_inv = 0, + .do_sel = 0, + .do_inv = 0, + .pu = 0, + .pd = 0, + .resv1 = 0, + .sl = 0, + .ie_en = 0, + .ie_inv = 0, + .di_inv = 0, + .st = 0, + .tie_en = 0, + .tie_val = 0, + .resv0 = 0, + .pad_di = 0}, + {.ch_sel = FUNC_I2S2_SCLK, + .ds = 0xf, + .oe_en = 1, + .oe_inv = 0, + .do_sel = 0, + .do_inv = 0, + .pu = 0, + .pd = 0, + .resv1 = 0, + .sl = 0, + .ie_en = 0, + .ie_inv = 0, + .di_inv = 0, + .st = 0, + .tie_en = 0, + .tie_val = 0, + .resv0 = 0, + .pad_di = 0}, + {.ch_sel = FUNC_I2S2_WS, + .ds = 0xf, + .oe_en = 1, + .oe_inv = 0, + .do_sel = 0, + .do_inv = 0, + .pu = 0, + .pd = 0, + .resv1 = 0, + .sl = 0, + .ie_en = 0, + .ie_inv = 0, + .di_inv = 0, + .st = 0, + .tie_en = 0, + .tie_val = 0, + .resv0 = 0, + .pad_di = 0}, + {.ch_sel = FUNC_I2S2_IN_D0, + .ds = 0x0, + .oe_en = 0, + .oe_inv = 0, + .do_sel = 0, + .do_inv = 0, + .pu = 0, + .pd = 0, + .resv1 = 0, + .sl = 0, + .ie_en = 1, + .ie_inv = 0, + .di_inv = 0, + .st = 1, + .tie_en = 0, + .tie_val = 0, + .resv0 = 0, + .pad_di = 0}, + {.ch_sel = FUNC_I2S2_IN_D1, + .ds = 0x0, + .oe_en = 0, + .oe_inv = 0, + .do_sel = 0, + .do_inv = 0, + .pu = 0, + .pd = 0, + .resv1 = 0, + .sl = 0, + .ie_en = 1, + .ie_inv = 0, + .di_inv = 0, + .st = 1, + .tie_en = 0, + .tie_val = 0, + .resv0 = 0, + .pad_di = 0}, + {.ch_sel = FUNC_I2S2_IN_D2, + .ds = 0x0, + .oe_en = 0, + .oe_inv = 0, + .do_sel = 0, + .do_inv = 0, + .pu = 0, + .pd = 0, + .resv1 = 0, + .sl = 0, + .ie_en = 1, + .ie_inv = 0, + .di_inv = 0, + .st = 1, + .tie_en = 0, + .tie_val = 0, + .resv0 = 0, + .pad_di = 0}, + {.ch_sel = FUNC_I2S2_IN_D3, + .ds = 0x0, + .oe_en = 0, + .oe_inv = 0, + .do_sel = 0, + .do_inv = 0, + .pu = 0, + .pd = 0, + .resv1 = 0, + .sl = 0, + .ie_en = 1, + .ie_inv = 0, + .di_inv = 0, + .st = 1, + .tie_en = 0, + .tie_val = 0, + .resv0 = 0, + .pad_di = 0}, + {.ch_sel = FUNC_I2S2_OUT_D0, + .ds = 0xf, + .oe_en = 1, + .oe_inv = 0, + .do_sel = 0, + .do_inv = 0, + .pu = 0, + .pd = 0, + .resv1 = 0, + .sl = 0, + .ie_en = 0, + .ie_inv = 0, + .di_inv = 0, + .st = 0, + .tie_en = 0, + .tie_val = 0, + .resv0 = 0, + .pad_di = 0}, + {.ch_sel = FUNC_I2S2_OUT_D1, + .ds = 0xf, + .oe_en = 1, + .oe_inv = 0, + .do_sel = 0, + .do_inv = 0, + .pu = 0, + .pd = 0, + .resv1 = 0, + .sl = 0, + .ie_en = 0, + .ie_inv = 0, + .di_inv = 0, + .st = 0, + .tie_en = 0, + .tie_val = 0, + .resv0 = 0, + .pad_di = 0}, + {.ch_sel = FUNC_I2S2_OUT_D2, + .ds = 0xf, + .oe_en = 1, + .oe_inv = 0, + .do_sel = 0, + .do_inv = 0, + .pu = 0, + .pd = 0, + .resv1 = 0, + .sl = 0, + .ie_en = 0, + .ie_inv = 0, + .di_inv = 0, + .st = 0, + .tie_en = 0, + .tie_val = 0, + .resv0 = 0, + .pad_di = 0}, + {.ch_sel = FUNC_I2S2_OUT_D3, + .ds = 0xf, + .oe_en = 1, + .oe_inv = 0, + .do_sel = 0, + .do_inv = 0, + .pu = 0, + .pd = 0, + .resv1 = 0, + .sl = 0, + .ie_en = 0, + .ie_inv = 0, + .di_inv = 0, + .st = 0, + .tie_en = 0, + .tie_val = 0, + .resv0 = 0, + .pad_di = 0}, + {.ch_sel = FUNC_RESV0, + .ds = 0x0, + .oe_en = 0, + .oe_inv = 0, + .do_sel = 0, + .do_inv = 0, + .pu = 0, + .pd = 0, + .resv1 = 0, + .sl = 0, + .ie_en = 0, + .ie_inv = 0, + .di_inv = 0, + .st = 0, + .tie_en = 0, + .tie_val = 0, + .resv0 = 0, + .pad_di = 0}, + {.ch_sel = FUNC_RESV1, + .ds = 0x0, + .oe_en = 0, + .oe_inv = 0, + .do_sel = 0, + .do_inv = 0, + .pu = 0, + .pd = 0, + .resv1 = 0, + .sl = 0, + .ie_en = 0, + .ie_inv = 0, + .di_inv = 0, + .st = 0, + .tie_en = 0, + .tie_val = 0, + .resv0 = 0, + .pad_di = 0}, + {.ch_sel = FUNC_RESV2, + .ds = 0x0, + .oe_en = 0, + .oe_inv = 0, + .do_sel = 0, + .do_inv = 0, + .pu = 0, + .pd = 0, + .resv1 = 0, + .sl = 0, + .ie_en = 0, + .ie_inv = 0, + .di_inv = 0, + .st = 0, + .tie_en = 0, + .tie_val = 0, + .resv0 = 0, + .pad_di = 0}, + {.ch_sel = FUNC_RESV3, + .ds = 0x0, + .oe_en = 0, + .oe_inv = 0, + .do_sel = 0, + .do_inv = 0, + .pu = 0, + .pd = 0, + .resv1 = 0, + .sl = 0, + .ie_en = 0, + .ie_inv = 0, + .di_inv = 0, + .st = 0, + .tie_en = 0, + .tie_val = 0, + .resv0 = 0, + .pad_di = 0}, + {.ch_sel = FUNC_RESV4, + .ds = 0x0, + .oe_en = 0, + .oe_inv = 0, + .do_sel = 0, + .do_inv = 0, + .pu = 0, + .pd = 0, + .resv1 = 0, + .sl = 0, + .ie_en = 0, + .ie_inv = 0, + .di_inv = 0, + .st = 0, + .tie_en = 0, + .tie_val = 0, + .resv0 = 0, + .pad_di = 0}, + {.ch_sel = FUNC_RESV5, + .ds = 0x0, + .oe_en = 0, + .oe_inv = 0, + .do_sel = 0, + .do_inv = 0, + .pu = 0, + .pd = 0, + .resv1 = 0, + .sl = 0, + .ie_en = 0, + .ie_inv = 0, + .di_inv = 0, + .st = 0, + .tie_en = 0, + .tie_val = 0, + .resv0 = 0, + .pad_di = 0}, + {.ch_sel = FUNC_I2C0_SCLK, + .ds = 0x0, + .oe_en = 1, + .oe_inv = 0, + .do_sel = 0, + .do_inv = 0, + .pu = 1, + .pd = 0, + .resv1 = 0, + .sl = 1, + .ie_en = 1, + .ie_inv = 0, + .di_inv = 0, + .st = 1, + .tie_en = 0, + .tie_val = 0, + .resv0 = 0, + .pad_di = 0}, + {.ch_sel = FUNC_I2C0_SDA, + .ds = 0x0, + .oe_en = 1, + .oe_inv = 0, + .do_sel = 0, + .do_inv = 0, + .pu = 1, + .pd = 0, + .resv1 = 0, + .sl = 1, + .ie_en = 1, + .ie_inv = 0, + .di_inv = 0, + .st = 1, + .tie_en = 0, + .tie_val = 0, + .resv0 = 0, + .pad_di = 0}, + {.ch_sel = FUNC_I2C1_SCLK, + .ds = 0x0, + .oe_en = 1, + .oe_inv = 0, + .do_sel = 0, + .do_inv = 0, + .pu = 1, + .pd = 0, + .resv1 = 0, + .sl = 1, + .ie_en = 1, + .ie_inv = 0, + .di_inv = 0, + .st = 1, + .tie_en = 0, + .tie_val = 0, + .resv0 = 0, + .pad_di = 0}, + {.ch_sel = FUNC_I2C1_SDA, + .ds = 0x0, + .oe_en = 1, + .oe_inv = 0, + .do_sel = 0, + .do_inv = 0, + .pu = 1, + .pd = 0, + .resv1 = 0, + .sl = 1, + .ie_en = 1, + .ie_inv = 0, + .di_inv = 0, + .st = 1, + .tie_en = 0, + .tie_val = 0, + .resv0 = 0, + .pad_di = 0}, + {.ch_sel = FUNC_I2C2_SCLK, + .ds = 0x0, + .oe_en = 1, + .oe_inv = 0, + .do_sel = 0, + .do_inv = 0, + .pu = 1, + .pd = 0, + .resv1 = 0, + .sl = 1, + .ie_en = 1, + .ie_inv = 0, + .di_inv = 0, + .st = 1, + .tie_en = 0, + .tie_val = 0, + .resv0 = 0, + .pad_di = 0}, + {.ch_sel = FUNC_I2C2_SDA, + .ds = 0x0, + .oe_en = 1, + .oe_inv = 0, + .do_sel = 0, + .do_inv = 0, + .pu = 1, + .pd = 0, + .resv1 = 0, + .sl = 1, + .ie_en = 1, + .ie_inv = 0, + .di_inv = 0, + .st = 1, + .tie_en = 0, + .tie_val = 0, + .resv0 = 0, + .pad_di = 0}, + {.ch_sel = FUNC_CMOS_XCLK, + .ds = 0xf, + .oe_en = 1, + .oe_inv = 0, + .do_sel = 0, + .do_inv = 0, + .pu = 0, + .pd = 0, + .resv1 = 0, + .sl = 0, + .ie_en = 0, + .ie_inv = 0, + .di_inv = 0, + .st = 0, + .tie_en = 0, + .tie_val = 0, + .resv0 = 0, + .pad_di = 0}, + {.ch_sel = FUNC_CMOS_RST, + .ds = 0xf, + .oe_en = 1, + .oe_inv = 0, + .do_sel = 0, + .do_inv = 0, + .pu = 0, + .pd = 0, + .resv1 = 0, + .sl = 0, + .ie_en = 0, + .ie_inv = 0, + .di_inv = 0, + .st = 0, + .tie_en = 0, + .tie_val = 0, + .resv0 = 0, + .pad_di = 0}, + {.ch_sel = FUNC_CMOS_PWDN, + .ds = 0xf, + .oe_en = 1, + .oe_inv = 0, + .do_sel = 0, + .do_inv = 0, + .pu = 0, + .pd = 0, + .resv1 = 0, + .sl = 0, + .ie_en = 0, + .ie_inv = 0, + .di_inv = 0, + .st = 0, + .tie_en = 0, + .tie_val = 0, + .resv0 = 0, + .pad_di = 0}, + {.ch_sel = FUNC_CMOS_VSYNC, + .ds = 0x0, + .oe_en = 0, + .oe_inv = 0, + .do_sel = 0, + .do_inv = 0, + .pu = 0, + .pd = 0, + .resv1 = 0, + .sl = 0, + .ie_en = 1, + .ie_inv = 0, + .di_inv = 0, + .st = 1, + .tie_en = 0, + .tie_val = 0, + .resv0 = 0, + .pad_di = 0}, + {.ch_sel = FUNC_CMOS_HREF, + .ds = 0x0, + .oe_en = 0, + .oe_inv = 0, + .do_sel = 0, + .do_inv = 0, + .pu = 0, + .pd = 0, + .resv1 = 0, + .sl = 0, + .ie_en = 1, + .ie_inv = 0, + .di_inv = 0, + .st = 1, + .tie_en = 0, + .tie_val = 0, + .resv0 = 0, + .pad_di = 0}, + {.ch_sel = FUNC_CMOS_PCLK, + .ds = 0x0, + .oe_en = 0, + .oe_inv = 0, + .do_sel = 0, + .do_inv = 0, + .pu = 0, + .pd = 0, + .resv1 = 0, + .sl = 0, + .ie_en = 1, + .ie_inv = 0, + .di_inv = 0, + .st = 1, + .tie_en = 0, + .tie_val = 0, + .resv0 = 0, + .pad_di = 0}, + {.ch_sel = FUNC_CMOS_D0, + .ds = 0x0, + .oe_en = 0, + .oe_inv = 0, + .do_sel = 0, + .do_inv = 0, + .pu = 0, + .pd = 0, + .resv1 = 0, + .sl = 0, + .ie_en = 1, + .ie_inv = 0, + .di_inv = 0, + .st = 1, + .tie_en = 0, + .tie_val = 0, + .resv0 = 0, + .pad_di = 0}, + {.ch_sel = FUNC_CMOS_D1, + .ds = 0x0, + .oe_en = 0, + .oe_inv = 0, + .do_sel = 0, + .do_inv = 0, + .pu = 0, + .pd = 0, + .resv1 = 0, + .sl = 0, + .ie_en = 1, + .ie_inv = 0, + .di_inv = 0, + .st = 1, + .tie_en = 0, + .tie_val = 0, + .resv0 = 0, + .pad_di = 0}, + {.ch_sel = FUNC_CMOS_D2, + .ds = 0x0, + .oe_en = 0, + .oe_inv = 0, + .do_sel = 0, + .do_inv = 0, + .pu = 0, + .pd = 0, + .resv1 = 0, + .sl = 0, + .ie_en = 1, + .ie_inv = 0, + .di_inv = 0, + .st = 1, + .tie_en = 0, + .tie_val = 0, + .resv0 = 0, + .pad_di = 0}, + {.ch_sel = FUNC_CMOS_D3, + .ds = 0x0, + .oe_en = 0, + .oe_inv = 0, + .do_sel = 0, + .do_inv = 0, + .pu = 0, + .pd = 0, + .resv1 = 0, + .sl = 0, + .ie_en = 1, + .ie_inv = 0, + .di_inv = 0, + .st = 1, + .tie_en = 0, + .tie_val = 0, + .resv0 = 0, + .pad_di = 0}, + {.ch_sel = FUNC_CMOS_D4, + .ds = 0x0, + .oe_en = 0, + .oe_inv = 0, + .do_sel = 0, + .do_inv = 0, + .pu = 0, + .pd = 0, + .resv1 = 0, + .sl = 0, + .ie_en = 1, + .ie_inv = 0, + .di_inv = 0, + .st = 1, + .tie_en = 0, + .tie_val = 0, + .resv0 = 0, + .pad_di = 0}, + {.ch_sel = FUNC_CMOS_D5, + .ds = 0x0, + .oe_en = 0, + .oe_inv = 0, + .do_sel = 0, + .do_inv = 0, + .pu = 0, + .pd = 0, + .resv1 = 0, + .sl = 0, + .ie_en = 1, + .ie_inv = 0, + .di_inv = 0, + .st = 1, + .tie_en = 0, + .tie_val = 0, + .resv0 = 0, + .pad_di = 0}, + {.ch_sel = FUNC_CMOS_D6, + .ds = 0x0, + .oe_en = 0, + .oe_inv = 0, + .do_sel = 0, + .do_inv = 0, + .pu = 0, + .pd = 0, + .resv1 = 0, + .sl = 0, + .ie_en = 1, + .ie_inv = 0, + .di_inv = 0, + .st = 1, + .tie_en = 0, + .tie_val = 0, + .resv0 = 0, + .pad_di = 0}, + {.ch_sel = FUNC_CMOS_D7, + .ds = 0x0, + .oe_en = 0, + .oe_inv = 0, + .do_sel = 0, + .do_inv = 0, + .pu = 0, + .pd = 0, + .resv1 = 0, + .sl = 0, + .ie_en = 1, + .ie_inv = 0, + .di_inv = 0, + .st = 1, + .tie_en = 0, + .tie_val = 0, + .resv0 = 0, + .pad_di = 0}, + {.ch_sel = FUNC_SCCB_SCLK, + .ds = 0x0, + .oe_en = 1, + .oe_inv = 1, + .do_sel = 0, + .do_inv = 0, + .pu = 1, + .pd = 0, + .resv1 = 0, + .sl = 1, + .ie_en = 1, + .ie_inv = 0, + .di_inv = 0, + .st = 1, + .tie_en = 0, + .tie_val = 0, + .resv0 = 0, + .pad_di = 0}, + {.ch_sel = FUNC_SCCB_SDA, + .ds = 0x0, + .oe_en = 1, + .oe_inv = 1, + .do_sel = 0, + .do_inv = 0, + .pu = 1, + .pd = 0, + .resv1 = 0, + .sl = 1, + .ie_en = 1, + .ie_inv = 0, + .di_inv = 0, + .st = 1, + .tie_en = 0, + .tie_val = 0, + .resv0 = 0, + .pad_di = 0}, + {.ch_sel = FUNC_UART1_CTS, + .ds = 0x0, + .oe_en = 0, + .oe_inv = 0, + .do_sel = 0, + .do_inv = 0, + .pu = 0, + .pd = 0, + .resv1 = 0, + .sl = 0, + .ie_en = 1, + .ie_inv = 0, + .di_inv = 0, + .st = 1, + .tie_en = 0, + .tie_val = 0, + .resv0 = 0, + .pad_di = 0}, + {.ch_sel = FUNC_UART1_DSR, + .ds = 0x0, + .oe_en = 0, + .oe_inv = 0, + .do_sel = 0, + .do_inv = 0, + .pu = 0, + .pd = 0, + .resv1 = 0, + .sl = 0, + .ie_en = 1, + .ie_inv = 0, + .di_inv = 0, + .st = 1, + .tie_en = 0, + .tie_val = 0, + .resv0 = 0, + .pad_di = 0}, + {.ch_sel = FUNC_UART1_DCD, + .ds = 0x0, + .oe_en = 0, + .oe_inv = 0, + .do_sel = 0, + .do_inv = 0, + .pu = 0, + .pd = 0, + .resv1 = 0, + .sl = 0, + .ie_en = 1, + .ie_inv = 0, + .di_inv = 0, + .st = 1, + .tie_en = 0, + .tie_val = 0, + .resv0 = 0, + .pad_di = 0}, + {.ch_sel = FUNC_UART1_RI, + .ds = 0x0, + .oe_en = 0, + .oe_inv = 0, + .do_sel = 0, + .do_inv = 0, + .pu = 0, + .pd = 0, + .resv1 = 0, + .sl = 0, + .ie_en = 1, + .ie_inv = 0, + .di_inv = 0, + .st = 1, + .tie_en = 0, + .tie_val = 0, + .resv0 = 0, + .pad_di = 0}, + {.ch_sel = FUNC_UART1_SIR_IN, + .ds = 0x0, + .oe_en = 0, + .oe_inv = 0, + .do_sel = 0, + .do_inv = 0, + .pu = 0, + .pd = 0, + .resv1 = 0, + .sl = 0, + .ie_en = 1, + .ie_inv = 0, + .di_inv = 0, + .st = 1, + .tie_en = 0, + .tie_val = 0, + .resv0 = 0, + .pad_di = 0}, + {.ch_sel = FUNC_UART1_DTR, + .ds = 0xf, + .oe_en = 1, + .oe_inv = 0, + .do_sel = 0, + .do_inv = 0, + .pu = 0, + .pd = 0, + .resv1 = 0, + .sl = 0, + .ie_en = 0, + .ie_inv = 0, + .di_inv = 0, + .st = 0, + .tie_en = 0, + .tie_val = 0, + .resv0 = 0, + .pad_di = 0}, + {.ch_sel = FUNC_UART1_RTS, + .ds = 0xf, + .oe_en = 1, + .oe_inv = 0, + .do_sel = 0, + .do_inv = 0, + .pu = 0, + .pd = 0, + .resv1 = 0, + .sl = 0, + .ie_en = 0, + .ie_inv = 0, + .di_inv = 0, + .st = 0, + .tie_en = 0, + .tie_val = 0, + .resv0 = 0, + .pad_di = 0}, + {.ch_sel = FUNC_UART1_OUT2, + .ds = 0xf, + .oe_en = 1, + .oe_inv = 0, + .do_sel = 0, + .do_inv = 0, + .pu = 0, + .pd = 0, + .resv1 = 0, + .sl = 0, + .ie_en = 0, + .ie_inv = 0, + .di_inv = 0, + .st = 0, + .tie_en = 0, + .tie_val = 0, + .resv0 = 0, + .pad_di = 0}, + {.ch_sel = FUNC_UART1_OUT1, + .ds = 0xf, + .oe_en = 1, + .oe_inv = 0, + .do_sel = 0, + .do_inv = 0, + .pu = 0, + .pd = 0, + .resv1 = 0, + .sl = 0, + .ie_en = 0, + .ie_inv = 0, + .di_inv = 0, + .st = 0, + .tie_en = 0, + .tie_val = 0, + .resv0 = 0, + .pad_di = 0}, + {.ch_sel = FUNC_UART1_SIR_OUT, + .ds = 0xf, + .oe_en = 1, + .oe_inv = 0, + .do_sel = 0, + .do_inv = 0, + .pu = 0, + .pd = 0, + .resv1 = 0, + .sl = 0, + .ie_en = 0, + .ie_inv = 0, + .di_inv = 0, + .st = 0, + .tie_en = 0, + .tie_val = 0, + .resv0 = 0, + .pad_di = 0}, + {.ch_sel = FUNC_UART1_BAUD, + .ds = 0xf, + .oe_en = 1, + .oe_inv = 0, + .do_sel = 0, + .do_inv = 0, + .pu = 0, + .pd = 0, + .resv1 = 0, + .sl = 0, + .ie_en = 0, + .ie_inv = 0, + .di_inv = 0, + .st = 0, + .tie_en = 0, + .tie_val = 0, + .resv0 = 0, + .pad_di = 0}, + {.ch_sel = FUNC_UART1_RE, + .ds = 0xf, + .oe_en = 1, + .oe_inv = 0, + .do_sel = 0, + .do_inv = 0, + .pu = 0, + .pd = 0, + .resv1 = 0, + .sl = 0, + .ie_en = 0, + .ie_inv = 0, + .di_inv = 0, + .st = 0, + .tie_en = 0, + .tie_val = 0, + .resv0 = 0, + .pad_di = 0}, + {.ch_sel = FUNC_UART1_DE, + .ds = 0xf, + .oe_en = 1, + .oe_inv = 0, + .do_sel = 0, + .do_inv = 0, + .pu = 0, + .pd = 0, + .resv1 = 0, + .sl = 0, + .ie_en = 0, + .ie_inv = 0, + .di_inv = 0, + .st = 0, + .tie_en = 0, + .tie_val = 0, + .resv0 = 0, + .pad_di = 0}, + {.ch_sel = FUNC_UART1_RS485_EN, + .ds = 0xf, + .oe_en = 1, + .oe_inv = 0, + .do_sel = 0, + .do_inv = 0, + .pu = 0, + .pd = 0, + .resv1 = 0, + .sl = 0, + .ie_en = 0, + .ie_inv = 0, + .di_inv = 0, + .st = 0, + .tie_en = 0, + .tie_val = 0, + .resv0 = 0, + .pad_di = 0}, + {.ch_sel = FUNC_UART2_CTS, + .ds = 0x0, + .oe_en = 0, + .oe_inv = 0, + .do_sel = 0, + .do_inv = 0, + .pu = 0, + .pd = 0, + .resv1 = 0, + .sl = 0, + .ie_en = 1, + .ie_inv = 0, + .di_inv = 0, + .st = 1, + .tie_en = 0, + .tie_val = 0, + .resv0 = 0, + .pad_di = 0}, + {.ch_sel = FUNC_UART2_DSR, + .ds = 0x0, + .oe_en = 0, + .oe_inv = 0, + .do_sel = 0, + .do_inv = 0, + .pu = 0, + .pd = 0, + .resv1 = 0, + .sl = 0, + .ie_en = 1, + .ie_inv = 0, + .di_inv = 0, + .st = 1, + .tie_en = 0, + .tie_val = 0, + .resv0 = 0, + .pad_di = 0}, + {.ch_sel = FUNC_UART2_DCD, + .ds = 0x0, + .oe_en = 0, + .oe_inv = 0, + .do_sel = 0, + .do_inv = 0, + .pu = 0, + .pd = 0, + .resv1 = 0, + .sl = 0, + .ie_en = 1, + .ie_inv = 0, + .di_inv = 0, + .st = 1, + .tie_en = 0, + .tie_val = 0, + .resv0 = 0, + .pad_di = 0}, + {.ch_sel = FUNC_UART2_RI, + .ds = 0x0, + .oe_en = 0, + .oe_inv = 0, + .do_sel = 0, + .do_inv = 0, + .pu = 0, + .pd = 0, + .resv1 = 0, + .sl = 0, + .ie_en = 1, + .ie_inv = 0, + .di_inv = 0, + .st = 1, + .tie_en = 0, + .tie_val = 0, + .resv0 = 0, + .pad_di = 0}, + {.ch_sel = FUNC_UART2_SIR_IN, + .ds = 0x0, + .oe_en = 0, + .oe_inv = 0, + .do_sel = 0, + .do_inv = 0, + .pu = 0, + .pd = 0, + .resv1 = 0, + .sl = 0, + .ie_en = 1, + .ie_inv = 0, + .di_inv = 0, + .st = 1, + .tie_en = 0, + .tie_val = 0, + .resv0 = 0, + .pad_di = 0}, + {.ch_sel = FUNC_UART2_DTR, + .ds = 0xf, + .oe_en = 1, + .oe_inv = 0, + .do_sel = 0, + .do_inv = 0, + .pu = 0, + .pd = 0, + .resv1 = 0, + .sl = 0, + .ie_en = 0, + .ie_inv = 0, + .di_inv = 0, + .st = 0, + .tie_en = 0, + .tie_val = 0, + .resv0 = 0, + .pad_di = 0}, + {.ch_sel = FUNC_UART2_RTS, + .ds = 0xf, + .oe_en = 1, + .oe_inv = 0, + .do_sel = 0, + .do_inv = 0, + .pu = 0, + .pd = 0, + .resv1 = 0, + .sl = 0, + .ie_en = 0, + .ie_inv = 0, + .di_inv = 0, + .st = 0, + .tie_en = 0, + .tie_val = 0, + .resv0 = 0, + .pad_di = 0}, + {.ch_sel = FUNC_UART2_OUT2, + .ds = 0xf, + .oe_en = 1, + .oe_inv = 0, + .do_sel = 0, + .do_inv = 0, + .pu = 0, + .pd = 0, + .resv1 = 0, + .sl = 0, + .ie_en = 0, + .ie_inv = 0, + .di_inv = 0, + .st = 0, + .tie_en = 0, + .tie_val = 0, + .resv0 = 0, + .pad_di = 0}, + {.ch_sel = FUNC_UART2_OUT1, + .ds = 0xf, + .oe_en = 1, + .oe_inv = 0, + .do_sel = 0, + .do_inv = 0, + .pu = 0, + .pd = 0, + .resv1 = 0, + .sl = 0, + .ie_en = 0, + .ie_inv = 0, + .di_inv = 0, + .st = 0, + .tie_en = 0, + .tie_val = 0, + .resv0 = 0, + .pad_di = 0}, + {.ch_sel = FUNC_UART2_SIR_OUT, + .ds = 0xf, + .oe_en = 1, + .oe_inv = 0, + .do_sel = 0, + .do_inv = 0, + .pu = 0, + .pd = 0, + .resv1 = 0, + .sl = 0, + .ie_en = 0, + .ie_inv = 0, + .di_inv = 0, + .st = 0, + .tie_en = 0, + .tie_val = 0, + .resv0 = 0, + .pad_di = 0}, + {.ch_sel = FUNC_UART2_BAUD, + .ds = 0xf, + .oe_en = 1, + .oe_inv = 0, + .do_sel = 0, + .do_inv = 0, + .pu = 0, + .pd = 0, + .resv1 = 0, + .sl = 0, + .ie_en = 0, + .ie_inv = 0, + .di_inv = 0, + .st = 0, + .tie_en = 0, + .tie_val = 0, + .resv0 = 0, + .pad_di = 0}, + {.ch_sel = FUNC_UART2_RE, + .ds = 0xf, + .oe_en = 1, + .oe_inv = 0, + .do_sel = 0, + .do_inv = 0, + .pu = 0, + .pd = 0, + .resv1 = 0, + .sl = 0, + .ie_en = 0, + .ie_inv = 0, + .di_inv = 0, + .st = 0, + .tie_en = 0, + .tie_val = 0, + .resv0 = 0, + .pad_di = 0}, + {.ch_sel = FUNC_UART2_DE, + .ds = 0xf, + .oe_en = 1, + .oe_inv = 0, + .do_sel = 0, + .do_inv = 0, + .pu = 0, + .pd = 0, + .resv1 = 0, + .sl = 0, + .ie_en = 0, + .ie_inv = 0, + .di_inv = 0, + .st = 0, + .tie_en = 0, + .tie_val = 0, + .resv0 = 0, + .pad_di = 0}, + {.ch_sel = FUNC_UART2_RS485_EN, + .ds = 0xf, + .oe_en = 1, + .oe_inv = 0, + .do_sel = 0, + .do_inv = 0, + .pu = 0, + .pd = 0, + .resv1 = 0, + .sl = 0, + .ie_en = 0, + .ie_inv = 0, + .di_inv = 0, + .st = 0, + .tie_en = 0, + .tie_val = 0, + .resv0 = 0, + .pad_di = 0}, + {.ch_sel = FUNC_UART3_CTS, + .ds = 0x0, + .oe_en = 0, + .oe_inv = 0, + .do_sel = 0, + .do_inv = 0, + .pu = 0, + .pd = 0, + .resv1 = 0, + .sl = 0, + .ie_en = 1, + .ie_inv = 0, + .di_inv = 0, + .st = 1, + .tie_en = 0, + .tie_val = 0, + .resv0 = 0, + .pad_di = 0}, + {.ch_sel = FUNC_UART3_DSR, + .ds = 0x0, + .oe_en = 0, + .oe_inv = 0, + .do_sel = 0, + .do_inv = 0, + .pu = 0, + .pd = 0, + .resv1 = 0, + .sl = 0, + .ie_en = 1, + .ie_inv = 0, + .di_inv = 0, + .st = 1, + .tie_en = 0, + .tie_val = 0, + .resv0 = 0, + .pad_di = 0}, + {.ch_sel = FUNC_UART3_DCD, + .ds = 0x0, + .oe_en = 0, + .oe_inv = 0, + .do_sel = 0, + .do_inv = 0, + .pu = 0, + .pd = 0, + .resv1 = 0, + .sl = 0, + .ie_en = 1, + .ie_inv = 0, + .di_inv = 0, + .st = 1, + .tie_en = 0, + .tie_val = 0, + .resv0 = 0, + .pad_di = 0}, + {.ch_sel = FUNC_UART3_RI, + .ds = 0x0, + .oe_en = 0, + .oe_inv = 0, + .do_sel = 0, + .do_inv = 0, + .pu = 0, + .pd = 0, + .resv1 = 0, + .sl = 0, + .ie_en = 1, + .ie_inv = 0, + .di_inv = 0, + .st = 1, + .tie_en = 0, + .tie_val = 0, + .resv0 = 0, + .pad_di = 0}, + {.ch_sel = FUNC_UART3_SIR_IN, + .ds = 0x0, + .oe_en = 0, + .oe_inv = 0, + .do_sel = 0, + .do_inv = 0, + .pu = 0, + .pd = 0, + .resv1 = 0, + .sl = 0, + .ie_en = 1, + .ie_inv = 0, + .di_inv = 0, + .st = 1, + .tie_en = 0, + .tie_val = 0, + .resv0 = 0, + .pad_di = 0}, + {.ch_sel = FUNC_UART3_DTR, + .ds = 0xf, + .oe_en = 1, + .oe_inv = 0, + .do_sel = 0, + .do_inv = 0, + .pu = 0, + .pd = 0, + .resv1 = 0, + .sl = 0, + .ie_en = 0, + .ie_inv = 0, + .di_inv = 0, + .st = 0, + .tie_en = 0, + .tie_val = 0, + .resv0 = 0, + .pad_di = 0}, + {.ch_sel = FUNC_UART3_RTS, + .ds = 0xf, + .oe_en = 1, + .oe_inv = 0, + .do_sel = 0, + .do_inv = 0, + .pu = 0, + .pd = 0, + .resv1 = 0, + .sl = 0, + .ie_en = 0, + .ie_inv = 0, + .di_inv = 0, + .st = 0, + .tie_en = 0, + .tie_val = 0, + .resv0 = 0, + .pad_di = 0}, + {.ch_sel = FUNC_UART3_OUT2, + .ds = 0xf, + .oe_en = 1, + .oe_inv = 0, + .do_sel = 0, + .do_inv = 0, + .pu = 0, + .pd = 0, + .resv1 = 0, + .sl = 0, + .ie_en = 0, + .ie_inv = 0, + .di_inv = 0, + .st = 0, + .tie_en = 0, + .tie_val = 0, + .resv0 = 0, + .pad_di = 0}, + {.ch_sel = FUNC_UART3_OUT1, + .ds = 0xf, + .oe_en = 1, + .oe_inv = 0, + .do_sel = 0, + .do_inv = 0, + .pu = 0, + .pd = 0, + .resv1 = 0, + .sl = 0, + .ie_en = 0, + .ie_inv = 0, + .di_inv = 0, + .st = 0, + .tie_en = 0, + .tie_val = 0, + .resv0 = 0, + .pad_di = 0}, + {.ch_sel = FUNC_UART3_SIR_OUT, + .ds = 0xf, + .oe_en = 1, + .oe_inv = 0, + .do_sel = 0, + .do_inv = 0, + .pu = 0, + .pd = 0, + .resv1 = 0, + .sl = 0, + .ie_en = 0, + .ie_inv = 0, + .di_inv = 0, + .st = 0, + .tie_en = 0, + .tie_val = 0, + .resv0 = 0, + .pad_di = 0}, + {.ch_sel = FUNC_UART3_BAUD, + .ds = 0xf, + .oe_en = 1, + .oe_inv = 0, + .do_sel = 0, + .do_inv = 0, + .pu = 0, + .pd = 0, + .resv1 = 0, + .sl = 0, + .ie_en = 0, + .ie_inv = 0, + .di_inv = 0, + .st = 0, + .tie_en = 0, + .tie_val = 0, + .resv0 = 0, + .pad_di = 0}, + {.ch_sel = FUNC_UART3_RE, + .ds = 0xf, + .oe_en = 1, + .oe_inv = 0, + .do_sel = 0, + .do_inv = 0, + .pu = 0, + .pd = 0, + .resv1 = 0, + .sl = 0, + .ie_en = 0, + .ie_inv = 0, + .di_inv = 0, + .st = 0, + .tie_en = 0, + .tie_val = 0, + .resv0 = 0, + .pad_di = 0}, + {.ch_sel = FUNC_UART3_DE, + .ds = 0xf, + .oe_en = 1, + .oe_inv = 0, + .do_sel = 0, + .do_inv = 0, + .pu = 0, + .pd = 0, + .resv1 = 0, + .sl = 0, + .ie_en = 0, + .ie_inv = 0, + .di_inv = 0, + .st = 0, + .tie_en = 0, + .tie_val = 0, + .resv0 = 0, + .pad_di = 0}, + {.ch_sel = FUNC_UART3_RS485_EN, + .ds = 0xf, + .oe_en = 1, + .oe_inv = 0, + .do_sel = 0, + .do_inv = 0, + .pu = 0, + .pd = 0, + .resv1 = 0, + .sl = 0, + .ie_en = 0, + .ie_inv = 0, + .di_inv = 0, + .st = 0, + .tie_en = 0, + .tie_val = 0, + .resv0 = 0, + .pad_di = 0}, + {.ch_sel = FUNC_TIMER0_TOGGLE1, + .ds = 0xf, + .oe_en = 1, + .oe_inv = 0, + .do_sel = 0, + .do_inv = 0, + .pu = 0, + .pd = 0, + .resv1 = 0, + .sl = 0, + .ie_en = 0, + .ie_inv = 0, + .di_inv = 0, + .st = 0, + .tie_en = 0, + .tie_val = 0, + .resv0 = 0, + .pad_di = 0}, + {.ch_sel = FUNC_TIMER0_TOGGLE2, + .ds = 0xf, + .oe_en = 1, + .oe_inv = 0, + .do_sel = 0, + .do_inv = 0, + .pu = 0, + .pd = 0, + .resv1 = 0, + .sl = 0, + .ie_en = 0, + .ie_inv = 0, + .di_inv = 0, + .st = 0, + .tie_en = 0, + .tie_val = 0, + .resv0 = 0, + .pad_di = 0}, + {.ch_sel = FUNC_TIMER0_TOGGLE3, + .ds = 0xf, + .oe_en = 1, + .oe_inv = 0, + .do_sel = 0, + .do_inv = 0, + .pu = 0, + .pd = 0, + .resv1 = 0, + .sl = 0, + .ie_en = 0, + .ie_inv = 0, + .di_inv = 0, + .st = 0, + .tie_en = 0, + .tie_val = 0, + .resv0 = 0, + .pad_di = 0}, + {.ch_sel = FUNC_TIMER0_TOGGLE4, + .ds = 0xf, + .oe_en = 1, + .oe_inv = 0, + .do_sel = 0, + .do_inv = 0, + .pu = 0, + .pd = 0, + .resv1 = 0, + .sl = 0, + .ie_en = 0, + .ie_inv = 0, + .di_inv = 0, + .st = 0, + .tie_en = 0, + .tie_val = 0, + .resv0 = 0, + .pad_di = 0}, + {.ch_sel = FUNC_TIMER1_TOGGLE1, + .ds = 0xf, + .oe_en = 1, + .oe_inv = 0, + .do_sel = 0, + .do_inv = 0, + .pu = 0, + .pd = 0, + .resv1 = 0, + .sl = 0, + .ie_en = 0, + .ie_inv = 0, + .di_inv = 0, + .st = 0, + .tie_en = 0, + .tie_val = 0, + .resv0 = 0, + .pad_di = 0}, + {.ch_sel = FUNC_TIMER1_TOGGLE2, + .ds = 0xf, + .oe_en = 1, + .oe_inv = 0, + .do_sel = 0, + .do_inv = 0, + .pu = 0, + .pd = 0, + .resv1 = 0, + .sl = 0, + .ie_en = 0, + .ie_inv = 0, + .di_inv = 0, + .st = 0, + .tie_en = 0, + .tie_val = 0, + .resv0 = 0, + .pad_di = 0}, + {.ch_sel = FUNC_TIMER1_TOGGLE3, + .ds = 0xf, + .oe_en = 1, + .oe_inv = 0, + .do_sel = 0, + .do_inv = 0, + .pu = 0, + .pd = 0, + .resv1 = 0, + .sl = 0, + .ie_en = 0, + .ie_inv = 0, + .di_inv = 0, + .st = 0, + .tie_en = 0, + .tie_val = 0, + .resv0 = 0, + .pad_di = 0}, + {.ch_sel = FUNC_TIMER1_TOGGLE4, + .ds = 0xf, + .oe_en = 1, + .oe_inv = 0, + .do_sel = 0, + .do_inv = 0, + .pu = 0, + .pd = 0, + .resv1 = 0, + .sl = 0, + .ie_en = 0, + .ie_inv = 0, + .di_inv = 0, + .st = 0, + .tie_en = 0, + .tie_val = 0, + .resv0 = 0, + .pad_di = 0}, + {.ch_sel = FUNC_TIMER2_TOGGLE1, + .ds = 0xf, + .oe_en = 1, + .oe_inv = 0, + .do_sel = 0, + .do_inv = 0, + .pu = 0, + .pd = 0, + .resv1 = 0, + .sl = 0, + .ie_en = 0, + .ie_inv = 0, + .di_inv = 0, + .st = 0, + .tie_en = 0, + .tie_val = 0, + .resv0 = 0, + .pad_di = 0}, + {.ch_sel = FUNC_TIMER2_TOGGLE2, + .ds = 0xf, + .oe_en = 1, + .oe_inv = 0, + .do_sel = 0, + .do_inv = 0, + .pu = 0, + .pd = 0, + .resv1 = 0, + .sl = 0, + .ie_en = 0, + .ie_inv = 0, + .di_inv = 0, + .st = 0, + .tie_en = 0, + .tie_val = 0, + .resv0 = 0, + .pad_di = 0}, + {.ch_sel = FUNC_TIMER2_TOGGLE3, + .ds = 0xf, + .oe_en = 1, + .oe_inv = 0, + .do_sel = 0, + .do_inv = 0, + .pu = 0, + .pd = 0, + .resv1 = 0, + .sl = 0, + .ie_en = 0, + .ie_inv = 0, + .di_inv = 0, + .st = 0, + .tie_en = 0, + .tie_val = 0, + .resv0 = 0, + .pad_di = 0}, + {.ch_sel = FUNC_TIMER2_TOGGLE4, + .ds = 0xf, + .oe_en = 1, + .oe_inv = 0, + .do_sel = 0, + .do_inv = 0, + .pu = 0, + .pd = 0, + .resv1 = 0, + .sl = 0, + .ie_en = 0, + .ie_inv = 0, + .di_inv = 0, + .st = 0, + .tie_en = 0, + .tie_val = 0, + .resv0 = 0, + .pad_di = 0}, + {.ch_sel = FUNC_CLK_SPI2, + .ds = 0xf, + .oe_en = 1, + .oe_inv = 0, + .do_sel = 0, + .do_inv = 0, + .pu = 0, + .pd = 0, + .resv1 = 0, + .sl = 0, + .ie_en = 0, + .ie_inv = 0, + .di_inv = 0, + .st = 0, + .tie_en = 0, + .tie_val = 0, + .resv0 = 0, + .pad_di = 0}, + {.ch_sel = FUNC_CLK_I2C2, + .ds = 0xf, + .oe_en = 1, + .oe_inv = 0, + .do_sel = 0, + .do_inv = 0, + .pu = 0, + .pd = 0, + .resv1 = 0, + .sl = 0, + .ie_en = 0, + .ie_inv = 0, + .di_inv = 0, + .st = 0, + .tie_en = 0, + .tie_val = 0, + .resv0 = 0, + .pad_di = 0}, + {.ch_sel = FUNC_INTERNAL0, + .ds = 0xf, + .oe_en = 1, + .oe_inv = 0, + .do_sel = 0, + .do_inv = 0, + .pu = 0, + .pd = 0, + .resv1 = 0, + .sl = 0, + .ie_en = 0, + .ie_inv = 0, + .di_inv = 0, + .st = 0, + .tie_en = 0, + .tie_val = 0, + .resv0 = 0, + .pad_di = 0}, + {.ch_sel = FUNC_INTERNAL1, + .ds = 0xf, + .oe_en = 1, + .oe_inv = 0, + .do_sel = 0, + .do_inv = 0, + .pu = 0, + .pd = 0, + .resv1 = 0, + .sl = 0, + .ie_en = 0, + .ie_inv = 0, + .di_inv = 0, + .st = 0, + .tie_en = 0, + .tie_val = 0, + .resv0 = 0, + .pad_di = 0}, + {.ch_sel = FUNC_INTERNAL2, + .ds = 0xf, + .oe_en = 1, + .oe_inv = 0, + .do_sel = 0, + .do_inv = 0, + .pu = 0, + .pd = 0, + .resv1 = 0, + .sl = 0, + .ie_en = 0, + .ie_inv = 0, + .di_inv = 0, + .st = 0, + .tie_en = 0, + .tie_val = 0, + .resv0 = 0, + .pad_di = 0}, + {.ch_sel = FUNC_INTERNAL3, + .ds = 0xf, + .oe_en = 1, + .oe_inv = 0, + .do_sel = 0, + .do_inv = 0, + .pu = 0, + .pd = 0, + .resv1 = 0, + .sl = 0, + .ie_en = 0, + .ie_inv = 0, + .di_inv = 0, + .st = 0, + .tie_en = 0, + .tie_val = 0, + .resv0 = 0, + .pad_di = 0}, + {.ch_sel = FUNC_INTERNAL4, + .ds = 0xf, + .oe_en = 1, + .oe_inv = 0, + .do_sel = 0, + .do_inv = 0, + .pu = 0, + .pd = 0, + .resv1 = 0, + .sl = 0, + .ie_en = 0, + .ie_inv = 0, + .di_inv = 0, + .st = 0, + .tie_en = 0, + .tie_val = 0, + .resv0 = 0, + .pad_di = 0}, + {.ch_sel = FUNC_INTERNAL5, + .ds = 0xf, + .oe_en = 1, + .oe_inv = 0, + .do_sel = 0, + .do_inv = 0, + .pu = 0, + .pd = 0, + .resv1 = 0, + .sl = 0, + .ie_en = 0, + .ie_inv = 0, + .di_inv = 0, + .st = 0, + .tie_en = 0, + .tie_val = 0, + .resv0 = 0, + .pad_di = 0}, + {.ch_sel = FUNC_INTERNAL6, + .ds = 0xf, + .oe_en = 1, + .oe_inv = 0, + .do_sel = 0, + .do_inv = 0, + .pu = 0, + .pd = 0, + .resv1 = 0, + .sl = 0, + .ie_en = 0, + .ie_inv = 0, + .di_inv = 0, + .st = 0, + .tie_en = 0, + .tie_val = 0, + .resv0 = 0, + .pad_di = 0}, + {.ch_sel = FUNC_INTERNAL7, + .ds = 0xf, + .oe_en = 1, + .oe_inv = 0, + .do_sel = 0, + .do_inv = 0, + .pu = 0, + .pd = 0, + .resv1 = 0, + .sl = 0, + .ie_en = 0, + .ie_inv = 0, + .di_inv = 0, + .st = 0, + .tie_en = 0, + .tie_val = 0, + .resv0 = 0, + .pad_di = 0}, + {.ch_sel = FUNC_INTERNAL8, + .ds = 0xf, + .oe_en = 1, + .oe_inv = 0, + .do_sel = 0, + .do_inv = 0, + .pu = 0, + .pd = 0, + .resv1 = 0, + .sl = 0, + .ie_en = 0, + .ie_inv = 0, + .di_inv = 0, + .st = 0, + .tie_en = 0, + .tie_val = 0, + .resv0 = 0, + .pad_di = 0}, + {.ch_sel = FUNC_INTERNAL9, + .ds = 0x0, + .oe_en = 0, + .oe_inv = 0, + .do_sel = 0, + .do_inv = 0, + .pu = 0, + .pd = 0, + .resv1 = 0, + .sl = 0, + .ie_en = 1, + .ie_inv = 0, + .di_inv = 0, + .st = 1, + .tie_en = 0, + .tie_val = 0, + .resv0 = 0, + .pad_di = 0}, + {.ch_sel = FUNC_INTERNAL10, + .ds = 0x0, + .oe_en = 0, + .oe_inv = 0, + .do_sel = 0, + .do_inv = 0, + .pu = 0, + .pd = 0, + .resv1 = 0, + .sl = 0, + .ie_en = 1, + .ie_inv = 0, + .di_inv = 0, + .st = 1, + .tie_en = 0, + .tie_val = 0, + .resv0 = 0, + .pad_di = 0}, + {.ch_sel = FUNC_INTERNAL11, + .ds = 0x0, + .oe_en = 0, + .oe_inv = 0, + .do_sel = 0, + .do_inv = 0, + .pu = 0, + .pd = 0, + .resv1 = 0, + .sl = 0, + .ie_en = 1, + .ie_inv = 0, + .di_inv = 0, + .st = 1, + .tie_en = 0, + .tie_val = 0, + .resv0 = 0, + .pad_di = 0}, + {.ch_sel = FUNC_INTERNAL12, + .ds = 0x0, + .oe_en = 0, + .oe_inv = 0, + .do_sel = 0, + .do_inv = 0, + .pu = 0, + .pd = 0, + .resv1 = 0, + .sl = 0, + .ie_en = 1, + .ie_inv = 0, + .di_inv = 0, + .st = 1, + .tie_en = 0, + .tie_val = 0, + .resv0 = 0, + .pad_di = 0}, + {.ch_sel = FUNC_INTERNAL13, + .ds = 0x0, + .oe_en = 0, + .oe_inv = 0, + .do_sel = 0, + .do_inv = 0, + .pu = 1, + .pd = 0, + .resv1 = 0, + .sl = 0, + .ie_en = 1, + .ie_inv = 0, + .di_inv = 0, + .st = 1, + .tie_en = 0, + .tie_val = 0, + .resv0 = 0, + .pad_di = 0}, + {.ch_sel = FUNC_INTERNAL14, + .ds = 0xf, + .oe_en = 1, + .oe_inv = 0, + .do_sel = 0, + .do_inv = 0, + .pu = 1, + .pd = 0, + .resv1 = 0, + .sl = 1, + .ie_en = 1, + .ie_inv = 0, + .di_inv = 0, + .st = 1, + .tie_en = 0, + .tie_val = 0, + .resv0 = 0, + .pad_di = 0}, + {.ch_sel = FUNC_INTERNAL15, + .ds = 0x0, + .oe_en = 0, + .oe_inv = 0, + .do_sel = 0, + .do_inv = 0, + .pu = 0, + .pd = 0, + .resv1 = 0, + .sl = 0, + .ie_en = 1, + .ie_inv = 0, + .di_inv = 0, + .st = 1, + .tie_en = 0, + .tie_val = 0, + .resv0 = 0, + .pad_di = 0}, + {.ch_sel = FUNC_INTERNAL16, + .ds = 0x0, + .oe_en = 0, + .oe_inv = 0, + .do_sel = 0, + .do_inv = 0, + .pu = 0, + .pd = 0, + .resv1 = 0, + .sl = 0, + .ie_en = 1, + .ie_inv = 0, + .di_inv = 0, + .st = 1, + .tie_en = 0, + .tie_val = 0, + .resv0 = 0, + .pad_di = 0}, + {.ch_sel = FUNC_INTERNAL17, + .ds = 0x0, + .oe_en = 0, + .oe_inv = 0, + .do_sel = 0, + .do_inv = 0, + .pu = 0, + .pd = 0, + .resv1 = 0, + .sl = 0, + .ie_en = 1, + .ie_inv = 0, + .di_inv = 0, + .st = 1, + .tie_en = 0, + .tie_val = 0, + .resv0 = 0, + .pad_di = 0}, + {.ch_sel = FUNC_CONSTANT, + .ds = 0x0, + .oe_en = 0, + .oe_inv = 0, + .do_sel = 0, + .do_inv = 0, + .pu = 0, + .pd = 0, + .resv1 = 0, + .sl = 0, + .ie_en = 0, + .ie_inv = 0, + .di_inv = 0, + .st = 0, + .tie_en = 0, + .tie_val = 0, + .resv0 = 0, + .pad_di = 0}, + {.ch_sel = FUNC_INTERNAL18, + .ds = 0x0, + .oe_en = 0, + .oe_inv = 0, + .do_sel = 0, + .do_inv = 0, + .pu = 0, + .pd = 0, + .resv1 = 0, + .sl = 0, + .ie_en = 1, + .ie_inv = 0, + .di_inv = 0, + .st = 1, + .tie_en = 0, + .tie_val = 0, + .resv0 = 0, + .pad_di = 0}, + {.ch_sel = FUNC_DEBUG0, + .ds = 0xf, + .oe_en = 1, + .oe_inv = 0, + .do_sel = 0, + .do_inv = 0, + .pu = 0, + .pd = 0, + .resv1 = 0, + .sl = 0, + .ie_en = 0, + .ie_inv = 0, + .di_inv = 0, + .st = 0, + .tie_en = 0, + .tie_val = 0, + .resv0 = 0, + .pad_di = 0}, + {.ch_sel = FUNC_DEBUG1, + .ds = 0xf, + .oe_en = 1, + .oe_inv = 0, + .do_sel = 0, + .do_inv = 0, + .pu = 0, + .pd = 0, + .resv1 = 0, + .sl = 0, + .ie_en = 0, + .ie_inv = 0, + .di_inv = 0, + .st = 0, + .tie_en = 0, + .tie_val = 0, + .resv0 = 0, + .pad_di = 0}, + {.ch_sel = FUNC_DEBUG2, + .ds = 0xf, + .oe_en = 1, + .oe_inv = 0, + .do_sel = 0, + .do_inv = 0, + .pu = 0, + .pd = 0, + .resv1 = 0, + .sl = 0, + .ie_en = 0, + .ie_inv = 0, + .di_inv = 0, + .st = 0, + .tie_en = 0, + .tie_val = 0, + .resv0 = 0, + .pad_di = 0}, + {.ch_sel = FUNC_DEBUG3, + .ds = 0xf, + .oe_en = 1, + .oe_inv = 0, + .do_sel = 0, + .do_inv = 0, + .pu = 0, + .pd = 0, + .resv1 = 0, + .sl = 0, + .ie_en = 0, + .ie_inv = 0, + .di_inv = 0, + .st = 0, + .tie_en = 0, + .tie_val = 0, + .resv0 = 0, + .pad_di = 0}, + {.ch_sel = FUNC_DEBUG4, + .ds = 0xf, + .oe_en = 1, + .oe_inv = 0, + .do_sel = 0, + .do_inv = 0, + .pu = 0, + .pd = 0, + .resv1 = 0, + .sl = 0, + .ie_en = 0, + .ie_inv = 0, + .di_inv = 0, + .st = 0, + .tie_en = 0, + .tie_val = 0, + .resv0 = 0, + .pad_di = 0}, + {.ch_sel = FUNC_DEBUG5, + .ds = 0xf, + .oe_en = 1, + .oe_inv = 0, + .do_sel = 0, + .do_inv = 0, + .pu = 0, + .pd = 0, + .resv1 = 0, + .sl = 0, + .ie_en = 0, + .ie_inv = 0, + .di_inv = 0, + .st = 0, + .tie_en = 0, + .tie_val = 0, + .resv0 = 0, + .pad_di = 0}, + {.ch_sel = FUNC_DEBUG6, + .ds = 0xf, + .oe_en = 1, + .oe_inv = 0, + .do_sel = 0, + .do_inv = 0, + .pu = 0, + .pd = 0, + .resv1 = 0, + .sl = 0, + .ie_en = 0, + .ie_inv = 0, + .di_inv = 0, + .st = 0, + .tie_en = 0, + .tie_val = 0, + .resv0 = 0, + .pad_di = 0}, + {.ch_sel = FUNC_DEBUG7, + .ds = 0xf, + .oe_en = 1, + .oe_inv = 0, + .do_sel = 0, + .do_inv = 0, + .pu = 0, + .pd = 0, + .resv1 = 0, + .sl = 0, + .ie_en = 0, + .ie_inv = 0, + .di_inv = 0, + .st = 0, + .tie_en = 0, + .tie_val = 0, + .resv0 = 0, + .pad_di = 0}, + {.ch_sel = FUNC_DEBUG8, + .ds = 0xf, + .oe_en = 1, + .oe_inv = 0, + .do_sel = 0, + .do_inv = 0, + .pu = 0, + .pd = 0, + .resv1 = 0, + .sl = 0, + .ie_en = 0, + .ie_inv = 0, + .di_inv = 0, + .st = 0, + .tie_en = 0, + .tie_val = 0, + .resv0 = 0, + .pad_di = 0}, + {.ch_sel = FUNC_DEBUG9, + .ds = 0xf, + .oe_en = 1, + .oe_inv = 0, + .do_sel = 0, + .do_inv = 0, + .pu = 0, + .pd = 0, + .resv1 = 0, + .sl = 0, + .ie_en = 0, + .ie_inv = 0, + .di_inv = 0, + .st = 0, + .tie_en = 0, + .tie_val = 0, + .resv0 = 0, + .pad_di = 0}, + {.ch_sel = FUNC_DEBUG10, + .ds = 0xf, + .oe_en = 1, + .oe_inv = 0, + .do_sel = 0, + .do_inv = 0, + .pu = 0, + .pd = 0, + .resv1 = 0, + .sl = 0, + .ie_en = 0, + .ie_inv = 0, + .di_inv = 0, + .st = 0, + .tie_en = 0, + .tie_val = 0, + .resv0 = 0, + .pad_di = 0}, + {.ch_sel = FUNC_DEBUG11, + .ds = 0xf, + .oe_en = 1, + .oe_inv = 0, + .do_sel = 0, + .do_inv = 0, + .pu = 0, + .pd = 0, + .resv1 = 0, + .sl = 0, + .ie_en = 0, + .ie_inv = 0, + .di_inv = 0, + .st = 0, + .tie_en = 0, + .tie_val = 0, + .resv0 = 0, + .pad_di = 0}, + {.ch_sel = FUNC_DEBUG12, + .ds = 0xf, + .oe_en = 1, + .oe_inv = 0, + .do_sel = 0, + .do_inv = 0, + .pu = 0, + .pd = 0, + .resv1 = 0, + .sl = 0, + .ie_en = 0, + .ie_inv = 0, + .di_inv = 0, + .st = 0, + .tie_en = 0, + .tie_val = 0, + .resv0 = 0, + .pad_di = 0}, + {.ch_sel = FUNC_DEBUG13, + .ds = 0xf, + .oe_en = 1, + .oe_inv = 0, + .do_sel = 0, + .do_inv = 0, + .pu = 0, + .pd = 0, + .resv1 = 0, + .sl = 0, + .ie_en = 0, + .ie_inv = 0, + .di_inv = 0, + .st = 0, + .tie_en = 0, + .tie_val = 0, + .resv0 = 0, + .pad_di = 0}, + {.ch_sel = FUNC_DEBUG14, + .ds = 0xf, + .oe_en = 1, + .oe_inv = 0, + .do_sel = 0, + .do_inv = 0, + .pu = 0, + .pd = 0, + .resv1 = 0, + .sl = 0, + .ie_en = 0, + .ie_inv = 0, + .di_inv = 0, + .st = 0, + .tie_en = 0, + .tie_val = 0, + .resv0 = 0, + .pad_di = 0}, + {.ch_sel = FUNC_DEBUG15, + .ds = 0xf, + .oe_en = 1, + .oe_inv = 0, + .do_sel = 0, + .do_inv = 0, + .pu = 0, + .pd = 0, + .resv1 = 0, + .sl = 0, + .ie_en = 0, + .ie_inv = 0, + .di_inv = 0, + .st = 0, + .tie_en = 0, + .tie_val = 0, + .resv0 = 0, + .pad_di = 0}, + {.ch_sel = FUNC_DEBUG16, + .ds = 0xf, + .oe_en = 1, + .oe_inv = 0, + .do_sel = 0, + .do_inv = 0, + .pu = 0, + .pd = 0, + .resv1 = 0, + .sl = 0, + .ie_en = 0, + .ie_inv = 0, + .di_inv = 0, + .st = 0, + .tie_en = 0, + .tie_val = 0, + .resv0 = 0, + .pad_di = 0}, + {.ch_sel = FUNC_DEBUG17, + .ds = 0xf, + .oe_en = 1, + .oe_inv = 0, + .do_sel = 0, + .do_inv = 0, + .pu = 0, + .pd = 0, + .resv1 = 0, + .sl = 0, + .ie_en = 0, + .ie_inv = 0, + .di_inv = 0, + .st = 0, + .tie_en = 0, + .tie_val = 0, + .resv0 = 0, + .pad_di = 0}, + {.ch_sel = FUNC_DEBUG18, + .ds = 0xf, + .oe_en = 1, + .oe_inv = 0, + .do_sel = 0, + .do_inv = 0, + .pu = 0, + .pd = 0, + .resv1 = 0, + .sl = 0, + .ie_en = 0, + .ie_inv = 0, + .di_inv = 0, + .st = 0, + .tie_en = 0, + .tie_val = 0, + .resv0 = 0, + .pad_di = 0}, + {.ch_sel = FUNC_DEBUG19, + .ds = 0xf, + .oe_en = 1, + .oe_inv = 0, + .do_sel = 0, + .do_inv = 0, + .pu = 0, + .pd = 0, + .resv1 = 0, + .sl = 0, + .ie_en = 0, + .ie_inv = 0, + .di_inv = 0, + .st = 0, + .tie_en = 0, + .tie_val = 0, + .resv0 = 0, + .pad_di = 0}, + {.ch_sel = FUNC_DEBUG20, + .ds = 0xf, + .oe_en = 1, + .oe_inv = 0, + .do_sel = 0, + .do_inv = 0, + .pu = 0, + .pd = 0, + .resv1 = 0, + .sl = 0, + .ie_en = 0, + .ie_inv = 0, + .di_inv = 0, + .st = 0, + .tie_en = 0, + .tie_val = 0, + .resv0 = 0, + .pad_di = 0}, + {.ch_sel = FUNC_DEBUG21, + .ds = 0xf, + .oe_en = 1, + .oe_inv = 0, + .do_sel = 0, + .do_inv = 0, + .pu = 0, + .pd = 0, + .resv1 = 0, + .sl = 0, + .ie_en = 0, + .ie_inv = 0, + .di_inv = 0, + .st = 0, + .tie_en = 0, + .tie_val = 0, + .resv0 = 0, + .pad_di = 0}, + {.ch_sel = FUNC_DEBUG22, + .ds = 0xf, + .oe_en = 1, + .oe_inv = 0, + .do_sel = 0, + .do_inv = 0, + .pu = 0, + .pd = 0, + .resv1 = 0, + .sl = 0, + .ie_en = 0, + .ie_inv = 0, + .di_inv = 0, + .st = 0, + .tie_en = 0, + .tie_val = 0, + .resv0 = 0, + .pad_di = 0}, + {.ch_sel = FUNC_DEBUG23, + .ds = 0xf, + .oe_en = 1, + .oe_inv = 0, + .do_sel = 0, + .do_inv = 0, + .pu = 0, + .pd = 0, + .resv1 = 0, + .sl = 0, + .ie_en = 0, + .ie_inv = 0, + .di_inv = 0, + .st = 0, + .tie_en = 0, + .tie_val = 0, + .resv0 = 0, + .pad_di = 0}, + {.ch_sel = FUNC_DEBUG24, + .ds = 0xf, + .oe_en = 1, + .oe_inv = 0, + .do_sel = 0, + .do_inv = 0, + .pu = 0, + .pd = 0, + .resv1 = 0, + .sl = 0, + .ie_en = 0, + .ie_inv = 0, + .di_inv = 0, + .st = 0, + .tie_en = 0, + .tie_val = 0, + .resv0 = 0, + .pad_di = 0}, + {.ch_sel = FUNC_DEBUG25, + .ds = 0xf, + .oe_en = 1, + .oe_inv = 0, + .do_sel = 0, + .do_inv = 0, + .pu = 0, + .pd = 0, + .resv1 = 0, + .sl = 0, + .ie_en = 0, + .ie_inv = 0, + .di_inv = 0, + .st = 0, + .tie_en = 0, + .tie_val = 0, + .resv0 = 0, + .pad_di = 0}, + {.ch_sel = FUNC_DEBUG26, + .ds = 0xf, + .oe_en = 1, + .oe_inv = 0, + .do_sel = 0, + .do_inv = 0, + .pu = 0, + .pd = 0, + .resv1 = 0, + .sl = 0, + .ie_en = 0, + .ie_inv = 0, + .di_inv = 0, + .st = 0, + .tie_en = 0, + .tie_val = 0, + .resv0 = 0, + .pad_di = 0}, + {.ch_sel = FUNC_DEBUG27, + .ds = 0xf, + .oe_en = 1, + .oe_inv = 0, + .do_sel = 0, + .do_inv = 0, + .pu = 0, + .pd = 0, + .resv1 = 0, + .sl = 0, + .ie_en = 0, + .ie_inv = 0, + .di_inv = 0, + .st = 0, + .tie_en = 0, + .tie_val = 0, + .resv0 = 0, + .pad_di = 0}, + {.ch_sel = FUNC_DEBUG28, + .ds = 0xf, + .oe_en = 1, + .oe_inv = 0, + .do_sel = 0, + .do_inv = 0, + .pu = 0, + .pd = 0, + .resv1 = 0, + .sl = 0, + .ie_en = 0, + .ie_inv = 0, + .di_inv = 0, + .st = 0, + .tie_en = 0, + .tie_val = 0, + .resv0 = 0, + .pad_di = 0}, + {.ch_sel = FUNC_DEBUG29, + .ds = 0xf, + .oe_en = 1, + .oe_inv = 0, + .do_sel = 0, + .do_inv = 0, + .pu = 0, + .pd = 0, + .resv1 = 0, + .sl = 0, + .ie_en = 0, + .ie_inv = 0, + .di_inv = 0, + .st = 0, + .tie_en = 0, + .tie_val = 0, + .resv0 = 0, + .pad_di = 0}, + {.ch_sel = FUNC_DEBUG30, + .ds = 0xf, + .oe_en = 1, + .oe_inv = 0, + .do_sel = 0, + .do_inv = 0, + .pu = 0, + .pd = 0, + .resv1 = 0, + .sl = 0, + .ie_en = 0, + .ie_inv = 0, + .di_inv = 0, + .st = 0, + .tie_en = 0, + .tie_val = 0, + .resv0 = 0, + .pad_di = 0}, + {.ch_sel = FUNC_DEBUG31, + .ds = 0xf, + .oe_en = 1, + .oe_inv = 0, + .do_sel = 0, + .do_inv = 0, + .pu = 0, + .pd = 0, + .resv1 = 0, + .sl = 0, + .ie_en = 0, + .ie_inv = 0, + .di_inv = 0, + .st = 0, + .tie_en = 0, + .tie_val = 0, + .resv0 = 0, + .pad_di = 0}, +}; + +int fpioa_init(void) +{ + int i = 0; + + /* Enable fpioa clock in system controller */ + sysctl_clock_enable(SYSCTL_CLOCK_FPIOA); + + /* Initialize tie */ + fpioa_tie_t tie = {0}; + + /* Set tie enable and tie value */ + for(i = 0; i < FUNC_MAX; i++) + { + tie.en[i / 32] |= (function_config[i].tie_en << (i % 32)); + tie.val[i / 32] |= (function_config[i].tie_val << (i % 32)); + } + + /* Atomic write every 32bit register to fpioa function */ + for(i = 0; i < FUNC_MAX / 32; i++) + { + /* Set value before enable */ + fpioa->tie.val[i] = tie.val[i]; + fpioa->tie.en[i] = tie.en[i]; + } + + return 0; +} + +int fpioa_get_io(int number, fpioa_io_config_t *cfg) +{ + /* Check parameters */ + if(number < 0 || number >= FPIOA_NUM_IO || cfg == NULL) + return -1; + /* Atomic read register */ + *cfg = fpioa->io[number]; + return 0; +} + +int fpioa_set_io(int number, fpioa_io_config_t *cfg) +{ + /* Check parameters */ + if(number < 0 || number >= FPIOA_NUM_IO || cfg == NULL) + return -1; + /* Atomic write register */ + fpioa->io[number] = *cfg; + return 0; +} + +int fpioa_set_io_pull(int number, fpioa_pull_t pull) +{ + /* Check parameters */ + if(number < 0 || number >= FPIOA_NUM_IO || pull >= FPIOA_PULL_MAX) + return -1; + + /* Atomic read register */ + fpioa_io_config_t cfg = fpioa->io[number]; + + switch(pull) + { + case FPIOA_PULL_NONE: + cfg.pu = 0; + cfg.pd = 0; + break; + case FPIOA_PULL_DOWN: + cfg.pu = 0; + cfg.pd = 1; + break; + case FPIOA_PULL_UP: + cfg.pu = 1; + cfg.pd = 0; + break; + default: + break; + } + /* Atomic write register */ + fpioa->io[number] = cfg; + return 0; +} + +int fpioa_get_io_pull(int number) +{ + /* Check parameters */ + if(number < 0 || number >= FPIOA_NUM_IO) + return -1; + + fpioa_pull_t pull; + /* Atomic read register */ + fpioa_io_config_t cfg = fpioa->io[number]; + + if(cfg.pu == 0 && cfg.pd == 1) + pull = FPIOA_PULL_DOWN; + else if(cfg.pu == 1 && cfg.pd == 0) + pull = FPIOA_PULL_UP; + else + pull = FPIOA_PULL_NONE; + return pull; +} + +int fpioa_set_io_driving(int number, fpioa_driving_t driving) +{ + /* Check parameters */ + if(number < 0 || number >= FPIOA_NUM_IO || driving >= FPIOA_DRIVING_MAX) + return -1; + + /* Atomic read register */ + fpioa_io_config_t cfg = fpioa->io[number]; + /* Set IO driving */ + cfg.ds = driving; + /* Atomic write register */ + fpioa->io[number] = cfg; + return 0; +} + +int fpioa_set_sl(int number, uint8_t sl_enable) +{ + /* Check parameters */ + if(number < 0 || number >= FPIOA_NUM_IO) + return -1; + + /* Atomic read register */ + fpioa_io_config_t cfg = fpioa->io[number]; + /* Set IO slew rate */ + cfg.sl = sl_enable; + /* Atomic write register */ + fpioa->io[number] = cfg; + return 0; +} + +int fpioa_set_st(int number, uint8_t st_enable) +{ + /* Check parameters */ + if(number < 0 || number >= FPIOA_NUM_IO) + return -1; + + /* Atomic read register */ + fpioa_io_config_t cfg = fpioa->io[number]; + /* Set IO schmitt trigger */ + cfg.st = st_enable; + /* Atomic write register */ + fpioa->io[number] = cfg; + return 0; +} + +int fpioa_set_oe_inv(int number, uint8_t inv_enable) +{ + /* Check parameters */ + if(number < 0 || number >= FPIOA_NUM_IO) + return -1; + + /* Atomic read register */ + fpioa_io_config_t cfg = fpioa->io[number]; + /* Set IO schmitt trigger */ + cfg.oe_inv = inv_enable; + /* Atomic write register */ + fpioa->io[number] = cfg; + return 0; +} + +int fpioa_get_io_driving(int number) +{ + /* Check parameters */ + if(number < 0 || number >= FPIOA_NUM_IO) + return -1; + + return fpioa->io[number].ds; +} + +int fpioa_set_function_raw(int number, fpioa_function_t function) +{ + /* Check parameters */ + if(number < 0 || number >= FPIOA_NUM_IO || function < 0 || function >= FUNC_MAX) + return -1; + /* Atomic write register */ + fpioa->io[number] = (const fpioa_io_config_t){ + .ch_sel = function_config[function].ch_sel, + .ds = function_config[function].ds, + .oe_en = function_config[function].oe_en, + .oe_inv = function_config[function].oe_inv, + .do_sel = function_config[function].do_sel, + .do_inv = function_config[function].do_inv, + .pu = function_config[function].pu, + .pd = function_config[function].pd, + .sl = function_config[function].sl, + .ie_en = function_config[function].ie_en, + .ie_inv = function_config[function].ie_inv, + .di_inv = function_config[function].di_inv, + .st = function_config[function].st, + /* resv and pad_di do not need initialization */ + }; + return 0; +} + +int fpioa_set_function(int number, fpioa_function_t function) +{ + uint8_t index = 0; + /* Check parameters */ + if(number < 0 || number >= FPIOA_NUM_IO || function < 0 || function >= FUNC_MAX) + return -1; + if(function == FUNC_RESV0) + { + fpioa_set_function_raw(number, FUNC_RESV0); + return 0; + } + /* Compare all IO */ + for(index = 0; index < FPIOA_NUM_IO; index++) + { + if((fpioa->io[index].ch_sel == function) && (index != number)) + fpioa_set_function_raw(index, FUNC_RESV0); + } + fpioa_set_function_raw(number, function); + return 0; +} + +int fpioa_set_tie_enable(fpioa_function_t function, int enable) +{ + /* Check parameters */ + if(function < 0 || function >= FUNC_MAX) + return -1; + /* Set tie enable */ + if(enable) + fpioa->tie.en[function / 32] |= (1UL << (function % 32)); + else + fpioa->tie.en[function / 32] &= (~(1UL << (function % 32))); + return 0; +} + +int fpioa_set_tie_value(fpioa_function_t function, int value) +{ + /* Check parameters */ + if(function < 0 || function >= FUNC_MAX) + return -1; + /* Set tie value */ + if(value) + fpioa->tie.val[function / 32] |= (1UL << (function % 32)); + else + fpioa->tie.val[function / 32] &= (~(1UL << (function % 32))); + return 0; +} + +int fpioa_get_io_by_function(fpioa_function_t function) +{ + int index = 0; + for(index = 0; index < FPIOA_NUM_IO; index++) + { + if(fpioa->io[index].ch_sel == function) + return index; + } + + return -1; +} diff --git a/Ubiquitous/Nuttx_Fusion_XiUOS/app_match_nuttx/nuttx/arch/risc-v/src/k210/fpioa.h b/Ubiquitous/Nuttx_Fusion_XiUOS/app_match_nuttx/nuttx/arch/risc-v/src/k210/fpioa.h new file mode 100755 index 000000000..15e86eaea --- /dev/null +++ b/Ubiquitous/Nuttx_Fusion_XiUOS/app_match_nuttx/nuttx/arch/risc-v/src/k210/fpioa.h @@ -0,0 +1,1035 @@ +/* Copyright 2018 Canaan Inc. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +/** + * @file + * @brief Field Programmable GPIO Array (FPIOA) + * + * The FPIOA peripheral supports the following features: + * + * - 48 IO with 256 functions + * + * - Schmitt trigger + * + * - Invert input and output + * + * - Pull up and pull down + * + * - Driving selector + * + * - Static input and output + * + */ + +#ifndef _DRIVER_FPIOA_H +#define _DRIVER_FPIOA_H + +#include +//#include "platform.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/* clang-format off */ +/* Pad number settings */ +#define FPIOA_NUM_IO (48) +/* clang-format on */ + +/** + * @brief FPIOA IO functions + * + * @note FPIOA pin function table + * + * | Function | Name | Description | + * |-----------|------------------|-----------------------------------| + * | 0 | JTAG_TCLK | JTAG Test Clock | + * | 1 | JTAG_TDI | JTAG Test Data In | + * | 2 | JTAG_TMS | JTAG Test Mode Select | + * | 3 | JTAG_TDO | JTAG Test Data Out | + * | 4 | SPI0_D0 | SPI0 Data 0 | + * | 5 | SPI0_D1 | SPI0 Data 1 | + * | 6 | SPI0_D2 | SPI0 Data 2 | + * | 7 | SPI0_D3 | SPI0 Data 3 | + * | 8 | SPI0_D4 | SPI0 Data 4 | + * | 9 | SPI0_D5 | SPI0 Data 5 | + * | 10 | SPI0_D6 | SPI0 Data 6 | + * | 11 | SPI0_D7 | SPI0 Data 7 | + * | 12 | SPI0_SS0 | SPI0 Chip Select 0 | + * | 13 | SPI0_SS1 | SPI0 Chip Select 1 | + * | 14 | SPI0_SS2 | SPI0 Chip Select 2 | + * | 15 | SPI0_SS3 | SPI0 Chip Select 3 | + * | 16 | SPI0_ARB | SPI0 Arbitration | + * | 17 | SPI0_SCLK | SPI0 Serial Clock | + * | 18 | UARTHS_RX | UART High speed Receiver | + * | 19 | UARTHS_TX | UART High speed Transmitter | + * | 20 | RESV6 | Reserved function | + * | 21 | RESV7 | Reserved function | + * | 22 | CLK_SPI1 | Clock SPI1 | + * | 23 | CLK_I2C1 | Clock I2C1 | + * | 24 | GPIOHS0 | GPIO High speed 0 | + * | 25 | GPIOHS1 | GPIO High speed 1 | + * | 26 | GPIOHS2 | GPIO High speed 2 | + * | 27 | GPIOHS3 | GPIO High speed 3 | + * | 28 | GPIOHS4 | GPIO High speed 4 | + * | 29 | GPIOHS5 | GPIO High speed 5 | + * | 30 | GPIOHS6 | GPIO High speed 6 | + * | 31 | GPIOHS7 | GPIO High speed 7 | + * | 32 | GPIOHS8 | GPIO High speed 8 | + * | 33 | GPIOHS9 | GPIO High speed 9 | + * | 34 | GPIOHS10 | GPIO High speed 10 | + * | 35 | GPIOHS11 | GPIO High speed 11 | + * | 36 | GPIOHS12 | GPIO High speed 12 | + * | 37 | GPIOHS13 | GPIO High speed 13 | + * | 38 | GPIOHS14 | GPIO High speed 14 | + * | 39 | GPIOHS15 | GPIO High speed 15 | + * | 40 | GPIOHS16 | GPIO High speed 16 | + * | 41 | GPIOHS17 | GPIO High speed 17 | + * | 42 | GPIOHS18 | GPIO High speed 18 | + * | 43 | GPIOHS19 | GPIO High speed 19 | + * | 44 | GPIOHS20 | GPIO High speed 20 | + * | 45 | GPIOHS21 | GPIO High speed 21 | + * | 46 | GPIOHS22 | GPIO High speed 22 | + * | 47 | GPIOHS23 | GPIO High speed 23 | + * | 48 | GPIOHS24 | GPIO High speed 24 | + * | 49 | GPIOHS25 | GPIO High speed 25 | + * | 50 | GPIOHS26 | GPIO High speed 26 | + * | 51 | GPIOHS27 | GPIO High speed 27 | + * | 52 | GPIOHS28 | GPIO High speed 28 | + * | 53 | GPIOHS29 | GPIO High speed 29 | + * | 54 | GPIOHS30 | GPIO High speed 30 | + * | 55 | GPIOHS31 | GPIO High speed 31 | + * | 56 | GPIO0 | GPIO pin 0 | + * | 57 | GPIO1 | GPIO pin 1 | + * | 58 | GPIO2 | GPIO pin 2 | + * | 59 | GPIO3 | GPIO pin 3 | + * | 60 | GPIO4 | GPIO pin 4 | + * | 61 | GPIO5 | GPIO pin 5 | + * | 62 | GPIO6 | GPIO pin 6 | + * | 63 | GPIO7 | GPIO pin 7 | + * | 64 | UART1_RX | UART1 Receiver | + * | 65 | UART1_TX | UART1 Transmitter | + * | 66 | UART2_RX | UART2 Receiver | + * | 67 | UART2_TX | UART2 Transmitter | + * | 68 | UART3_RX | UART3 Receiver | + * | 69 | UART3_TX | UART3 Transmitter | + * | 70 | SPI1_D0 | SPI1 Data 0 | + * | 71 | SPI1_D1 | SPI1 Data 1 | + * | 72 | SPI1_D2 | SPI1 Data 2 | + * | 73 | SPI1_D3 | SPI1 Data 3 | + * | 74 | SPI1_D4 | SPI1 Data 4 | + * | 75 | SPI1_D5 | SPI1 Data 5 | + * | 76 | SPI1_D6 | SPI1 Data 6 | + * | 77 | SPI1_D7 | SPI1 Data 7 | + * | 78 | SPI1_SS0 | SPI1 Chip Select 0 | + * | 79 | SPI1_SS1 | SPI1 Chip Select 1 | + * | 80 | SPI1_SS2 | SPI1 Chip Select 2 | + * | 81 | SPI1_SS3 | SPI1 Chip Select 3 | + * | 82 | SPI1_ARB | SPI1 Arbitration | + * | 83 | SPI1_SCLK | SPI1 Serial Clock | + * | 84 | SPI_SLAVE_D0 | SPI Slave Data 0 | + * | 85 | SPI_SLAVE_SS | SPI Slave Select | + * | 86 | SPI_SLAVE_SCLK | SPI Slave Serial Clock | + * | 87 | I2S0_MCLK | I2S0 Master Clock | + * | 88 | I2S0_SCLK | I2S0 Serial Clock(BCLK) | + * | 89 | I2S0_WS | I2S0 Word Select(LRCLK) | + * | 90 | I2S0_IN_D0 | I2S0 Serial Data Input 0 | + * | 91 | I2S0_IN_D1 | I2S0 Serial Data Input 1 | + * | 92 | I2S0_IN_D2 | I2S0 Serial Data Input 2 | + * | 93 | I2S0_IN_D3 | I2S0 Serial Data Input 3 | + * | 94 | I2S0_OUT_D0 | I2S0 Serial Data Output 0 | + * | 95 | I2S0_OUT_D1 | I2S0 Serial Data Output 1 | + * | 96 | I2S0_OUT_D2 | I2S0 Serial Data Output 2 | + * | 97 | I2S0_OUT_D3 | I2S0 Serial Data Output 3 | + * | 98 | I2S1_MCLK | I2S1 Master Clock | + * | 99 | I2S1_SCLK | I2S1 Serial Clock(BCLK) | + * | 100 | I2S1_WS | I2S1 Word Select(LRCLK) | + * | 101 | I2S1_IN_D0 | I2S1 Serial Data Input 0 | + * | 102 | I2S1_IN_D1 | I2S1 Serial Data Input 1 | + * | 103 | I2S1_IN_D2 | I2S1 Serial Data Input 2 | + * | 104 | I2S1_IN_D3 | I2S1 Serial Data Input 3 | + * | 105 | I2S1_OUT_D0 | I2S1 Serial Data Output 0 | + * | 106 | I2S1_OUT_D1 | I2S1 Serial Data Output 1 | + * | 107 | I2S1_OUT_D2 | I2S1 Serial Data Output 2 | + * | 108 | I2S1_OUT_D3 | I2S1 Serial Data Output 3 | + * | 109 | I2S2_MCLK | I2S2 Master Clock | + * | 110 | I2S2_SCLK | I2S2 Serial Clock(BCLK) | + * | 111 | I2S2_WS | I2S2 Word Select(LRCLK) | + * | 112 | I2S2_IN_D0 | I2S2 Serial Data Input 0 | + * | 113 | I2S2_IN_D1 | I2S2 Serial Data Input 1 | + * | 114 | I2S2_IN_D2 | I2S2 Serial Data Input 2 | + * | 115 | I2S2_IN_D3 | I2S2 Serial Data Input 3 | + * | 116 | I2S2_OUT_D0 | I2S2 Serial Data Output 0 | + * | 117 | I2S2_OUT_D1 | I2S2 Serial Data Output 1 | + * | 118 | I2S2_OUT_D2 | I2S2 Serial Data Output 2 | + * | 119 | I2S2_OUT_D3 | I2S2 Serial Data Output 3 | + * | 120 | RESV0 | Reserved function | + * | 121 | RESV1 | Reserved function | + * | 122 | RESV2 | Reserved function | + * | 123 | RESV3 | Reserved function | + * | 124 | RESV4 | Reserved function | + * | 125 | RESV5 | Reserved function | + * | 126 | I2C0_SCLK | I2C0 Serial Clock | + * | 127 | I2C0_SDA | I2C0 Serial Data | + * | 128 | I2C1_SCLK | I2C1 Serial Clock | + * | 129 | I2C1_SDA | I2C1 Serial Data | + * | 130 | I2C2_SCLK | I2C2 Serial Clock | + * | 131 | I2C2_SDA | I2C2 Serial Data | + * | 132 | CMOS_XCLK | DVP System Clock | + * | 133 | CMOS_RST | DVP System Reset | + * | 134 | CMOS_PWDN | DVP Power Down Mode | + * | 135 | CMOS_VSYNC | DVP Vertical Sync | + * | 136 | CMOS_HREF | DVP Horizontal Reference output | + * | 137 | CMOS_PCLK | Pixel Clock | + * | 138 | CMOS_D0 | Data Bit 0 | + * | 139 | CMOS_D1 | Data Bit 1 | + * | 140 | CMOS_D2 | Data Bit 2 | + * | 141 | CMOS_D3 | Data Bit 3 | + * | 142 | CMOS_D4 | Data Bit 4 | + * | 143 | CMOS_D5 | Data Bit 5 | + * | 144 | CMOS_D6 | Data Bit 6 | + * | 145 | CMOS_D7 | Data Bit 7 | + * | 146 | SCCB_SCLK | SCCB Serial Clock | + * | 147 | SCCB_SDA | SCCB Serial Data | + * | 148 | UART1_CTS | UART1 Clear To Send | + * | 149 | UART1_DSR | UART1 Data Set Ready | + * | 150 | UART1_DCD | UART1 Data Carrier Detect | + * | 151 | UART1_RI | UART1 Ring Indicator | + * | 152 | UART1_SIR_IN | UART1 Serial Infrared Input | + * | 153 | UART1_DTR | UART1 Data Terminal Ready | + * | 154 | UART1_RTS | UART1 Request To Send | + * | 155 | UART1_OUT2 | UART1 User-designated Output 2 | + * | 156 | UART1_OUT1 | UART1 User-designated Output 1 | + * | 157 | UART1_SIR_OUT | UART1 Serial Infrared Output | + * | 158 | UART1_BAUD | UART1 Transmit Clock Output | + * | 159 | UART1_RE | UART1 Receiver Output Enable | + * | 160 | UART1_DE | UART1 Driver Output Enable | + * | 161 | UART1_RS485_EN | UART1 RS485 Enable | + * | 162 | UART2_CTS | UART2 Clear To Send | + * | 163 | UART2_DSR | UART2 Data Set Ready | + * | 164 | UART2_DCD | UART2 Data Carrier Detect | + * | 165 | UART2_RI | UART2 Ring Indicator | + * | 166 | UART2_SIR_IN | UART2 Serial Infrared Input | + * | 167 | UART2_DTR | UART2 Data Terminal Ready | + * | 168 | UART2_RTS | UART2 Request To Send | + * | 169 | UART2_OUT2 | UART2 User-designated Output 2 | + * | 170 | UART2_OUT1 | UART2 User-designated Output 1 | + * | 171 | UART2_SIR_OUT | UART2 Serial Infrared Output | + * | 172 | UART2_BAUD | UART2 Transmit Clock Output | + * | 173 | UART2_RE | UART2 Receiver Output Enable | + * | 174 | UART2_DE | UART2 Driver Output Enable | + * | 175 | UART2_RS485_EN | UART2 RS485 Enable | + * | 176 | UART3_CTS | UART3 Clear To Send | + * | 177 | UART3_DSR | UART3 Data Set Ready | + * | 178 | UART3_DCD | UART3 Data Carrier Detect | + * | 179 | UART3_RI | UART3 Ring Indicator | + * | 180 | UART3_SIR_IN | UART3 Serial Infrared Input | + * | 181 | UART3_DTR | UART3 Data Terminal Ready | + * | 182 | UART3_RTS | UART3 Request To Send | + * | 183 | UART3_OUT2 | UART3 User-designated Output 2 | + * | 184 | UART3_OUT1 | UART3 User-designated Output 1 | + * | 185 | UART3_SIR_OUT | UART3 Serial Infrared Output | + * | 186 | UART3_BAUD | UART3 Transmit Clock Output | + * | 187 | UART3_RE | UART3 Receiver Output Enable | + * | 188 | UART3_DE | UART3 Driver Output Enable | + * | 189 | UART3_RS485_EN | UART3 RS485 Enable | + * | 190 | TIMER0_TOGGLE1 | TIMER0 Toggle Output 1 | + * | 191 | TIMER0_TOGGLE2 | TIMER0 Toggle Output 2 | + * | 192 | TIMER0_TOGGLE3 | TIMER0 Toggle Output 3 | + * | 193 | TIMER0_TOGGLE4 | TIMER0 Toggle Output 4 | + * | 194 | TIMER1_TOGGLE1 | TIMER1 Toggle Output 1 | + * | 195 | TIMER1_TOGGLE2 | TIMER1 Toggle Output 2 | + * | 196 | TIMER1_TOGGLE3 | TIMER1 Toggle Output 3 | + * | 197 | TIMER1_TOGGLE4 | TIMER1 Toggle Output 4 | + * | 198 | TIMER2_TOGGLE1 | TIMER2 Toggle Output 1 | + * | 199 | TIMER2_TOGGLE2 | TIMER2 Toggle Output 2 | + * | 200 | TIMER2_TOGGLE3 | TIMER2 Toggle Output 3 | + * | 201 | TIMER2_TOGGLE4 | TIMER2 Toggle Output 4 | + * | 202 | CLK_SPI2 | Clock SPI2 | + * | 203 | CLK_I2C2 | Clock I2C2 | + * | 204 | INTERNAL0 | Internal function signal 0 | + * | 205 | INTERNAL1 | Internal function signal 1 | + * | 206 | INTERNAL2 | Internal function signal 2 | + * | 207 | INTERNAL3 | Internal function signal 3 | + * | 208 | INTERNAL4 | Internal function signal 4 | + * | 209 | INTERNAL5 | Internal function signal 5 | + * | 210 | INTERNAL6 | Internal function signal 6 | + * | 211 | INTERNAL7 | Internal function signal 7 | + * | 212 | INTERNAL8 | Internal function signal 8 | + * | 213 | INTERNAL9 | Internal function signal 9 | + * | 214 | INTERNAL10 | Internal function signal 10 | + * | 215 | INTERNAL11 | Internal function signal 11 | + * | 216 | INTERNAL12 | Internal function signal 12 | + * | 217 | INTERNAL13 | Internal function signal 13 | + * | 218 | INTERNAL14 | Internal function signal 14 | + * | 219 | INTERNAL15 | Internal function signal 15 | + * | 220 | INTERNAL16 | Internal function signal 16 | + * | 221 | INTERNAL17 | Internal function signal 17 | + * | 222 | CONSTANT | Constant function | + * | 223 | INTERNAL18 | Internal function signal 18 | + * | 224 | DEBUG0 | Debug function 0 | + * | 225 | DEBUG1 | Debug function 1 | + * | 226 | DEBUG2 | Debug function 2 | + * | 227 | DEBUG3 | Debug function 3 | + * | 228 | DEBUG4 | Debug function 4 | + * | 229 | DEBUG5 | Debug function 5 | + * | 230 | DEBUG6 | Debug function 6 | + * | 231 | DEBUG7 | Debug function 7 | + * | 232 | DEBUG8 | Debug function 8 | + * | 233 | DEBUG9 | Debug function 9 | + * | 234 | DEBUG10 | Debug function 10 | + * | 235 | DEBUG11 | Debug function 11 | + * | 236 | DEBUG12 | Debug function 12 | + * | 237 | DEBUG13 | Debug function 13 | + * | 238 | DEBUG14 | Debug function 14 | + * | 239 | DEBUG15 | Debug function 15 | + * | 240 | DEBUG16 | Debug function 16 | + * | 241 | DEBUG17 | Debug function 17 | + * | 242 | DEBUG18 | Debug function 18 | + * | 243 | DEBUG19 | Debug function 19 | + * | 244 | DEBUG20 | Debug function 20 | + * | 245 | DEBUG21 | Debug function 21 | + * | 246 | DEBUG22 | Debug function 22 | + * | 247 | DEBUG23 | Debug function 23 | + * | 248 | DEBUG24 | Debug function 24 | + * | 249 | DEBUG25 | Debug function 25 | + * | 250 | DEBUG26 | Debug function 26 | + * | 251 | DEBUG27 | Debug function 27 | + * | 252 | DEBUG28 | Debug function 28 | + * | 253 | DEBUG29 | Debug function 29 | + * | 254 | DEBUG30 | Debug function 30 | + * | 255 | DEBUG31 | Debug function 31 | + * + * Any IO of FPIOA have 256 functions, it is a IO-function matrix. + * All IO have default reset function, after reset, re-configure + * IO function is required. + */ + +/* clang-format off */ +typedef enum _fpioa_function +{ + FUNC_JTAG_TCLK = 0, /*!< JTAG Test Clock */ + FUNC_JTAG_TDI = 1, /*!< JTAG Test Data In */ + FUNC_JTAG_TMS = 2, /*!< JTAG Test Mode Select */ + FUNC_JTAG_TDO = 3, /*!< JTAG Test Data Out */ + FUNC_SPI0_D0 = 4, /*!< SPI0 Data 0 */ + FUNC_SPI0_D1 = 5, /*!< SPI0 Data 1 */ + FUNC_SPI0_D2 = 6, /*!< SPI0 Data 2 */ + FUNC_SPI0_D3 = 7, /*!< SPI0 Data 3 */ + FUNC_SPI0_D4 = 8, /*!< SPI0 Data 4 */ + FUNC_SPI0_D5 = 9, /*!< SPI0 Data 5 */ + FUNC_SPI0_D6 = 10, /*!< SPI0 Data 6 */ + FUNC_SPI0_D7 = 11, /*!< SPI0 Data 7 */ + FUNC_SPI0_SS0 = 12, /*!< SPI0 Chip Select 0 */ + FUNC_SPI0_SS1 = 13, /*!< SPI0 Chip Select 1 */ + FUNC_SPI0_SS2 = 14, /*!< SPI0 Chip Select 2 */ + FUNC_SPI0_SS3 = 15, /*!< SPI0 Chip Select 3 */ + FUNC_SPI0_ARB = 16, /*!< SPI0 Arbitration */ + FUNC_SPI0_SCLK = 17, /*!< SPI0 Serial Clock */ + FUNC_UARTHS_RX = 18, /*!< UART High speed Receiver */ + FUNC_UARTHS_TX = 19, /*!< UART High speed Transmitter */ + FUNC_RESV6 = 20, /*!< Reserved function */ + FUNC_RESV7 = 21, /*!< Reserved function */ + FUNC_CLK_SPI1 = 22, /*!< Clock SPI1 */ + FUNC_CLK_I2C1 = 23, /*!< Clock I2C1 */ + FUNC_GPIOHS0 = 24, /*!< GPIO High speed 0 */ + FUNC_GPIOHS1 = 25, /*!< GPIO High speed 1 */ + FUNC_GPIOHS2 = 26, /*!< GPIO High speed 2 */ + FUNC_GPIOHS3 = 27, /*!< GPIO High speed 3 */ + FUNC_GPIOHS4 = 28, /*!< GPIO High speed 4 */ + FUNC_GPIOHS5 = 29, /*!< GPIO High speed 5 */ + FUNC_GPIOHS6 = 30, /*!< GPIO High speed 6 */ + FUNC_GPIOHS7 = 31, /*!< GPIO High speed 7 */ + FUNC_GPIOHS8 = 32, /*!< GPIO High speed 8 */ + FUNC_GPIOHS9 = 33, /*!< GPIO High speed 9 */ + FUNC_GPIOHS10 = 34, /*!< GPIO High speed 10 */ + FUNC_GPIOHS11 = 35, /*!< GPIO High speed 11 */ + FUNC_GPIOHS12 = 36, /*!< GPIO High speed 12 */ + FUNC_GPIOHS13 = 37, /*!< GPIO High speed 13 */ + FUNC_GPIOHS14 = 38, /*!< GPIO High speed 14 */ + FUNC_GPIOHS15 = 39, /*!< GPIO High speed 15 */ + FUNC_GPIOHS16 = 40, /*!< GPIO High speed 16 */ + FUNC_GPIOHS17 = 41, /*!< GPIO High speed 17 */ + FUNC_GPIOHS18 = 42, /*!< GPIO High speed 18 */ + FUNC_GPIOHS19 = 43, /*!< GPIO High speed 19 */ + FUNC_GPIOHS20 = 44, /*!< GPIO High speed 20 */ + FUNC_GPIOHS21 = 45, /*!< GPIO High speed 21 */ + FUNC_GPIOHS22 = 46, /*!< GPIO High speed 22 */ + FUNC_GPIOHS23 = 47, /*!< GPIO High speed 23 */ + FUNC_GPIOHS24 = 48, /*!< GPIO High speed 24 */ + FUNC_GPIOHS25 = 49, /*!< GPIO High speed 25 */ + FUNC_GPIOHS26 = 50, /*!< GPIO High speed 26 */ + FUNC_GPIOHS27 = 51, /*!< GPIO High speed 27 */ + FUNC_GPIOHS28 = 52, /*!< GPIO High speed 28 */ + FUNC_GPIOHS29 = 53, /*!< GPIO High speed 29 */ + FUNC_GPIOHS30 = 54, /*!< GPIO High speed 30 */ + FUNC_GPIOHS31 = 55, /*!< GPIO High speed 31 */ + FUNC_GPIO0 = 56, /*!< GPIO pin 0 */ + FUNC_GPIO1 = 57, /*!< GPIO pin 1 */ + FUNC_GPIO2 = 58, /*!< GPIO pin 2 */ + FUNC_GPIO3 = 59, /*!< GPIO pin 3 */ + FUNC_GPIO4 = 60, /*!< GPIO pin 4 */ + FUNC_GPIO5 = 61, /*!< GPIO pin 5 */ + FUNC_GPIO6 = 62, /*!< GPIO pin 6 */ + FUNC_GPIO7 = 63, /*!< GPIO pin 7 */ + FUNC_UART1_RX = 64, /*!< UART1 Receiver */ + FUNC_UART1_TX = 65, /*!< UART1 Transmitter */ + FUNC_UART2_RX = 66, /*!< UART2 Receiver */ + FUNC_UART2_TX = 67, /*!< UART2 Transmitter */ + FUNC_UART3_RX = 68, /*!< UART3 Receiver */ + FUNC_UART3_TX = 69, /*!< UART3 Transmitter */ + FUNC_SPI1_D0 = 70, /*!< SPI1 Data 0 */ + FUNC_SPI1_D1 = 71, /*!< SPI1 Data 1 */ + FUNC_SPI1_D2 = 72, /*!< SPI1 Data 2 */ + FUNC_SPI1_D3 = 73, /*!< SPI1 Data 3 */ + FUNC_SPI1_D4 = 74, /*!< SPI1 Data 4 */ + FUNC_SPI1_D5 = 75, /*!< SPI1 Data 5 */ + FUNC_SPI1_D6 = 76, /*!< SPI1 Data 6 */ + FUNC_SPI1_D7 = 77, /*!< SPI1 Data 7 */ + FUNC_SPI1_SS0 = 78, /*!< SPI1 Chip Select 0 */ + FUNC_SPI1_SS1 = 79, /*!< SPI1 Chip Select 1 */ + FUNC_SPI1_SS2 = 80, /*!< SPI1 Chip Select 2 */ + FUNC_SPI1_SS3 = 81, /*!< SPI1 Chip Select 3 */ + FUNC_SPI1_ARB = 82, /*!< SPI1 Arbitration */ + FUNC_SPI1_SCLK = 83, /*!< SPI1 Serial Clock */ + FUNC_SPI_SLAVE_D0 = 84, /*!< SPI Slave Data 0 */ + FUNC_SPI_SLAVE_SS = 85, /*!< SPI Slave Select */ + FUNC_SPI_SLAVE_SCLK = 86, /*!< SPI Slave Serial Clock */ + FUNC_I2S0_MCLK = 87, /*!< I2S0 Master Clock */ + FUNC_I2S0_SCLK = 88, /*!< I2S0 Serial Clock(BCLK) */ + FUNC_I2S0_WS = 89, /*!< I2S0 Word Select(LRCLK) */ + FUNC_I2S0_IN_D0 = 90, /*!< I2S0 Serial Data Input 0 */ + FUNC_I2S0_IN_D1 = 91, /*!< I2S0 Serial Data Input 1 */ + FUNC_I2S0_IN_D2 = 92, /*!< I2S0 Serial Data Input 2 */ + FUNC_I2S0_IN_D3 = 93, /*!< I2S0 Serial Data Input 3 */ + FUNC_I2S0_OUT_D0 = 94, /*!< I2S0 Serial Data Output 0 */ + FUNC_I2S0_OUT_D1 = 95, /*!< I2S0 Serial Data Output 1 */ + FUNC_I2S0_OUT_D2 = 96, /*!< I2S0 Serial Data Output 2 */ + FUNC_I2S0_OUT_D3 = 97, /*!< I2S0 Serial Data Output 3 */ + FUNC_I2S1_MCLK = 98, /*!< I2S1 Master Clock */ + FUNC_I2S1_SCLK = 99, /*!< I2S1 Serial Clock(BCLK) */ + FUNC_I2S1_WS = 100, /*!< I2S1 Word Select(LRCLK) */ + FUNC_I2S1_IN_D0 = 101, /*!< I2S1 Serial Data Input 0 */ + FUNC_I2S1_IN_D1 = 102, /*!< I2S1 Serial Data Input 1 */ + FUNC_I2S1_IN_D2 = 103, /*!< I2S1 Serial Data Input 2 */ + FUNC_I2S1_IN_D3 = 104, /*!< I2S1 Serial Data Input 3 */ + FUNC_I2S1_OUT_D0 = 105, /*!< I2S1 Serial Data Output 0 */ + FUNC_I2S1_OUT_D1 = 106, /*!< I2S1 Serial Data Output 1 */ + FUNC_I2S1_OUT_D2 = 107, /*!< I2S1 Serial Data Output 2 */ + FUNC_I2S1_OUT_D3 = 108, /*!< I2S1 Serial Data Output 3 */ + FUNC_I2S2_MCLK = 109, /*!< I2S2 Master Clock */ + FUNC_I2S2_SCLK = 110, /*!< I2S2 Serial Clock(BCLK) */ + FUNC_I2S2_WS = 111, /*!< I2S2 Word Select(LRCLK) */ + FUNC_I2S2_IN_D0 = 112, /*!< I2S2 Serial Data Input 0 */ + FUNC_I2S2_IN_D1 = 113, /*!< I2S2 Serial Data Input 1 */ + FUNC_I2S2_IN_D2 = 114, /*!< I2S2 Serial Data Input 2 */ + FUNC_I2S2_IN_D3 = 115, /*!< I2S2 Serial Data Input 3 */ + FUNC_I2S2_OUT_D0 = 116, /*!< I2S2 Serial Data Output 0 */ + FUNC_I2S2_OUT_D1 = 117, /*!< I2S2 Serial Data Output 1 */ + FUNC_I2S2_OUT_D2 = 118, /*!< I2S2 Serial Data Output 2 */ + FUNC_I2S2_OUT_D3 = 119, /*!< I2S2 Serial Data Output 3 */ + FUNC_RESV0 = 120, /*!< Reserved function */ + FUNC_RESV1 = 121, /*!< Reserved function */ + FUNC_RESV2 = 122, /*!< Reserved function */ + FUNC_RESV3 = 123, /*!< Reserved function */ + FUNC_RESV4 = 124, /*!< Reserved function */ + FUNC_RESV5 = 125, /*!< Reserved function */ + FUNC_I2C0_SCLK = 126, /*!< I2C0 Serial Clock */ + FUNC_I2C0_SDA = 127, /*!< I2C0 Serial Data */ + FUNC_I2C1_SCLK = 128, /*!< I2C1 Serial Clock */ + FUNC_I2C1_SDA = 129, /*!< I2C1 Serial Data */ + FUNC_I2C2_SCLK = 130, /*!< I2C2 Serial Clock */ + FUNC_I2C2_SDA = 131, /*!< I2C2 Serial Data */ + FUNC_CMOS_XCLK = 132, /*!< DVP System Clock */ + FUNC_CMOS_RST = 133, /*!< DVP System Reset */ + FUNC_CMOS_PWDN = 134, /*!< DVP Power Down Mode */ + FUNC_CMOS_VSYNC = 135, /*!< DVP Vertical Sync */ + FUNC_CMOS_HREF = 136, /*!< DVP Horizontal Reference output */ + FUNC_CMOS_PCLK = 137, /*!< Pixel Clock */ + FUNC_CMOS_D0 = 138, /*!< Data Bit 0 */ + FUNC_CMOS_D1 = 139, /*!< Data Bit 1 */ + FUNC_CMOS_D2 = 140, /*!< Data Bit 2 */ + FUNC_CMOS_D3 = 141, /*!< Data Bit 3 */ + FUNC_CMOS_D4 = 142, /*!< Data Bit 4 */ + FUNC_CMOS_D5 = 143, /*!< Data Bit 5 */ + FUNC_CMOS_D6 = 144, /*!< Data Bit 6 */ + FUNC_CMOS_D7 = 145, /*!< Data Bit 7 */ + FUNC_SCCB_SCLK = 146, /*!< SCCB Serial Clock */ + FUNC_SCCB_SDA = 147, /*!< SCCB Serial Data */ + FUNC_UART1_CTS = 148, /*!< UART1 Clear To Send */ + FUNC_UART1_DSR = 149, /*!< UART1 Data Set Ready */ + FUNC_UART1_DCD = 150, /*!< UART1 Data Carrier Detect */ + FUNC_UART1_RI = 151, /*!< UART1 Ring Indicator */ + FUNC_UART1_SIR_IN = 152, /*!< UART1 Serial Infrared Input */ + FUNC_UART1_DTR = 153, /*!< UART1 Data Terminal Ready */ + FUNC_UART1_RTS = 154, /*!< UART1 Request To Send */ + FUNC_UART1_OUT2 = 155, /*!< UART1 User-designated Output 2 */ + FUNC_UART1_OUT1 = 156, /*!< UART1 User-designated Output 1 */ + FUNC_UART1_SIR_OUT = 157, /*!< UART1 Serial Infrared Output */ + FUNC_UART1_BAUD = 158, /*!< UART1 Transmit Clock Output */ + FUNC_UART1_RE = 159, /*!< UART1 Receiver Output Enable */ + FUNC_UART1_DE = 160, /*!< UART1 Driver Output Enable */ + FUNC_UART1_RS485_EN = 161, /*!< UART1 RS485 Enable */ + FUNC_UART2_CTS = 162, /*!< UART2 Clear To Send */ + FUNC_UART2_DSR = 163, /*!< UART2 Data Set Ready */ + FUNC_UART2_DCD = 164, /*!< UART2 Data Carrier Detect */ + FUNC_UART2_RI = 165, /*!< UART2 Ring Indicator */ + FUNC_UART2_SIR_IN = 166, /*!< UART2 Serial Infrared Input */ + FUNC_UART2_DTR = 167, /*!< UART2 Data Terminal Ready */ + FUNC_UART2_RTS = 168, /*!< UART2 Request To Send */ + FUNC_UART2_OUT2 = 169, /*!< UART2 User-designated Output 2 */ + FUNC_UART2_OUT1 = 170, /*!< UART2 User-designated Output 1 */ + FUNC_UART2_SIR_OUT = 171, /*!< UART2 Serial Infrared Output */ + FUNC_UART2_BAUD = 172, /*!< UART2 Transmit Clock Output */ + FUNC_UART2_RE = 173, /*!< UART2 Receiver Output Enable */ + FUNC_UART2_DE = 174, /*!< UART2 Driver Output Enable */ + FUNC_UART2_RS485_EN = 175, /*!< UART2 RS485 Enable */ + FUNC_UART3_CTS = 176, /*!< UART3 Clear To Send */ + FUNC_UART3_DSR = 177, /*!< UART3 Data Set Ready */ + FUNC_UART3_DCD = 178, /*!< UART3 Data Carrier Detect */ + FUNC_UART3_RI = 179, /*!< UART3 Ring Indicator */ + FUNC_UART3_SIR_IN = 180, /*!< UART3 Serial Infrared Input */ + FUNC_UART3_DTR = 181, /*!< UART3 Data Terminal Ready */ + FUNC_UART3_RTS = 182, /*!< UART3 Request To Send */ + FUNC_UART3_OUT2 = 183, /*!< UART3 User-designated Output 2 */ + FUNC_UART3_OUT1 = 184, /*!< UART3 User-designated Output 1 */ + FUNC_UART3_SIR_OUT = 185, /*!< UART3 Serial Infrared Output */ + FUNC_UART3_BAUD = 186, /*!< UART3 Transmit Clock Output */ + FUNC_UART3_RE = 187, /*!< UART3 Receiver Output Enable */ + FUNC_UART3_DE = 188, /*!< UART3 Driver Output Enable */ + FUNC_UART3_RS485_EN = 189, /*!< UART3 RS485 Enable */ + FUNC_TIMER0_TOGGLE1 = 190, /*!< TIMER0 Toggle Output 1 */ + FUNC_TIMER0_TOGGLE2 = 191, /*!< TIMER0 Toggle Output 2 */ + FUNC_TIMER0_TOGGLE3 = 192, /*!< TIMER0 Toggle Output 3 */ + FUNC_TIMER0_TOGGLE4 = 193, /*!< TIMER0 Toggle Output 4 */ + FUNC_TIMER1_TOGGLE1 = 194, /*!< TIMER1 Toggle Output 1 */ + FUNC_TIMER1_TOGGLE2 = 195, /*!< TIMER1 Toggle Output 2 */ + FUNC_TIMER1_TOGGLE3 = 196, /*!< TIMER1 Toggle Output 3 */ + FUNC_TIMER1_TOGGLE4 = 197, /*!< TIMER1 Toggle Output 4 */ + FUNC_TIMER2_TOGGLE1 = 198, /*!< TIMER2 Toggle Output 1 */ + FUNC_TIMER2_TOGGLE2 = 199, /*!< TIMER2 Toggle Output 2 */ + FUNC_TIMER2_TOGGLE3 = 200, /*!< TIMER2 Toggle Output 3 */ + FUNC_TIMER2_TOGGLE4 = 201, /*!< TIMER2 Toggle Output 4 */ + FUNC_CLK_SPI2 = 202, /*!< Clock SPI2 */ + FUNC_CLK_I2C2 = 203, /*!< Clock I2C2 */ + FUNC_INTERNAL0 = 204, /*!< Internal function signal 0 */ + FUNC_INTERNAL1 = 205, /*!< Internal function signal 1 */ + FUNC_INTERNAL2 = 206, /*!< Internal function signal 2 */ + FUNC_INTERNAL3 = 207, /*!< Internal function signal 3 */ + FUNC_INTERNAL4 = 208, /*!< Internal function signal 4 */ + FUNC_INTERNAL5 = 209, /*!< Internal function signal 5 */ + FUNC_INTERNAL6 = 210, /*!< Internal function signal 6 */ + FUNC_INTERNAL7 = 211, /*!< Internal function signal 7 */ + FUNC_INTERNAL8 = 212, /*!< Internal function signal 8 */ + FUNC_INTERNAL9 = 213, /*!< Internal function signal 9 */ + FUNC_INTERNAL10 = 214, /*!< Internal function signal 10 */ + FUNC_INTERNAL11 = 215, /*!< Internal function signal 11 */ + FUNC_INTERNAL12 = 216, /*!< Internal function signal 12 */ + FUNC_INTERNAL13 = 217, /*!< Internal function signal 13 */ + FUNC_INTERNAL14 = 218, /*!< Internal function signal 14 */ + FUNC_INTERNAL15 = 219, /*!< Internal function signal 15 */ + FUNC_INTERNAL16 = 220, /*!< Internal function signal 16 */ + FUNC_INTERNAL17 = 221, /*!< Internal function signal 17 */ + FUNC_CONSTANT = 222, /*!< Constant function */ + FUNC_INTERNAL18 = 223, /*!< Internal function signal 18 */ + FUNC_DEBUG0 = 224, /*!< Debug function 0 */ + FUNC_DEBUG1 = 225, /*!< Debug function 1 */ + FUNC_DEBUG2 = 226, /*!< Debug function 2 */ + FUNC_DEBUG3 = 227, /*!< Debug function 3 */ + FUNC_DEBUG4 = 228, /*!< Debug function 4 */ + FUNC_DEBUG5 = 229, /*!< Debug function 5 */ + FUNC_DEBUG6 = 230, /*!< Debug function 6 */ + FUNC_DEBUG7 = 231, /*!< Debug function 7 */ + FUNC_DEBUG8 = 232, /*!< Debug function 8 */ + FUNC_DEBUG9 = 233, /*!< Debug function 9 */ + FUNC_DEBUG10 = 234, /*!< Debug function 10 */ + FUNC_DEBUG11 = 235, /*!< Debug function 11 */ + FUNC_DEBUG12 = 236, /*!< Debug function 12 */ + FUNC_DEBUG13 = 237, /*!< Debug function 13 */ + FUNC_DEBUG14 = 238, /*!< Debug function 14 */ + FUNC_DEBUG15 = 239, /*!< Debug function 15 */ + FUNC_DEBUG16 = 240, /*!< Debug function 16 */ + FUNC_DEBUG17 = 241, /*!< Debug function 17 */ + FUNC_DEBUG18 = 242, /*!< Debug function 18 */ + FUNC_DEBUG19 = 243, /*!< Debug function 19 */ + FUNC_DEBUG20 = 244, /*!< Debug function 20 */ + FUNC_DEBUG21 = 245, /*!< Debug function 21 */ + FUNC_DEBUG22 = 246, /*!< Debug function 22 */ + FUNC_DEBUG23 = 247, /*!< Debug function 23 */ + FUNC_DEBUG24 = 248, /*!< Debug function 24 */ + FUNC_DEBUG25 = 249, /*!< Debug function 25 */ + FUNC_DEBUG26 = 250, /*!< Debug function 26 */ + FUNC_DEBUG27 = 251, /*!< Debug function 27 */ + FUNC_DEBUG28 = 252, /*!< Debug function 28 */ + FUNC_DEBUG29 = 253, /*!< Debug function 29 */ + FUNC_DEBUG30 = 254, /*!< Debug function 30 */ + FUNC_DEBUG31 = 255, /*!< Debug function 31 */ + FUNC_MAX = 256, /*!< Function numbers */ +} fpioa_function_t; +/* clang-format on */ + +/** + * @brief FPIOA pull settings + * + * @note FPIOA pull settings description + * + * | PU | PD | Description | + * |-----|-----|-----------------------------------| + * | 0 | 0 | No Pull | + * | 0 | 1 | Pull Down | + * | 1 | 0 | Pull Up | + * | 1 | 1 | Undefined | + * + */ + +/* clang-format off */ +typedef enum _fpioa_pull +{ + FPIOA_PULL_NONE, /*!< No Pull */ + FPIOA_PULL_DOWN, /*!< Pull Down */ + FPIOA_PULL_UP, /*!< Pull Up */ + FPIOA_PULL_MAX /*!< Count of pull settings */ +} fpioa_pull_t; +/* clang-format on */ + +/** + * @brief FPIOA driving settings + * + * @note FPIOA driving settings description + * There are 16 kinds of driving settings + * + * @note Low Level Output Current + * + * |DS[3:0] |Min(mA)|Typ(mA)|Max(mA)| + * |--------|-------|-------|-------| + * |0000 |3.2 |5.4 |8.3 | + * |0001 |4.7 |8.0 |12.3 | + * |0010 |6.3 |10.7 |16.4 | + * |0011 |7.8 |13.2 |20.2 | + * |0100 |9.4 |15.9 |24.2 | + * |0101 |10.9 |18.4 |28.1 | + * |0110 |12.4 |20.9 |31.8 | + * |0111 |13.9 |23.4 |35.5 | + * + * @note High Level Output Current + * + * |DS[3:0] |Min(mA)|Typ(mA)|Max(mA)| + * |--------|-------|-------|-------| + * |0000 |5.0 |7.6 |11.2 | + * |0001 |7.5 |11.4 |16.8 | + * |0010 |10.0 |15.2 |22.3 | + * |0011 |12.4 |18.9 |27.8 | + * |0100 |14.9 |22.6 |33.3 | + * |0101 |17.4 |26.3 |38.7 | + * |0110 |19.8 |30.0 |44.1 | + * |0111 |22.3 |33.7 |49.5 | + * + */ + +/* clang-format off */ +typedef enum _fpioa_driving +{ + FPIOA_DRIVING_0, /*!< 0000 */ + FPIOA_DRIVING_1, /*!< 0001 */ + FPIOA_DRIVING_2, /*!< 0010 */ + FPIOA_DRIVING_3, /*!< 0011 */ + FPIOA_DRIVING_4, /*!< 0100 */ + FPIOA_DRIVING_5, /*!< 0101 */ + FPIOA_DRIVING_6, /*!< 0110 */ + FPIOA_DRIVING_7, /*!< 0111 */ + FPIOA_DRIVING_8, /*!< 1000 */ + FPIOA_DRIVING_9, /*!< 1001 */ + FPIOA_DRIVING_10, /*!< 1010 */ + FPIOA_DRIVING_11, /*!< 1011 */ + FPIOA_DRIVING_12, /*!< 1100 */ + FPIOA_DRIVING_13, /*!< 1101 */ + FPIOA_DRIVING_14, /*!< 1110 */ + FPIOA_DRIVING_15, /*!< 1111 */ + FPIOA_DRIVING_MAX /*!< Count of driving settings */ +} fpioa_driving_t; +/* clang-format on */ + +/** + * @brief FPIOA IO + * + * FPIOA IO is the specific pin of the chip package. Every IO + * has a 32bit width register that can independently implement + * schmitt trigger, invert input, invert output, strong pull + * up, driving selector, static input and static output. And more, + * it can implement any pin of any peripheral devices. + * + * @note FPIOA IO's register bits Layout + * + * | Bits | Name |Description | + * |-----------|----------|---------------------------------------------------| + * | 31 | PAD_DI | Read current IO's data input. | + * | 30:24 | NA | Reserved bits. | + * | 23 | ST | Schmitt trigger. | + * | 22 | DI_INV | Invert Data input. | + * | 21 | IE_INV | Invert the input enable signal. | + * | 20 | IE_EN | Input enable. It can disable or enable IO input. | + * | 19 | SL | Slew rate control enable. | + * | 18 | SPU | Strong pull up. | + * | 17 | PD | Pull select: 0 for pull down, 1 for pull up. | + * | 16 | PU | Pull enable. | + * | 15 | DO_INV | Invert the result of data output select (DO_SEL). | + * | 14 | DO_SEL | Data output select: 0 for DO, 1 for OE. | + * | 13 | OE_INV | Invert the output enable signal. | + * | 12 | OE_EN | Output enable.It can disable or enable IO output. | + * | 11:8 | DS | Driving selector. | + * | 7:0 | CH_SEL | Channel select from 256 input. | + * + */ +typedef struct _fpioa_io_config +{ + uint32_t ch_sel : 8; + /*!< Channel select from 256 input. */ + uint32_t ds : 4; + /*!< Driving selector. */ + uint32_t oe_en : 1; + /*!< Static output enable, will AND with OE_INV. */ + uint32_t oe_inv : 1; + /*!< Invert output enable. */ + uint32_t do_sel : 1; + /*!< Data output select: 0 for DO, 1 for OE. */ + uint32_t do_inv : 1; + /*!< Invert the result of data output select (DO_SEL). */ + uint32_t pu : 1; + /*!< Pull up enable. 0 for nothing, 1 for pull up. */ + uint32_t pd : 1; + /*!< Pull down enable. 0 for nothing, 1 for pull down. */ + uint32_t resv0 : 1; + /*!< Reserved bits. */ + uint32_t sl : 1; + /*!< Slew rate control enable. */ + uint32_t ie_en : 1; + /*!< Static input enable, will AND with IE_INV. */ + uint32_t ie_inv : 1; + /*!< Invert input enable. */ + uint32_t di_inv : 1; + /*!< Invert Data input. */ + uint32_t st : 1; + /*!< Schmitt trigger. */ + uint32_t resv1 : 7; + /*!< Reserved bits. */ + uint32_t pad_di : 1; + /*!< Read current IO's data input. */ +} __attribute__((packed, aligned(4))) fpioa_io_config_t; + +/** + * @brief FPIOA tie setting + * + * FPIOA Object have 48 IO pin object and 256 bit input tie bits. + * All SPI arbitration signal will tie high by default. + * + * @note FPIOA function tie bits RAM Layout + * + * | Address | Name |Description | + * |-----------|------------------|----------------------------------| + * | 0x000 | TIE_EN[31:0] | Input tie enable bits [31:0] | + * | 0x004 | TIE_EN[63:32] | Input tie enable bits [63:32] | + * | 0x008 | TIE_EN[95:64] | Input tie enable bits [95:64] | + * | 0x00C | TIE_EN[127:96] | Input tie enable bits [127:96] | + * | 0x010 | TIE_EN[159:128] | Input tie enable bits [159:128] | + * | 0x014 | TIE_EN[191:160] | Input tie enable bits [191:160] | + * | 0x018 | TIE_EN[223:192] | Input tie enable bits [223:192] | + * | 0x01C | TIE_EN[255:224] | Input tie enable bits [255:224] | + * | 0x020 | TIE_VAL[31:0] | Input tie value bits [31:0] | + * | 0x024 | TIE_VAL[63:32] | Input tie value bits [63:32] | + * | 0x028 | TIE_VAL[95:64] | Input tie value bits [95:64] | + * | 0x02C | TIE_VAL[127:96] | Input tie value bits [127:96] | + * | 0x030 | TIE_VAL[159:128] | Input tie value bits [159:128] | + * | 0x034 | TIE_VAL[191:160] | Input tie value bits [191:160] | + * | 0x038 | TIE_VAL[223:192] | Input tie value bits [223:192] | + * | 0x03C | TIE_VAL[255:224] | Input tie value bits [255:224] | + * + * @note Function which input tie high by default + * + * | Name |Description | + * |---------------|---------------------------------------| + * | SPI0_ARB | Arbitration function of SPI master 0 | + * | SPI1_ARB | Arbitration function of SPI master 1 | + * + * Tie high means the SPI Arbitration input is 1 + * + */ +typedef struct _fpioa_tie +{ + uint32_t en[FUNC_MAX / 32]; + /*!< FPIOA GPIO multiplexer tie enable array */ + uint32_t val[FUNC_MAX / 32]; + /*!< FPIOA GPIO multiplexer tie value array */ +} __attribute__((packed, aligned(4))) fpioa_tie_t; + +/** + * @brief FPIOA Object + * + * FPIOA Object have 48 IO pin object and 256 bit input tie bits. + * All SPI arbitration signal will tie high by default. + * + * @note FPIOA IO Pin RAM Layout + * + * | Address | Name |Description | + * |-----------|----------|--------------------------------| + * | 0x000 | PAD0 | FPIOA GPIO multiplexer io 0 | + * | 0x004 | PAD1 | FPIOA GPIO multiplexer io 1 | + * | 0x008 | PAD2 | FPIOA GPIO multiplexer io 2 | + * | 0x00C | PAD3 | FPIOA GPIO multiplexer io 3 | + * | 0x010 | PAD4 | FPIOA GPIO multiplexer io 4 | + * | 0x014 | PAD5 | FPIOA GPIO multiplexer io 5 | + * | 0x018 | PAD6 | FPIOA GPIO multiplexer io 6 | + * | 0x01C | PAD7 | FPIOA GPIO multiplexer io 7 | + * | 0x020 | PAD8 | FPIOA GPIO multiplexer io 8 | + * | 0x024 | PAD9 | FPIOA GPIO multiplexer io 9 | + * | 0x028 | PAD10 | FPIOA GPIO multiplexer io 10 | + * | 0x02C | PAD11 | FPIOA GPIO multiplexer io 11 | + * | 0x030 | PAD12 | FPIOA GPIO multiplexer io 12 | + * | 0x034 | PAD13 | FPIOA GPIO multiplexer io 13 | + * | 0x038 | PAD14 | FPIOA GPIO multiplexer io 14 | + * | 0x03C | PAD15 | FPIOA GPIO multiplexer io 15 | + * | 0x040 | PAD16 | FPIOA GPIO multiplexer io 16 | + * | 0x044 | PAD17 | FPIOA GPIO multiplexer io 17 | + * | 0x048 | PAD18 | FPIOA GPIO multiplexer io 18 | + * | 0x04C | PAD19 | FPIOA GPIO multiplexer io 19 | + * | 0x050 | PAD20 | FPIOA GPIO multiplexer io 20 | + * | 0x054 | PAD21 | FPIOA GPIO multiplexer io 21 | + * | 0x058 | PAD22 | FPIOA GPIO multiplexer io 22 | + * | 0x05C | PAD23 | FPIOA GPIO multiplexer io 23 | + * | 0x060 | PAD24 | FPIOA GPIO multiplexer io 24 | + * | 0x064 | PAD25 | FPIOA GPIO multiplexer io 25 | + * | 0x068 | PAD26 | FPIOA GPIO multiplexer io 26 | + * | 0x06C | PAD27 | FPIOA GPIO multiplexer io 27 | + * | 0x070 | PAD28 | FPIOA GPIO multiplexer io 28 | + * | 0x074 | PAD29 | FPIOA GPIO multiplexer io 29 | + * | 0x078 | PAD30 | FPIOA GPIO multiplexer io 30 | + * | 0x07C | PAD31 | FPIOA GPIO multiplexer io 31 | + * | 0x080 | PAD32 | FPIOA GPIO multiplexer io 32 | + * | 0x084 | PAD33 | FPIOA GPIO multiplexer io 33 | + * | 0x088 | PAD34 | FPIOA GPIO multiplexer io 34 | + * | 0x08C | PAD35 | FPIOA GPIO multiplexer io 35 | + * | 0x090 | PAD36 | FPIOA GPIO multiplexer io 36 | + * | 0x094 | PAD37 | FPIOA GPIO multiplexer io 37 | + * | 0x098 | PAD38 | FPIOA GPIO multiplexer io 38 | + * | 0x09C | PAD39 | FPIOA GPIO multiplexer io 39 | + * | 0x0A0 | PAD40 | FPIOA GPIO multiplexer io 40 | + * | 0x0A4 | PAD41 | FPIOA GPIO multiplexer io 41 | + * | 0x0A8 | PAD42 | FPIOA GPIO multiplexer io 42 | + * | 0x0AC | PAD43 | FPIOA GPIO multiplexer io 43 | + * | 0x0B0 | PAD44 | FPIOA GPIO multiplexer io 44 | + * | 0x0B4 | PAD45 | FPIOA GPIO multiplexer io 45 | + * | 0x0B8 | PAD46 | FPIOA GPIO multiplexer io 46 | + * | 0x0BC | PAD47 | FPIOA GPIO multiplexer io 47 | + * + */ +typedef struct _fpioa +{ + fpioa_io_config_t io[FPIOA_NUM_IO]; + /*!< FPIOA GPIO multiplexer io array */ + fpioa_tie_t tie; + /*!< FPIOA GPIO multiplexer tie */ +} __attribute__((packed, aligned(4))) fpioa_t; + +/** + * @brief FPIOA object instanse + */ +extern volatile fpioa_t *const fpioa; + +/** + * @brief Initialize FPIOA user custom default settings + * + * @note This function will set all FPIOA pad registers to user-defined + * values from kconfig + * + * @return result + * - 0 Success + * - Other Fail + */ +int fpioa_init(void); + +/** + * @brief Get IO configuration + * + * @param[in] number The IO number + * @param cfg Pointer to struct of IO configuration for specified IO + * + * @return result + * - 0 Success + * - Other Fail + */ +int fpioa_get_io(int number, fpioa_io_config_t *cfg); + +/** + * @brief Set IO configuration + * + * @param[in] number The IO number + * @param[in] cfg Pointer to struct of IO configuration for specified IO + * + * @return result + * - 0 Success + * - Other Fail + */ +int fpioa_set_io(int number, fpioa_io_config_t *cfg); + +/** + * @brief Set IO configuration with function number + * + * @note The default IO configuration which bind to function number will + * set automatically + * + * @param[in] number The IO number + * @param[in] function The function enum number + * + * @return result + * - 0 Success + * - Other Fail + */ +int fpioa_set_function_raw(int number, fpioa_function_t function); + +/** + * @brief Set only IO configuration with function number + * + * @note The default IO configuration which bind to function number will + * set automatically + * + * @param[in] number The IO number + * @param[in] function The function enum number + * + * @return result + * - 0 Success + * - Other Fail + */ +int fpioa_set_function(int number, fpioa_function_t function); + +/** + * @brief Set tie enable to function + * + * @param[in] function The function enum number + * @param[in] enable Tie enable to set, 1 is enable, 0 is disable + * + * @return result + * - 0 Success + * - Other Fail + */ +int fpioa_set_tie_enable(fpioa_function_t function, int enable); + +/** + * @brief Set tie value to function + * + * @param[in] function The function enum number + * @param[in] value Tie value to set, 1 is HIGH, 0 is LOW + * + * @return result + * - 0 Success + * - Other Fail + */ +int fpioa_set_tie_value(fpioa_function_t function, int value); + +/** + * @brief Set IO pull function + * + * @param[in] number The IO number + * @param[in] pull The pull enum number + * + * @return result + * - 0 Success + * - Other Fail + */ +int fpioa_set_io_pull(int number, fpioa_pull_t pull); + +/** + * @brief Get IO pull function + * + * @param[in] number The IO number + * + * @return result + * - -1 Fail + * - Other The pull enum number + */ +int fpioa_get_io_pull(int number); + +/** + * @brief Set IO driving + * + * @param[in] number The IO number + * @param[in] driving The driving enum number + * + * @return result + * - 0 Success + * - Other Fail + */ +int fpioa_set_io_driving(int number, fpioa_driving_t driving); + +/** + * @brief Get IO driving + * + * @param[in] number The IO number + * + * @return result + * - -1 Fail + * - Other The driving enum number + */ +int fpioa_get_io_driving(int number); + +/** + * @brief Get IO by function + * + * @param[in] function The function enum number + * + * @return result + * - -1 Fail + * - Other The IO number + */ +int fpioa_get_io_by_function(fpioa_function_t function); + +/** + * @brief Set IO slew rate control + * + * @param[in] number The IO number + * @param[in] sl_value Enable slew rate. 0: disable 1:enable + * + * @return result + * - 0 Success + * - Other Fail + */ +int fpioa_set_sl(int number, uint8_t sl_enable); + +/** + * @brief Set IO schmitt trigger + * + * @param[in] number The IO number + * @param[in] st_enable Enable schmitt trigger. 0: disable 1:enable + * + * @return result + * - 0 Success + * - Other Fail + */ +int fpioa_set_st(int number, uint8_t st_enable); + +/** + * @brief Set IO output invert enable + * + * @param[in] number The IO number + * @param[in] inv_enable Enable output invert. 0: disable 1:enable + * + * @return result + * - 0 Success + * - Other Fail + */ +int fpioa_set_oe_inv(int number, uint8_t inv_enable); + +#ifdef __cplusplus +} +#endif + +#endif /* _DRIVER_FPIOA_H */ diff --git a/Ubiquitous/Nuttx_Fusion_XiUOS/app_match_nuttx/nuttx/arch/risc-v/src/k210/k210_clockconfig.c b/Ubiquitous/Nuttx_Fusion_XiUOS/app_match_nuttx/nuttx/arch/risc-v/src/k210/k210_clockconfig.c index 616348bf6..dd22f07a0 100755 --- a/Ubiquitous/Nuttx_Fusion_XiUOS/app_match_nuttx/nuttx/arch/risc-v/src/k210/k210_clockconfig.c +++ b/Ubiquitous/Nuttx_Fusion_XiUOS/app_match_nuttx/nuttx/arch/risc-v/src/k210/k210_clockconfig.c @@ -142,12 +142,18 @@ void k210_clockconfig(void) void k210_sysctl_init(void) { -// sysctl_pll_set_freq(SYSCTL_PLL0, 800000000UL); -// sysctl_pll_set_freq(SYSCTL_PLL1, 400000000UL); -// sysctl_pll_set_freq(SYSCTL_PLL2, 45158400UL); + sysctl_pll_set_freq(SYSCTL_PLL0, 800000000UL); + sysctl_pll_set_freq(SYSCTL_PLL1, 400000000UL); + sysctl_pll_set_freq(SYSCTL_PLL2, 45158400UL); + sysctl_clock_set_threshold(SYSCTL_THRESHOLD_APB1, 2); -// sysctl_set_power_mode(SYSCTL_POWER_BANK0, SYSCTL_POWER_V18); -// sysctl_set_power_mode(SYSCTL_POWER_BANK1, SYSCTL_POWER_V18); -// sysctl_set_power_mode(SYSCTL_POWER_BANK2, SYSCTL_POWER_V18); + sysctl_set_power_mode(SYSCTL_POWER_BANK0, SYSCTL_POWER_V18); + sysctl_set_power_mode(SYSCTL_POWER_BANK1, SYSCTL_POWER_V18); + sysctl_set_power_mode(SYSCTL_POWER_BANK2, SYSCTL_POWER_V18); + + // for IO-27/28 + sysctl_set_power_mode(SYSCTL_POWER_BANK4, SYSCTL_POWER_V33); + // for IO-20~23 + sysctl_set_power_mode(SYSCTL_POWER_BANK3, SYSCTL_POWER_V33); } diff --git a/Ubiquitous/Nuttx_Fusion_XiUOS/app_match_nuttx/nuttx/arch/risc-v/src/k210/k210_fpioa.c b/Ubiquitous/Nuttx_Fusion_XiUOS/app_match_nuttx/nuttx/arch/risc-v/src/k210/k210_fpioa.c index 267011ec3..ad161b9dd 100644 --- a/Ubiquitous/Nuttx_Fusion_XiUOS/app_match_nuttx/nuttx/arch/risc-v/src/k210/k210_fpioa.c +++ b/Ubiquitous/Nuttx_Fusion_XiUOS/app_match_nuttx/nuttx/arch/risc-v/src/k210/k210_fpioa.c @@ -58,40 +58,6 @@ int k210_fpioa_get_io_by_function(uint8_t function) return -1; } -int fpioa_set_io_pull(int number, fpioa_pull_t pull) -{ - /* Check parameters */ - if (number < 0 || number >= K210_IO_NUMBER || pull >= FPIOA_PULL_MAX) - return -1; - - /* read register */ - uint32_t *fpioa = (uint32_t *)K210_FPIOA_BASE; - fpioa_io_config_t cfg = *(fpioa_io_config_t *)(&fpioa[number]); - uint32_t ioflags = 0x0000; - - switch (pull) - { - case FPIOA_PULL_NONE: - cfg.pu = 0; - cfg.pd = 0; - break; - case FPIOA_PULL_DOWN: - cfg.pu = 0; - cfg.pd = 1; - break; - case FPIOA_PULL_UP: - cfg.pu = 1; - cfg.pd = 0; - break; - default: - break; - } - - /* write register */ - ioflags = *(uint32_t*)(&cfg); - putreg32(ioflags, &fpioa[number]); - return 0; -} void k210_fpioa_config(uint32_t io, uint32_t ioflags) { diff --git a/Ubiquitous/Nuttx_Fusion_XiUOS/app_match_nuttx/nuttx/arch/risc-v/src/k210/k210_fpioa.h b/Ubiquitous/Nuttx_Fusion_XiUOS/app_match_nuttx/nuttx/arch/risc-v/src/k210/k210_fpioa.h index cc122c3b8..161fbe7c5 100644 --- a/Ubiquitous/Nuttx_Fusion_XiUOS/app_match_nuttx/nuttx/arch/risc-v/src/k210/k210_fpioa.h +++ b/Ubiquitous/Nuttx_Fusion_XiUOS/app_match_nuttx/nuttx/arch/risc-v/src/k210/k210_fpioa.h @@ -22,7 +22,7 @@ * @file k210_fpioa.h * @brief nuttx source code * https://github.com/apache/incubator-nuttx.git -* @version 10.3.0 +* @version 10.3.0 * @author AIIT XUOS Lab * @date 2022-03-23 */ @@ -35,6 +35,7 @@ ****************************************************************************/ #include +#include "fpioa.h" /**************************************************************************** * Pre-processor Definitions @@ -102,34 +103,6 @@ #define K210_IOFLAG_GPIOHS (K210_IO_DS(0xf) | K210_IO_OUTPUT_ENABLE | \ K210_IO_INPUT_ENABLE | K210_IO_ST) -typedef struct _fpioa_io_config -{ - uint32_t ch_sel : 8; /* Channel select from 256 input. */ - uint32_t ds : 4; /* Driving selector. */ - uint32_t oe_en : 1; /* Static output enable, will AND with OE_INV. */ - uint32_t oe_inv : 1; /* Invert output enable. */ - uint32_t do_sel : 1; /* Data output select: 0 for DO, 1 for OE. */ - uint32_t do_inv : 1; /* Invert the result of data output select (DO_SEL). */ - uint32_t pu : 1; /* Pull up enable. 0 for nothing, 1 for pull up. */ - uint32_t pd : 1; /* Pull down enable. 0 for nothing, 1 for pull down. */ - uint32_t resv0 : 1; /* Reserved bits. */ - uint32_t sl : 1; /* Slew rate control enable. */ - uint32_t ie_en : 1; /* Static input enable, will AND with IE_INV. */ - uint32_t ie_inv : 1; /* Invert input enable. */ - uint32_t di_inv : 1; /* Invert Data input. */ - uint32_t st : 1; /* Schmitt trigger. */ - uint32_t resv1 : 7; /* Reserved bits. */ - uint32_t pad_di : 1; /* Read current IO's data input. */ -} __attribute__((packed, aligned(4))) fpioa_io_config_t; - -typedef enum _fpioa_pull -{ - FPIOA_PULL_NONE, /* No Pull */ - FPIOA_PULL_DOWN, /* Pull Down */ - FPIOA_PULL_UP, /* Pull Up */ - FPIOA_PULL_MAX /* Count of pull settings */ -} fpioa_pull_t; - /**************************************************************************** * Public Functions Prototypes diff --git a/Ubiquitous/Nuttx_Fusion_XiUOS/app_match_nuttx/nuttx/drivers/serial/Kconfig b/Ubiquitous/Nuttx_Fusion_XiUOS/app_match_nuttx/nuttx/drivers/serial/Kconfig new file mode 100755 index 000000000..3fb8296b8 --- /dev/null +++ b/Ubiquitous/Nuttx_Fusion_XiUOS/app_match_nuttx/nuttx/drivers/serial/Kconfig @@ -0,0 +1,712 @@ +# +# For a description of the syntax of this configuration file, +# see the file kconfig-language.txt in the NuttX tools repository. +# + +config ARCH_HAVE_SERIAL_TERMIOS + bool + default n + +menuconfig SERIAL + bool "Serial Driver Support" + default y + ---help--- + Front-end character drivers for chip-specific UARTs. This provide + some TTY-like functionality and are commonly used (but not required + for) the NuttX system console. See also include/nuttx/serial/serial.h + +if SERIAL + +config SERIAL_PM_ACTIVITY_DOMAIN + int "PM activity domain" + default 0 + depends on PM + ---help--- + When characters are received on a console device, pm_activity() + will be called with this PM domain. + +config SERIAL_PM_ACTIVITY_PRIORITY + int "PM activity priority when receive character" + default 6 + depends on PM + ---help--- + When characters are received on a console device, pm_activity() + will be called with this PM priority. + +config SERIAL_REMOVABLE + bool + default n + +config SERIAL_CONSOLE + bool + default n + +menuconfig U16550_UART + bool "16550 UART Chip support" + select ARCH_HAVE_SERIAL_TERMIOS + default n + +if U16550_UART +source "drivers/serial/Kconfig-16550" +endif + +# +# MCU serial peripheral driver? +# + +config OTHER_UART_SERIALDRIVER + bool + default n + select MCU_SERIAL + +config MCU_SERIAL + bool + default n + +config RPMSG_UART + bool "UART rpmsg support" + default n + depends on OPENAMP + select ARCH_HAVE_SERIAL_TERMIOS + select SERIAL_RXDMA + select SERIAL_TXDMA + select SERIAL_REMOVABLE + select SERIAL_IFLOWCONTROL + +config RPMSG_SERIALINIT + bool "Add dummy up_serialinit for UART rpmsg" + default y if !U16550_UART && !MCU_SERIAL + depends on RPMSG_UART + +# +# Standard serial driver configuration +# + +config STANDARD_SERIAL + bool "Enable standard \"upper-half\" serial driver" + default y if MCU_SERIAL + default n if !MCU_SERIAL + ---help--- + Enable the standard, upper-half serial driver used by most MCU serial peripherals. + +config SERIAL_NPOLLWAITERS + int "Number of poll threads" + default 4 + ---help--- + Maximum number of threads than can be waiting for POLL events. + Default: 4 + +config SERIAL_IFLOWCONTROL + bool + default n + +config SERIAL_RS485CONTROL + bool + default n + ---help--- + Use RTS pin to control RS485 direction (Asserted while transmitting). + +config SERIAL_OFLOWCONTROL + bool + default n + +config SERIAL_TXDMA + bool + default n + +config SERIAL_RXDMA + bool + default n + +config SERIAL_IFLOWCONTROL_WATERMARKS + bool "RX flow control watermarks" + default n + depends on SERIAL_IFLOWCONTROL + ---help--- + Call the "lower half" rxflowcontrol method whenever the number of + characters in the serial RX buffer falls above an upper water mark + level or below a lower watermark level. The default behavior is to + call the rxflowcontrol method only when the RX buffer is empty or + full. + +if SERIAL_IFLOWCONTROL_WATERMARKS + +config SERIAL_IFLOWCONTROL_LOWER_WATERMARK + int "RX lower Watermark (percent)" + default 10 + range 1 99 + ---help--- + Call the rxflowcontrol method then there are this amount (or or less) + data buffered in the serial drivers RX buffer. This is expressed + as a percentage of the total size of the RX buffer which may vary + from instance-to-instance. + +config SERIAL_IFLOWCONTROL_UPPER_WATERMARK + int "RX upper Watermark (percent)" + default 90 + range 1 99 + ---help--- + Call the rxflowcontrol method then there are this amount (or more) + data buffered in the serial drivers RX buffer. This is expressed + as a percentage of the total size of the RX buffer which may vary + from instance-to-instance. + +endif # SERIAL_IFLOWCONTROL_WATERMARKS + +config SERIAL_TIOCSERGSTRUCT + bool "Support TIOCSERGSTRUCT" + default n + depends on DEBUG_FEATURES && (MCU_SERIAL || U16550_UART) + ---help--- + As a debug option, many serial bottom half drivers support the TIOCSERGSTRUCT + that allows you to get the internal driver data structure. By default, this + IOCTL is not supported in order to reduce footprint. But if (1) the driver + supports the TIOCSERGSTRUCT ioctl, and (2) this option is selected, then + support for the TIOCSERGSTRUCT will be enabled. + +config SERIAL_TERMIOS + bool "Serial TERMIOS support" + depends on ARCH_HAVE_SERIAL_TERMIOS + default n + ---help--- + Serial driver supports termios.h interfaces (tcsetattr, tcflush, etc.). + If this is not defined, then the terminal settings (baud, parity, etc). + are not configurable at runtime; serial streams cannot be flushed, etc.. + +config TTY_LAUNCH + bool "Enable feature TTY launch program" + default n + ---help--- + If select this, then user can launch a program with a special input. + +if TTY_LAUNCH + +config TTY_LAUNCH_CHAR + hex "TTY launch program characters" + default 0x12 + ---help--- + Use Ctrl-R 0x12 inputs to determine whether launch a program + +config TTY_LAUNCH_ARGS + string "TTY launch argument list" + default INIT_ARGS + ---help--- + The argument list for user applications. e.g.: + "\"arg1\",\"arg2\",\"arg3\"" + +config TTY_LAUNCH_PRIORITY + int "TTY launch program priority" + default INIT_PRIORITY + +config TTY_LAUNCH_STACKSIZE + hex "TTY launch program stack size" + default INIT_STACKSIZE + +choice + prompt "TTY launch method" + default TTY_LAUNCH_ENTRY + +config TTY_LAUNCH_ENTRY + bool "TTY launch program" + +config TTY_LAUNCH_FILE + bool "TTY launch file" + depends on !BINFMT_DISABLE + +endchoice + +config TTY_LAUNCH_ENTRYPOINT + string "TTY launch program entry" + depends on TTY_LAUNCH_ENTRY + default INIT_ENTRYPOINT + +config TTY_LAUNCH_ENTRYNAME + string "TTY launch program name" + depends on TTY_LAUNCH_ENTRY + default TTY_LAUNCH_ENTRYPOINT + +config TTY_LAUNCH_FILEPATH + string "TTY launch file path" + depends on TTY_LAUNCH_FILE + default INIT_FILEPATH + ---help--- + The name of the entry point for user applications. For the example + applications this is of the form 'app_main' where 'app' is the application + name. If not defined, USER_ENTRYPOINT defaults to "main". + +endif # TTY_LAUNCH + +config TTY_FORCE_PANIC + bool "Enable TTY force crash" + default n + depends on DEBUG_FEATURES + ---help--- + This is for debugging system busyloop or deadlock, when the shell can't run, + then use this force crash the system to see the dumplog. + +config TTY_FORCE_PANIC_CHAR + hex "TTY force crash characters" + default 0x1F + depends on TTY_FORCE_PANIC + ---help--- + Use Ctrl-? 0x1F inputs to determine whether panic system + +config TTY_SIGINT + bool "Support SIGINT" + default n + ---help--- + Whether support Ctrl-c/x event. Enabled automatically for console + devices. May be enabled for other serial devices using the ISIG bit + in the Termios c_lflag. + + REVISIT: This implementation is compliant but incomplete. The + c_lflag ISIG bit normally enables/disables INTR, QUIT, SUSP, and + DSUSP character processing. The relationship between these names, + standard signals, and typical key presses are as follows: + + INTR SIGINT Ctrl-C ETX(0x03) Interrupt + KILL SIGKILL Ctrl-U NAK(0x15) Kill + QUIT SIGQUIT Ctrl-\ FS (0x1c) Quit + SUSP SIGTSTP Ctrl-Z SUB(0x1a) Suspend + DSUSP SIGTSTP Ctrl-Y EM (0x19) Delayed suspend + + Additional requirements: + - SIGKILL cannot be caught or ignored. Compared to SIGTERM which + is like SIGKILL but can be caught or ignored. + - SIGQUIT is like SIGINT but causes generation of a core dump + - SIGSTOP cannot be caught or ignored. SIGTSTP is like SIGSTOP but + can be caught or ignored. + - The delayed suspend (DSUSD) is like suspend (SUPD), except that + the suspension is delayed until the next read operation + + Ctrl-D (EOT 0x04) normally should not generate a signal but, instead, + should cause an immediate End-of-File result. + +config TTY_SIGINT_CHAR + hex "Serial parse SIGINT characters" + default 0x03 if SERIAL_CONSOLE + default 0x04 if !SERIAL_CONSOLE + depends on TTY_SIGINT + ---help--- + Use ASCII 0x03 (Ctrl-c) or 0x04 (ctrl-d) inputs to determine whether + to send a SIGINT event. Other characters may also be selected. + + REVISIT: Traditionally Ctrl-C would generate SIGINT. Ctrl-D is the + End-of-File character that should close the stream. + +config TTY_SIGTSTP + bool "Support SIGTSTP" + default n + ---help--- + Whether support Ctrl-z event. Enabled automatically for console + devices. May be enabled for other serial devices using the ISIG bit + in the Termios c_lflag. + + REVISIT: This implementation is compliant but incomplete. The + c_lflag ISIG bit normally enables/disables INTR, QUIT, SUSP, and + DSUSP character processing. The relationship between these names, + standard signals, and typical key presses are as follows: + + INTR SIGINT Ctrl-C ETX(0x03) Interrupt + KILL SIGKILL Ctrl-U NAK(0x15) Kill + QUIT SIGQUIT Ctrl-\ FS (0x1c) Quit + SUSP SIGTSTP Ctrl-Z SUB(0x1a) Suspend + DSUSP SIGTSTP Ctrl-Y EM (0x19) Delayed suspend + + Additional requirements: + - SIGKILL cannot be caught or ignored. Compared to SIGTERM which + is like SIGKILL but can be caught or ignored. + - SIGQUIT is like SIGINT but causes generation of a core dump + - SIGSTOP cannot be caught or ignored. SIGTSTP is like SIGSTOP but + can be caught or ignored. + - The delayed suspend (DSUSD) is like suspend (SUPD), except that + the suspension is delayed until the next read operation + +config TTY_SIGTSTP_CHAR + hex "Serial parse SIGTSTP characters" + default 0x1a + depends on TTY_SIGTSTP + ---help--- + Use ASCII 0x1a (Ctrl-z) input to determine whether to send a SIGTSTP + event. Other characters may also be selected. + +# +# Serial console selection +# + +choice + prompt "Serial console" + default NO_SERIAL_CONSOLE if !OTHER_UART_SERIALDRIVER + default OTHER_SERIAL_CONSOLE if OTHER_UART_SERIALDRIVER + depends on MCU_SERIAL + #depends on DEV_CONSOLE - We may have serial console with no file system at all + +config UART_SERIAL_CONSOLE + bool "UART" + depends on UART_SERIALDRIVER + select SERIAL_CONSOLE + +config UART0_SERIAL_CONSOLE + bool "UART0" + depends on UART0_SERIALDRIVER + select SERIAL_CONSOLE + +config USART0_SERIAL_CONSOLE + bool "USART0" + depends on USART0_SERIALDRIVER + select SERIAL_CONSOLE + +config UART1_SERIAL_CONSOLE + bool "UART1" + depends on UART1_SERIALDRIVER + select SERIAL_CONSOLE + +config USART1_SERIAL_CONSOLE + bool "USART1" + depends on USART1_SERIALDRIVER + select SERIAL_CONSOLE + +config UART2_SERIAL_CONSOLE + bool "UART2" + depends on UART2_SERIALDRIVER + select SERIAL_CONSOLE + +config USART2_SERIAL_CONSOLE + bool "USART2" + depends on USART2_SERIALDRIVER + select SERIAL_CONSOLE + +config UART3_SERIAL_CONSOLE + bool "UART3" + depends on UART3_SERIALDRIVER + select SERIAL_CONSOLE + +config USART3_SERIAL_CONSOLE + bool "USART3" + depends on USART3_SERIALDRIVER + select SERIAL_CONSOLE + +config UART4_SERIAL_CONSOLE + bool "UART4" + depends on UART4_SERIALDRIVER + select SERIAL_CONSOLE + +config USART4_SERIAL_CONSOLE + bool "USART4" + depends on USART4_SERIALDRIVER + select SERIAL_CONSOLE + +config UART5_SERIAL_CONSOLE + bool "UART5" + depends on UART5_SERIALDRIVER + select SERIAL_CONSOLE + +config USART5_SERIAL_CONSOLE + bool "USART5" + depends on USART5_SERIALDRIVER + select SERIAL_CONSOLE + +config UART6_SERIAL_CONSOLE + bool "UART6" + depends on UART6_SERIALDRIVER + select SERIAL_CONSOLE + +config USART6_SERIAL_CONSOLE + bool "USART6" + depends on USART6_SERIALDRIVER + select SERIAL_CONSOLE + +config UART7_SERIAL_CONSOLE + bool "UART7" + depends on UART7_SERIALDRIVER + select SERIAL_CONSOLE + +config USART7_SERIAL_CONSOLE + bool "USART7" + depends on USART7_SERIALDRIVER + select SERIAL_CONSOLE + +config UART8_SERIAL_CONSOLE + bool "UART8" + depends on UART8_SERIALDRIVER + select SERIAL_CONSOLE + +config USART8_SERIAL_CONSOLE + bool "USART8" + depends on USART8_SERIALDRIVER + select SERIAL_CONSOLE + +config USART9_SERIAL_CONSOLE + bool "USART8" + depends on USART9_SERIALDRIVER + select SERIAL_CONSOLE + +config LPUART0_SERIAL_CONSOLE + bool "LPUART0" + depends on LPUART0_SERIALDRIVER + select SERIAL_CONSOLE + +config LPUART1_SERIAL_CONSOLE + bool "LPUART1" + depends on LPUART1_SERIALDRIVER + select SERIAL_CONSOLE + +config LPUART2_SERIAL_CONSOLE + bool "LPUART2" + depends on LPUART2_SERIALDRIVER + select SERIAL_CONSOLE + +config LPUART3_SERIAL_CONSOLE + bool "LPUART3" + depends on LPUART3_SERIALDRIVER + select SERIAL_CONSOLE + +config LPUART4_SERIAL_CONSOLE + bool "LPUART4" + depends on LPUART4_SERIALDRIVER + select SERIAL_CONSOLE + +config LPUART5_SERIAL_CONSOLE + bool "LPUART5" + depends on LPUART5_SERIALDRIVER + select SERIAL_CONSOLE + +config LPUART6_SERIAL_CONSOLE + bool "LPUART6" + depends on LPUART6_SERIALDRIVER + select SERIAL_CONSOLE + +config LPUART7_SERIAL_CONSOLE + bool "LPUART7" + depends on LPUART7_SERIALDRIVER + select SERIAL_CONSOLE + +config LPUART8_SERIAL_CONSOLE + bool "LPUART8" + depends on LPUART8_SERIALDRIVER + select SERIAL_CONSOLE + +config SCI0_SERIAL_CONSOLE + bool "SCI0" + depends on SCI0_SERIALDRIVER + select SERIAL_CONSOLE + +config SCI1_SERIAL_CONSOLE + bool "SCI1" + depends on SCI1_SERIALDRIVER + select SERIAL_CONSOLE + +config SCI2_SERIAL_CONSOLE + bool "SCI2" + depends on SCI2_SERIALDRIVER + select SERIAL_CONSOLE + +config SCI3_SERIAL_CONSOLE + bool "SCI3" + depends on SCI3_SERIALDRIVER + select SERIAL_CONSOLE + +config SCI4_SERIAL_CONSOLE + bool "SCI4" + depends on SCI4_SERIALDRIVER + select SERIAL_CONSOLE + +config SCI5_SERIAL_CONSOLE + bool "SCI5" + depends on SCI5_SERIALDRIVER + select SERIAL_CONSOLE + +config SCI6_SERIAL_CONSOLE + bool "SCI6" + depends on SCI6_SERIALDRIVER + select SERIAL_CONSOLE + +config SCI7_SERIAL_CONSOLE + bool "SCI7" + depends on SCI7_SERIALDRIVER + select SERIAL_CONSOLE + +config SCI8_SERIAL_CONSOLE + bool "SCI8" + depends on SCI8_SERIALDRIVER + select SERIAL_CONSOLE + +config SCI9_SERIAL_CONSOLE + bool "SCI9" + depends on SCI9_SERIALDRIVER + select SERIAL_CONSOLE + +config SCI10_SERIAL_CONSOLE + bool "SCI10" + depends on SCI10_SERIALDRIVER + select SERIAL_CONSOLE + +config SCI11_SERIAL_CONSOLE + bool "SCI11" + depends on SCI11_SERIALDRIVER + select SERIAL_CONSOLE + +config SCI12_SERIAL_CONSOLE + bool "SCI12" + depends on SCI12_SERIALDRIVER + select SERIAL_CONSOLE + +config OTHER_SERIAL_CONSOLE + bool "Other serial console" + select SERIAL_CONSOLE + +config NO_SERIAL_CONSOLE + bool "No serial console" + +endchoice + +# +# U[S]ARTn_XYZ settings for MCU serial drivers +# + +menu "UART Configuration" + depends on UART_SERIALDRIVER + +config UART_RXBUFSIZE + int "Receive buffer size" + default 256 + ---help--- + Characters are buffered as they are received. This specifies + the size of the receive buffer. + +config UART_TXBUFSIZE + int "Transmit buffer size" + default 256 + ---help--- + Characters are buffered before being sent. This specifies + the size of the transmit buffer. + +config UART_BAUD + int "BAUD rate" + default 115200 + ---help--- + The configured BAUD of the UART. + +config UART_BITS + int "Character size" + default 8 + ---help--- + The number of bits. Must be either 7 or 8. + +config UART_PARITY + int "Parity setting" + default 0 + range 0 2 + ---help--- + 0=no parity, 1=odd parity, 2=even parity + +config UART_2STOP + int "use 2 stop bits" + default 0 + ---help--- + 1=Two stop bits + +config UART_IFLOWCONTROL + bool "UART RTS flow control" + default n + select SERIAL_IFLOWCONTROL + ---help--- + Enable UART RTS flow control + +config UART_OFLOWCONTROL + bool "UART CTS flow control" + default n + select SERIAL_OFLOWCONTROL + ---help--- + Enable UART CTS flow control + +config UART_TXDMA + bool "UART Tx DMA support" + default n + select SERIAL_TXDMA + ---help--- + Enable Tx DMA transfers on UART + +config UART_RXDMA + bool "UART Rx DMA support" + default n + select SERIAL_RXDMA + ---help--- + Enable Rx DMA transfers on UART + +endmenu + +source "drivers/serial/Kconfig-uart" +source "drivers/serial/Kconfig-lpuart" +source "drivers/serial/Kconfig-usart" +source "drivers/serial/Kconfig-sci" + +menuconfig PSEUDOTERM + bool "Pseudo-Terminal (PTY) support" + default n + select PIPES + select ARCH_HAVE_SERIAL_TERMIOS + ---help--- + Enable support support for master and slave pseudo-terminal devices. + +if PSEUDOTERM + +config PSEUDOTERM_SUSV1 + bool "SUSv1 style" + default y + ---help--- + PTYs as specified in the Single Unix Specification (SUSv1). + + Master: /dev/ptmx (multiplexor) + Slave: /dev/pts/N + + Where N is the minor number + +config PSEUDOTERM_RXBUFSIZE + int "Pseudo-Terminal Rx buffer size" + default 256 + ---help--- + Master-to-slave pipe buffer size. Default: 256 + +config PSEUDOTERM_TXBUFSIZE + int "Pseudo-Terminal Tx buffer size" + default 256 + ---help--- + Slave-to-master pipe buffer size. Default: 256 + +endif # PSEUDOTERM + +menuconfig UART_BTH4 + bool "BT H4 uart pseudo device" + default n + select MM_CIRCBUF + ---help--- + Enable support for Bluetooth H4 UART Pseudo Device(eg. /dev/ttyHCI). + This instantiates a serial-like interface over an existing bluetooth + controller via HCI interface. Useful for external Bluetooth + stacks working this way instead of the socket based interface. + +if UART_BTH4 + +config UART_BTH4_TXBUFSIZE + int "BT H4 uart TX buffer size" + default 1024 + ---help--- + H4 UART TX buffer size. Default: 1024 + +config UART_BTH4_RXBUFSIZE + int "BT H4 uart RX buffer size" + default 1024 + ---help--- + H4 UART RX buffer size. Default: 1024 + +config UART_BTH4_NPOLLWAITERS + int "Number of poll threads" + default 2 + ---help--- + Maximum number of threads than can be waiting for POLL events. + Default: 2 + +endif # UART_BTH4 + +endif # SERIAL diff --git a/Ubiquitous/Nuttx_Fusion_XiUOS/app_match_nuttx/nuttx/drivers/serial/Kconfig-16550 b/Ubiquitous/Nuttx_Fusion_XiUOS/app_match_nuttx/nuttx/drivers/serial/Kconfig-16550 new file mode 100755 index 000000000..4e232659a --- /dev/null +++ b/Ubiquitous/Nuttx_Fusion_XiUOS/app_match_nuttx/nuttx/drivers/serial/Kconfig-16550 @@ -0,0 +1,363 @@ +# +# For a description of the syntax of this configuration file, +# see the file kconfig-language.txt in the NuttX tools repository. +# + +if U16550_UART + +config U16550_SERIAL_DISABLE_REORDERING + bool "Disable reordering of ttySx devices." + default n + ---help--- + NuttX per default reorders the serial ports (/dev/ttySx) so that the + console is always on /dev/ttyS0. If more than one UART is in use this + can, however, have the side-effect that all port mappings + (hardware USART1 -> /dev/ttyS0) change if the console is moved to another + UART. This option disables that re-ordering for 16550 UARTs. + +config U16550_UART0 + bool "16550 UART0" + default n + +if U16550_UART0 + +config U16550_UART0_BASE + hex "16550 UART0 base address" + +config U16550_UART0_CLOCK + int "16550 UART0 clock" + +config U16550_UART0_IRQ + int "16550 UART0 IRQ number" + +config U16550_UART0_BAUD + int "16550 UART0 BAUD" + default 115200 + +config U16550_UART0_PARITY + int "16550 UART0 parity" + default 0 + range 0 2 + ---help--- + 16550 UART0 parity. 0=None, 1=Odd, 2=Even. Default: None + +config U16550_UART0_BITS + int "16550 UART0 number of bits" + default 8 + ---help--- + 16550 UART0 number of bits. Default: 8 + +config U16550_UART0_2STOP + int "16550 UART0 two stop bits" + default 0 + ---help--- + 0=1 stop bit, 1=Two stop bits. Default: 1 stop bit + +config U16550_UART0_RXBUFSIZE + int "16550 UART0 Rx buffer size" + default 256 + ---help--- + 16550 UART0 Rx buffer size. Default: 256 + +config U16550_UART0_TXBUFSIZE + int "16550 UART0 Tx buffer size" + default 256 + ---help--- + 16550 UART0 Tx buffer size. Default: 256 + +config U16550_UART0_IFLOWCONTROL + bool "16550 UART0 RTS flow control" + default n + select SERIAL_IFLOWCONTROL + ---help--- + Enable 16550 UART0 RTS flow control + +config U16550_UART0_OFLOWCONTROL + bool "16550 UART0 CTS flow control" + default n + select SERIAL_OFLOWCONTROL + ---help--- + Enable 16550 UART0 CTS flow control + +endif # U16550_UART0 + +config U16550_UART1 + bool "16550 UART1" + default n + +if U16550_UART1 + +config U16550_UART1_BASE + hex "16550 UART1 base address" + default 0x50210000 + +config U16550_UART1_CLOCK + int "16550 UART1 clock" + default 195000000 + +config U16550_UART1_IRQ + int "16550 UART1 IRQ number" + default 38 + +config U16550_UART1_BAUD + int "16550 UART1 BAUD" + default 9600 + +config U16550_UART1_PARITY + int "16550 UART1 parity" + default 0 + range 0 2 + ---help--- + 16550 UART1 parity. 0=None, 1=Odd, 2=Even. Default: None + +config U16550_UART1_BITS + int "16550 UART1 number of bits" + default 8 + ---help--- + 16550 UART1 number of bits. Default: 8 + +config U16550_UART1_2STOP + int "16550 UART1 two stop bits" + default 0 + ---help--- + 0=1 stop bit, 1=Two stop bits. Default: 1 stop bit + +config U16550_UART1_RXBUFSIZE + int "16550 UART1 Rx buffer size" + default 256 + ---help--- + 16550 UART1 Rx buffer size. Default: 256 + +config U16550_UART1_TXBUFSIZE + int "16550 UART1 Tx buffer size" + default 256 + ---help--- + 16550 UART1 Tx buffer size. Default: 256 + +config U16550_UART1_IFLOWCONTROL + bool "16550 UART1 RTS flow control" + default n + select SERIAL_IFLOWCONTROL + ---help--- + Enable 16550 UART1 RTS flow control + +config U16550_UART1_OFLOWCONTROL + bool "16550 UART1 CTS flow control" + default n + select SERIAL_OFLOWCONTROL + ---help--- + Enable 16550 UART1 CTS flow control + +endif # U16550_UART1 + +config U16550_UART2 + bool "16550 UART2" + default n + +if U16550_UART2 + +config U16550_UART2_BASE + hex "16550 UART2 base address" + default 0x50220000 + +config U16550_UART2_CLOCK + int "16550 UART2 clock" + default 195000000 + +config U16550_UART2_IRQ + int "16550 UART2 IRQ number" + default 39 + +config U16550_UART2_BAUD + int "16550 UART2 BAUD" + default 115200 + +config U16550_UART2_PARITY + int "16550 UART2 parity" + default 0 + range 0 2 + ---help--- + 16550 UART2 parity. 0=None, 1=Odd, 2=Even. Default: None + +config U16550_UART2_BITS + int "16550 UART2 number of bits" + default 8 + ---help--- + 16550 UART2 number of bits. Default: 8 + +config U16550_UART2_2STOP + int "16550 UART2 two stop bits" + default 0 + ---help--- + 0=1 stop bit, 1=Two stop bits. Default: 1 stop bit + +config U16550_UART2_RXBUFSIZE + int "16550 UART2 Rx buffer size" + default 256 + ---help--- + 16550 UART2 Rx buffer size. Default: 256 + +config U16550_UART2_TXBUFSIZE + int "16550 UART2 Tx buffer size" + default 256 + ---help--- + 16550 UART2 Tx buffer size. Default: 256 + +config U16550_UART2_IFLOWCONTROL + bool "16550 UART2 RTS flow control" + default n + select SERIAL_IFLOWCONTROL + ---help--- + Enable 16550 UART2 RTS flow control + +config U16550_UART2_OFLOWCONTROL + bool "16550 UART2 CTS flow control" + default n + select SERIAL_OFLOWCONTROL + ---help--- + Enable 16550 UART2 CTS flow control + +endif # U16550_UART2 + +config U16550_UART3 + bool "16550 UART3" + default n + +if U16550_UART3 + +config U16550_UART3_BASE + hex "16550 UART3 base address" + default 0x50230000 + +config U16550_UART3_CLOCK + int "16550 UART3 clock" + default 195000000 + +config U16550_UART3_IRQ + int "16550 UART3 IRQ number" + default 40 + +config U16550_UART3_BAUD + int "16550 UART3 BAUD" + default 115200 + +config U16550_UART3_PARITY + int "16550 UART3 parity" + default 0 + range 0 2 + ---help--- + 16550 UART3 parity. 0=None, 1=Odd, 2=Even. Default: None + +config U16550_UART3_BITS + int "16550 UART3 number of bits" + default 8 + ---help--- + 16550 UART3 number of bits. Default: 8 + +config U16550_UART3_2STOP + int "16550 UART3 two stop bits" + default 0 + ---help--- + 0=1 stop bit, 1=Two stop bits. Default: 1 stop bit + +config U16550_UART3_RXBUFSIZE + int "16550 UART3 Rx buffer size" + default 256 + ---help--- + 16550 UART3 Rx buffer size. Default: 256 + +config U16550_UART3_TXBUFSIZE + int "16550 UART3 Tx buffer size" + default 256 + ---help--- + 16550 UART3 Tx buffer size. Default: 256 + +config U16550_UART3_IFLOWCONTROL + bool "16550 UART3 RTS flow control" + default n + select SERIAL_IFLOWCONTROL + ---help--- + Enable 16550 UART3 RTS flow control + +config U16550_UART3_OFLOWCONTROL + bool "16550 UART3 CTS flow control" + default n + select SERIAL_OFLOWCONTROL + ---help--- + Enable 16550 UART3 CTS flow control + +endif # U16550_UART3 + +choice + prompt "16550 Serial Console" + default U16550_NO_SERIAL_CONSOLE + depends on DEV_CONSOLE + +config U16550_UART_SERIAL_CONSOLE + bool "16550 UART0 serial console" + depends on U16550_UART + select SERIAL_CONSOLE + +config U16550_UART1_SERIAL_CONSOLE + bool "16550 UART1 serial console" + depends on U16550_UART1 + select SERIAL_CONSOLE + +config U16550_UART2_SERIAL_CONSOLE + bool "16550 UART2 serial console" + depends on U16550_UART2 + select SERIAL_CONSOLE + +config U16550_UART3_SERIAL_CONSOLE + bool "16550 UART3 serial console" + depends on U16550_UART3 + select SERIAL_CONSOLE + +config U16550_NO_SERIAL_CONSOLE + bool "No 16550 serial console" + +endchoice # 16550 Serial Console + +config U16550_SUPRESS_CONFIG + bool "Suppress 16550 configuration" + default n + +config U16550_SUPRESS_INITIAL_CONFIG + bool "Suppress initial 16550 configuration" + depends on !16550_SUPRESS_CONFIG + default y + ---help--- + This option is useful, for example, if you are using a bootloader + that configures the U16550_UART. In that case, you may want to + just leave the existing console configuration in place. Default: n + +config SERIAL_UART_ARCH_MMIO + bool "Platform access register through the memory mapping" + default y + +config SERIAL_UART_ARCH_IOCTL + bool "Platform has own custom IOCTL" + default n + +config U16550_REGINCR + int "Address increment between 16550 registers" + default 4 + ---help--- + The address increment between 16550 registers. Options are 1, 2, or 4. + Default: 1 + +config U16550_REGWIDTH + int "Bit width of 16550 registers" + default 32 + ---help--- + The bit width of registers. Options are 8, 16, or 32. Default: 8 + +config U16550_ADDRWIDTH + int "Address width of 16550 registers" + default 32 + ---help--- + The bit width of registers. Options are 0, 8, 16, or 32. + Default: 32 + Note: 0 means auto detect address size (uintptr_t) + +endif # U16550_UART diff --git a/Ubiquitous/Nuttx_Fusion_XiUOS/app_match_nuttx/nuttx/drivers/serial/Make.defs b/Ubiquitous/Nuttx_Fusion_XiUOS/app_match_nuttx/nuttx/drivers/serial/Make.defs new file mode 100755 index 000000000..4d828a625 --- /dev/null +++ b/Ubiquitous/Nuttx_Fusion_XiUOS/app_match_nuttx/nuttx/drivers/serial/Make.defs @@ -0,0 +1,57 @@ +############################################################################ +# drivers/serial/Make.defs +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################ + +# Include serial drivers + +CSRCS += serial.c serial_io.c + +ifeq ($(CONFIG_SERIAL_RXDMA),y) + CSRCS += serial_dma.c +else ifeq ($(CONFIG_SERIAL_TXDMA),y) + CSRCS += serial_dma.c +endif + +ifeq ($(CONFIG_U16550_UART),y) + CSRCS += uart_16550.c +endif + +ifeq ($(CONFIG_RPMSG_UART),y) + CSRCS += uart_rpmsg.c +endif + +# Pseudo-terminal support + +ifeq ($(CONFIG_PSEUDOTERM),y) + CSRCS += pty.c +ifeq ($(CONFIG_PSEUDOTERM_SUSV1),y) + CSRCS += ptmx.c +endif +endif + +# Bluetooth H:4 UART driver + +ifeq ($(CONFIG_UART_BTH4),y) + CSRCS += uart_bth4.c +endif + +# Include serial build support + +DEPPATH += --dep-path serial +VPATH += :serial diff --git a/Ubiquitous/Nuttx_Fusion_XiUOS/app_match_nuttx/nuttx/drivers/serial/uart_16550.c b/Ubiquitous/Nuttx_Fusion_XiUOS/app_match_nuttx/nuttx/drivers/serial/uart_16550.c new file mode 100755 index 000000000..a03ead794 --- /dev/null +++ b/Ubiquitous/Nuttx_Fusion_XiUOS/app_match_nuttx/nuttx/drivers/serial/uart_16550.c @@ -0,0 +1,1417 @@ +/**************************************************************************** + * drivers/serial/uart_16550.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/* Serial driver for 16550 UART */ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include + +//#include + +#ifdef CONFIG_U16550_UART + +/**************************************************************************** + * Pre-processor definitions + ****************************************************************************/ + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +static int u16550_setup(FAR struct uart_dev_s *dev); +static void u16550_shutdown(FAR struct uart_dev_s *dev); +static int u16550_attach(FAR struct uart_dev_s *dev); +static void u16550_detach(FAR struct uart_dev_s *dev); +static int u16550_interrupt(int irq, FAR void *context, FAR void *arg); +static int u16550_ioctl(FAR struct file *filep, int cmd, unsigned long arg); +static int u16550_receive(FAR struct uart_dev_s *dev, unsigned int *status); +static void u16550_rxint(FAR struct uart_dev_s *dev, bool enable); +static bool u16550_rxavailable(FAR struct uart_dev_s *dev); +#ifdef CONFIG_SERIAL_IFLOWCONTROL +static bool u16550_rxflowcontrol(struct uart_dev_s *dev, + unsigned int nbuffered, bool upper); +#endif +#ifdef CONFIG_SERIAL_TXDMA +static void u16550_dmasend(FAR struct uart_dev_s *dev); +static void u16550_dmatxavail(FAR struct uart_dev_s *dev); +#endif +#ifdef CONFIG_SERIAL_RXDMA +static void u16550_dmareceive(FAR struct uart_dev_s *dev); +static void u16550_dmarxfree(FAR struct uart_dev_s *dev); +#endif +static void u16550_send(FAR struct uart_dev_s *dev, int ch); +static void u16550_txint(FAR struct uart_dev_s *dev, bool enable); +static bool u16550_txready(FAR struct uart_dev_s *dev); +static bool u16550_txempty(FAR struct uart_dev_s *dev); + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +static const struct uart_ops_s g_uart_ops = +{ + .setup = u16550_setup, + .shutdown = u16550_shutdown, + .attach = u16550_attach, + .detach = u16550_detach, + .ioctl = u16550_ioctl, + .receive = u16550_receive, + .rxint = u16550_rxint, + .rxavailable = u16550_rxavailable, +#ifdef CONFIG_SERIAL_IFLOWCONTROL + .rxflowcontrol = u16550_rxflowcontrol, +#endif +#ifdef CONFIG_SERIAL_TXDMA + .dmasend = u16550_dmasend, +#endif +#ifdef CONFIG_SERIAL_RXDMA + .dmareceive = u16550_dmareceive, + .dmarxfree = u16550_dmarxfree, +#endif +#ifdef CONFIG_SERIAL_TXDMA + .dmatxavail = u16550_dmatxavail, +#endif + .send = u16550_send, + .txint = u16550_txint, + .txready = u16550_txready, + .txempty = u16550_txempty, +}; + +/* I/O buffers */ + +#ifdef CONFIG_U16550_UART0 +static char g_uart0rxbuffer[CONFIG_U16550_UART0_RXBUFSIZE]; +static char g_uart0txbuffer[CONFIG_U16550_UART0_TXBUFSIZE]; +#endif +#ifdef CONFIG_U16550_UART1 +static char g_uart1rxbuffer[CONFIG_U16550_UART1_RXBUFSIZE]; +static char g_uart1txbuffer[CONFIG_U16550_UART1_TXBUFSIZE]; +#endif +#ifdef CONFIG_U16550_UART2 +static char g_uart2rxbuffer[CONFIG_U16550_UART2_RXBUFSIZE]; +static char g_uart2txbuffer[CONFIG_U16550_UART2_TXBUFSIZE]; +#endif +#ifdef CONFIG_U16550_UART3 +static char g_uart3rxbuffer[CONFIG_U16550_UART3_RXBUFSIZE]; +static char g_uart3txbuffer[CONFIG_U16550_UART3_TXBUFSIZE]; +#endif + +/* This describes the state of the 16550 uart0 port. */ + +#ifdef CONFIG_U16550_UART0 +static struct u16550_s g_uart0priv = +{ + .uartbase = CONFIG_U16550_UART0_BASE, +#ifndef CONFIG_U16550_SUPRESS_CONFIG + .baud = CONFIG_U16550_UART0_BAUD, + .uartclk = CONFIG_U16550_UART0_CLOCK, +#endif + .irq = CONFIG_U16550_UART0_IRQ, +#ifndef CONFIG_U16550_SUPRESS_CONFIG + .parity = CONFIG_U16550_UART0_PARITY, + .bits = CONFIG_U16550_UART0_BITS, + .stopbits2 = CONFIG_U16550_UART0_2STOP, +#if defined(CONFIG_U16550_UART0_IFLOWCONTROL) || defined(CONFIG_U16550_UART0_OFLOWCONTROL) + .flow = true, +#endif +#endif +}; + +static uart_dev_t g_uart0port = +{ + .recv = + { + .size = CONFIG_U16550_UART0_RXBUFSIZE, + .buffer = g_uart0rxbuffer, + }, + .xmit = + { + .size = CONFIG_U16550_UART0_TXBUFSIZE, + .buffer = g_uart0txbuffer, + }, + .ops = &g_uart_ops, + .priv = &g_uart0priv, +}; +#endif + +/* This describes the state of the 16550 uart1 port. */ + +#ifdef CONFIG_U16550_UART1 +static struct u16550_s g_uart1priv = +{ + .uartbase = CONFIG_U16550_UART1_BASE, +#ifndef CONFIG_U16550_SUPRESS_CONFIG + .baud = CONFIG_U16550_UART1_BAUD, + .uartclk = CONFIG_U16550_UART1_CLOCK, +#endif + .irq = CONFIG_U16550_UART1_IRQ, +#ifndef CONFIG_U16550_SUPRESS_CONFIG + .parity = CONFIG_U16550_UART1_PARITY, + .bits = CONFIG_U16550_UART1_BITS, + .stopbits2 = CONFIG_U16550_UART1_2STOP, +#if defined(CONFIG_U16550_UART1_IFLOWCONTROL) || defined(CONFIG_U16550_UART1_OFLOWCONTROL) + .flow = true, +#endif +#endif +}; + +static uart_dev_t g_uart1port = +{ + .recv = + { + .size = CONFIG_U16550_UART1_RXBUFSIZE, + .buffer = g_uart1rxbuffer, + }, + .xmit = + { + .size = CONFIG_U16550_UART1_TXBUFSIZE, + .buffer = g_uart1txbuffer, + }, + .ops = &g_uart_ops, + .priv = &g_uart1priv, +}; +#endif + +/* This describes the state of the 16550 uart2 port. */ + +#ifdef CONFIG_U16550_UART2 +static struct u16550_s g_uart2priv = +{ + .uartbase = CONFIG_U16550_UART2_BASE, +#ifndef CONFIG_U16550_SUPRESS_CONFIG + .baud = CONFIG_U16550_UART2_BAUD, + .uartclk = CONFIG_U16550_UART2_CLOCK, +#endif + .irq = CONFIG_U16550_UART2_IRQ, +#ifndef CONFIG_U16550_SUPRESS_CONFIG + .parity = CONFIG_U16550_UART2_PARITY, + .bits = CONFIG_U16550_UART2_BITS, + .stopbits2 = CONFIG_U16550_UART2_2STOP, +#if defined(CONFIG_U16550_UART2_IFLOWCONTROL) || defined(CONFIG_U16550_UART2_OFLOWCONTROL) + .flow = true, +#endif +#endif +}; + +static uart_dev_t g_uart2port = +{ + .recv = + { + .size = CONFIG_U16550_UART2_RXBUFSIZE, + .buffer = g_uart2rxbuffer, + }, + .xmit = + { + .size = CONFIG_U16550_UART2_TXBUFSIZE, + .buffer = g_uart2txbuffer, + }, + .ops = &g_uart_ops, + .priv = &g_uart2priv, +}; + +#endif + +/* This describes the state of the 16550 uart1 port. */ + +#ifdef CONFIG_U16550_UART3 +static struct u16550_s g_uart3priv = +{ + .uartbase = CONFIG_U16550_UART3_BASE, +#ifndef CONFIG_U16550_SUPRESS_CONFIG + .baud = CONFIG_U16550_UART3_BAUD, + .uartclk = CONFIG_U16550_UART3_CLOCK, +#endif + .irq = CONFIG_U16550_UART3_IRQ, +#ifndef CONFIG_U16550_SUPRESS_CONFIG + .parity = CONFIG_U16550_UART3_PARITY, + .bits = CONFIG_U16550_UART3_BITS, + .stopbits2 = CONFIG_U16550_UART3_2STOP, +#if defined(CONFIG_U16550_UART3_IFLOWCONTROL) || defined(CONFIG_U16550_UART3_OFLOWCONTROL) + .flow = true, +#endif +#endif +}; + +static uart_dev_t g_uart3port = +{ + .recv = + { + .size = CONFIG_U16550_UART3_RXBUFSIZE, + .buffer = g_uart3rxbuffer, + }, + .xmit = + { + .size = CONFIG_U16550_UART3_TXBUFSIZE, + .buffer = g_uart3txbuffer, + }, + .ops = &g_uart_ops, + .priv = &g_uart3priv, +}; + +#endif + +/* Which UART with be tty0/console and which tty1? tty2? tty3? */ + +#ifdef CONFIG_U16550_SERIAL_DISABLE_REORDERING + +# if defined(CONFIG_U16550_UART0_SERIAL_CONSOLE) +# define CONSOLE_DEV g_uart0port /* UART0=console */ +# elif defined(CONFIG_U16550_UART1_SERIAL_CONSOLE) +# define CONSOLE_DEV g_uart1port /* UART1=console */ +# elif defined(CONFIG_U16550_UART2_SERIAL_CONSOLE) +# define CONSOLE_DEV g_uart2port /* UART2=console */ +# elif defined(CONFIG_U16550_UART3_SERIAL_CONSOLE) +# define CONSOLE_DEV g_uart3port /* UART3=console */ +# endif + +# ifdef CONFIG_U16550_UART0 +# define TTYS0_DEV g_uart0port +# endif + +# ifdef CONFIG_U16550_UART1 +# define TTYS1_DEV g_uart1port +# endif + +# ifdef CONFIG_U16550_UART2 +# define TTYS2_DEV g_uart2port +# endif + +# ifdef CONFIG_U16550_UART3 +# define TTYS3_DEV g_uart3port +# endif + +#else /* CONFIG_U16550_SERIAL_DISABLE_REORDERING */ + +/* Which UART with be tty0/console and which tty1? tty2? tty3? */ + +# if defined(CONFIG_U16550_UART0_SERIAL_CONSOLE) +# define CONSOLE_DEV g_uart0port /* UART0=console */ +# define TTYS0_DEV g_uart0port /* UART0=ttyS0 */ +# ifdef CONFIG_U16550_UART1 +# define TTYS1_DEV g_uart1port /* UART0=ttyS0;UART1=ttyS1 */ +# ifdef CONFIG_U16550_UART2 +# define TTYS2_DEV g_uart2port /* UART0=ttyS0;UART1=ttyS1;UART2=ttyS2 */ +# ifdef CONFIG_U16550_UART3 +# define TTYS3_DEV g_uart3port /* UART0=ttyS0;UART1=ttyS1;UART2=ttyS2;UART3=ttyS3 */ +# else +# undef TTYS3_DEV /* UART0=ttyS0;UART1=ttyS1;UART2=ttyS;No ttyS3 */ +# endif +# else +# ifdef CONFIG_U16550_UART3 +# define TTYS2_DEV g_uart3port /* UART0=ttyS0;UART1=ttyS1;UART3=ttys2;No ttyS3 */ +# else +# undef TTYS2_DEV /* UART0=ttyS0;UART1=ttyS1;No ttyS2;No ttyS3 */ +# endif +# undef TTYS3_DEV /* No ttyS3 */ +# endif +# else +# ifdef CONFIG_U16550_UART2 +# define TTYS1_DEV g_uart2port /* UART0=ttyS0;UART2=ttyS1;No ttyS3 */ +# ifdef CONFIG_U16550_UART3 +# define TTYS2_DEV g_uart3port /* UART0=ttyS0;UART2=ttyS1;UART3=ttyS2;No ttyS3 */ +# else +# undef TTYS2_DEV /* UART0=ttyS0;UART2=ttyS1;No ttyS2;No ttyS3 */ +# endif +# undef TTYS3_DEV /* No ttyS3 */ +# else +# ifdef CONFIG_U16550_UART3 +# define TTYS1_DEV g_uart3port /* UART0=ttyS0;UART3=ttyS1;No ttyS2;No ttyS3 */ +# else +# undef TTYS1_DEV /* UART0=ttyS0;No ttyS1;No ttyS2;No ttyS3 */ +# endif +# undef TTYS2_DEV /* No ttyS2 */ +# undef TTYS3_DEV /* No ttyS3 */ +# endif +# endif +# elif defined(CONFIG_U16550_UART1_SERIAL_CONSOLE) +# define CONSOLE_DEV g_uart1port /* UART1=console */ +# define TTYS0_DEV g_uart1port /* UART1=ttyS0 */ +# ifdef CONFIG_U16550_UART0 +# define TTYS1_DEV g_uart0port /* UART1=ttyS0;UART0=ttyS1 */ +# ifdef CONFIG_U16550_UART2 +# define TTYS2_DEV g_uart2port /* UART1=ttyS0;UART0=ttyS1;UART2=ttyS2 */ +# ifdef CONFIG_U16550_UART3 +# define TTYS3_DEV g_uart3port /* UART1=ttyS0;UART0=ttyS1;UART2=ttyS2;UART3=ttyS3 */ +# else +# undef TTYS3_DEV /* UART1=ttyS0;UART0=ttyS1;UART2=ttyS;No ttyS3 */ +# endif +# else +# ifdef CONFIG_U16550_UART3 +# define TTYS2_DEV g_uart3port /* UART1=ttyS0;UART0=ttyS1;UART3=ttys2;No ttyS3 */ +# else +# undef TTYS2_DEV /* UART1=ttyS0;UART0=ttyS1;No ttyS2;No ttyS3 */ +# endif +# undef TTYS3_DEV /* No ttyS3 */ +# endif +# else +# ifdef CONFIG_U16550_UART2 +# define TTYS1_DEV g_uart2port /* UART1=ttyS0;UART2=ttyS1 */ +# ifdef CONFIG_U16550_UART3 +# define TTYS2_DEV g_uart3port /* UART1=ttyS0;UART2=ttyS1;UART3=ttyS2;No ttyS3 */ +# else +# undef TTYS2_DEV /* UART1=ttyS0;UART2=ttyS1;No ttyS2;No ttyS3 */ +# endif +# undef TTYS3_DEV /* No ttyS3 */ +# else +# ifdef CONFIG_U16550_UART3 +# define TTYS1_DEV g_uart3port /* UART1=ttyS0;UART3=ttyS1;No ttyS2;No ttyS3 */ +# else +# undef TTYS1_DEV /* UART1=ttyS0;No ttyS1;No ttyS2;No ttyS3 */ +# endif +# undef TTYS2_DEV /* No ttyS2 */ +# undef TTYS3_DEV /* No ttyS3 */ +# endif +# endif +# elif defined(CONFIG_U16550_UART2_SERIAL_CONSOLE) +# define CONSOLE_DEV g_uart2port /* UART2=console */ +# define TTYS0_DEV g_uart2port /* UART2=ttyS0 */ +# ifdef CONFIG_U16550_UART0 +# define TTYS1_DEV g_uart0port /* UART2=ttyS0;UART0=ttyS1 */ +# ifdef CONFIG_U16550_UART1 +# define TTYS2_DEV g_uart1port /* UART2=ttyS0;UART0=ttyS1;UART1=ttyS2 */ +# ifdef CONFIG_U16550_UART3 +# define TTYS3_DEV g_uart3port /* UART2=ttyS0;UART0=ttyS1;UART1=ttyS2;UART3=ttyS3 */ +# else +# undef TTYS3_DEV /* UART2=ttyS0;UART0=ttyS1;UART1=ttyS;No ttyS3 */ +# endif +# else +# ifdef CONFIG_U16550_UART3 +# define TTYS2_DEV g_uart3port /* UART2=ttyS0;UART0=ttyS1;UART3=ttys2;No ttyS3 */ +# else +# undef TTYS2_DEV /* UART2=ttyS0;UART0=ttyS1;No ttyS2;No ttyS3 */ +# endif +# undef TTYS3_DEV /* No ttyS3 */ +# endif +# else +# ifdef CONFIG_U16550_UART1 +# define TTYS1_DEV g_uart1port /* UART2=ttyS0;UART1=ttyS1 */ +# ifdef CONFIG_U16550_UART3 +# define TTYS2_DEV g_uart3port /* UART2=ttyS0;UART1=ttyS1;UART3=ttyS2 */ +# else +# undef TTYS2_DEV /* UART2=ttyS0;UART1=ttyS1;No ttyS2;No ttyS3 */ +# endif +# undef TTYS3_DEV /* No ttyS3 */ +# else +# ifdef CONFIG_U16550_UART3 +# define TTYS1_DEV g_uart3port /* UART2=ttyS0;UART3=ttyS1;No ttyS3 */ +# else +# undef TTYS1_DEV /* UART2=ttyS0;No ttyS1;No ttyS2;No ttyS3 */ +# endif +# undef TTYS2_DEV /* No ttyS2 */ +# undef TTYS3_DEV /* No ttyS3 */ +# endif +# endif +# elif defined(CONFIG_U16550_UART3_SERIAL_CONSOLE) +# define CONSOLE_DEV g_uart3port /* UART3=console */ +# define TTYS0_DEV g_uart3port /* UART3=ttyS0 */ +# ifdef CONFIG_U16550_UART0 +# define TTYS1_DEV g_uart0port /* UART3=ttyS0;UART0=ttyS1 */ +# ifdef CONFIG_U16550_UART1 +# define TTYS2_DEV g_uart1port /* UART3=ttyS0;UART0=ttyS1;UART1=ttyS2 */ +# ifdef CONFIG_U16550_UART2 +# define TTYS3_DEV g_uart2port /* UART3=ttyS0;UART0=ttyS1;UART1=ttyS2;UART2=ttyS3 */ +# else +# undef TTYS3_DEV /* UART3=ttyS0;UART0=ttyS1;UART1=ttyS;No ttyS3 */ +# endif +# else +# ifdef CONFIG_U16550_UART2 +# define TTYS2_DEV g_uart2port /* UART3=ttyS0;UART0=ttyS1;UART2=ttys2;No ttyS3 */ +# else +# undef TTYS2_DEV /* UART3=ttyS0;UART0=ttyS1;No ttyS2;No ttyS3 */ +# endif +# undef TTYS3_DEV /* No ttyS3 */ +# endif +# else +# ifdef CONFIG_U16550_UART1 +# define TTYS1_DEV g_uart1port /* UART3=ttyS0;UART1=ttyS1 */ +# ifdef CONFIG_U16550_UART2 +# define TTYS2_DEV g_uart2port /* UART3=ttyS0;UART1=ttyS1;UART2=ttyS2;No ttyS3 */ +# else +# undef TTYS2_DEV /* UART3=ttyS0;UART1=ttyS1;No ttyS2;No ttyS3 */ +# endif +# undef TTYS3_DEV /* No ttyS3 */ +# else +# ifdef CONFIG_U16550_UART2 +# define TTYS1_DEV g_uart2port /* UART3=ttyS0;UART2=ttyS1;No ttyS3;No ttyS3 */ +# undef TTYS3_DEV /* UART3=ttyS0;UART2=ttyS1;No ttyS2;No ttyS3 */ +# else +# undef TTYS1_DEV /* UART3=ttyS0;No ttyS1;No ttyS2;No ttyS3 */ +# endif +# undef TTYS2_DEV /* No ttyS2 */ +# undef TTYS3_DEV /* No ttyS3 */ +# endif +# endif +# endif + +#endif /* CONFIG_U16550_SERIAL_DISABLE_REORDERING */ + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: u16550_serialin + ****************************************************************************/ + +static inline uart_datawidth_t u16550_serialin(FAR struct u16550_s *priv, + int offset) +{ +#ifdef CONFIG_SERIAL_UART_ARCH_MMIO + return *((FAR volatile uart_datawidth_t *)(priv->uartbase + offset)); +#else + return uart_getreg(priv->uartbase, offset); +#endif +} + +/**************************************************************************** + * Name: u16550_serialout + ****************************************************************************/ + +static inline void u16550_serialout(FAR struct u16550_s *priv, int offset, + uart_datawidth_t value) +{ +#ifdef CONFIG_SERIAL_UART_ARCH_MMIO + *((FAR volatile uart_datawidth_t *)(priv->uartbase + offset)) = value; +#else + uart_putreg(priv->uartbase, offset, value); +#endif +} + +/**************************************************************************** + * Name: u16550_disableuartint + ****************************************************************************/ + +static inline void u16550_disableuartint(FAR struct u16550_s *priv, + FAR uart_datawidth_t *ier) +{ + if (ier) + { + *ier = priv->ier & UART_IER_ALLIE; + } + + priv->ier &= ~UART_IER_ALLIE; + u16550_serialout(priv, UART_IER_OFFSET, priv->ier); +} + +/**************************************************************************** + * Name: u16550_restoreuartint + ****************************************************************************/ + +static inline void u16550_restoreuartint(FAR struct u16550_s *priv, + uint32_t ier) +{ + priv->ier |= ier & UART_IER_ALLIE; + u16550_serialout(priv, UART_IER_OFFSET, priv->ier); +} + +/**************************************************************************** + * Name: u16550_enablebreaks + ****************************************************************************/ + +static inline void u16550_enablebreaks(FAR struct u16550_s *priv, + bool enable) +{ + uint32_t lcr = u16550_serialin(priv, UART_LCR_OFFSET); + + if (enable) + { + lcr |= UART_LCR_BRK; + } + else + { + lcr &= ~UART_LCR_BRK; + } + + u16550_serialout(priv, UART_LCR_OFFSET, lcr); +} + +/**************************************************************************** + * Name: u16550_divisor + * + * Description: + * Select a divider to produce the BAUD from the UART_CLK. + * + * BAUD = UART_CLK / (16 * DL), or + * DIV = UART_CLK / BAUD / 16 + * + * Ignoring the fractional divider for now. + * + ****************************************************************************/ + +#ifndef CONFIG_U16550_SUPRESS_CONFIG +static inline uint32_t u16550_divisor(FAR struct u16550_s *priv) +{ + return (priv->uartclk / (uint32_t)priv->baud); +// return (priv->uartclk + (priv->baud << 3)) / (priv->baud << 4); +} +#endif + +static bool u16550_irq_flag = 0; +/**************************************************************************** + * Name: u16550_setup + * + * Description: + * Configure the UART baud, bits, parity, fifos, etc. This + * method is called the first time that the serial port is + * opened. + * + ****************************************************************************/ + +static int u16550_setup(FAR struct uart_dev_s *dev) +{ +#ifndef CONFIG_U16550_SUPRESS_CONFIG + FAR struct u16550_s *priv = (FAR struct u16550_s *)dev->priv; + uint16_t div; + uint8_t dlh, dll, dlf; + uint32_t lcr; +#if defined(CONFIG_SERIAL_IFLOWCONTROL) || defined(CONFIG_SERIAL_OFLOWCONTROL) + uint32_t mcr; +#endif + + /* Clear fifos */ + + u16550_serialout(priv, UART_FCR_OFFSET, + (UART_FCR_RXRST | UART_FCR_TXRST)); + + /* Set trigger */ + + u16550_serialout(priv, UART_FCR_OFFSET, + (UART_FCR_FIFOEN | UART_FCR_RXTRIGGER_8)); + + /* Set up the IER */ + + priv->ier = u16550_serialin(priv, UART_IER_OFFSET); + + /* Set up the LCR */ + + lcr = 0; + switch (priv->bits) + { + case 5 : + lcr |= UART_LCR_WLS_5BIT; + break; + + case 6 : + lcr |= UART_LCR_WLS_6BIT; + break; + + case 7 : + lcr |= UART_LCR_WLS_7BIT; + break; + + default: + case 8 : + lcr |= UART_LCR_WLS_8BIT; + break; + } + + if (priv->stopbits2) + { + lcr |= UART_LCR_STB; + } + + if (priv->parity == 1) + { + lcr |= UART_LCR_PEN; + } + else if (priv->parity == 2) + { + lcr |= (UART_LCR_PEN | UART_LCR_EPS); + } + + /* Enter DLAB=1 */ + + u16550_serialout(priv, UART_LCR_OFFSET, (lcr | UART_LCR_DLAB)); + + /* Set the BAUD divisor */ + + div = u16550_divisor(priv); + dlh = div >> 12; + dll = (div - (dlh << 12)) / 16; + dlf = div - (dlh << 12) - dll * 16; + + u16550_serialout(priv, UART_DLM_OFFSET, dlh); + u16550_serialout(priv, UART_DLL_OFFSET, dll); + u16550_serialout(priv, UART_DLF_OFFSET, dlf); + + /* Clear DLAB */ + + u16550_serialout(priv, UART_LCR_OFFSET, lcr); + + /* Configure the FIFOs */ + + u16550_serialout(priv, UART_FCR_OFFSET, + (UART_FCR_RXTRIGGER_8 | UART_FCR_TXRST | UART_FCR_RXRST | + UART_FCR_FIFOEN)); + + /* Set up the auto flow control */ + +#if defined(CONFIG_SERIAL_IFLOWCONTROL) || defined(CONFIG_SERIAL_OFLOWCONTROL) + mcr = u16550_serialin(priv, UART_MCR_OFFSET); + if (priv->flow) + { + mcr |= UART_MCR_AFCE; + } + else + { + mcr &= ~UART_MCR_AFCE; + } + + mcr |= UART_MCR_RTS; + + u16550_serialout(priv, UART_MCR_OFFSET, mcr); + + u16550_serialout(priv, UART_SRT_OFFSET, 0x0); + +#endif /* defined(CONFIG_SERIAL_IFLOWCONTROL) || defined(CONFIG_SERIAL_OFLOWCONTROL) */ + +#endif + return OK; +} + +/**************************************************************************** + * Name: u16550_shutdown + * + * Description: + * Disable the UART. This method is called when the serial + * port is closed + * + ****************************************************************************/ + +static void u16550_shutdown(struct uart_dev_s *dev) +{ + FAR struct u16550_s *priv = (FAR struct u16550_s *)dev->priv; + u16550_disableuartint(priv, NULL); +} + +/**************************************************************************** + * Name: u16550_attach + * + * Description: + * Configure the UART to operation in interrupt driven mode. This method + * is called when the serial port is opened. Normally, this is just after + * the setup() method is called, however, the serial console may operate in + * a non-interrupt driven mode during the boot phase. + * + * RX and TX interrupts are not enabled when by the attach method (unless + * the hardware supports multiple levels of interrupt enabling). The RX + * and TX interrupts are not enabled until the txint() and rxint() methods + * are called. + * + ****************************************************************************/ + +static int u16550_attach(struct uart_dev_s *dev) +{ + FAR struct u16550_s *priv = (FAR struct u16550_s *)dev->priv; + int ret; + + /* Attach and enable the IRQ */ + + ret = irq_attach(priv->irq, u16550_interrupt, dev); +#ifndef CONFIG_ARCH_NOINTC + if (ret == OK) + { + /* Enable the interrupt (RX and TX interrupts are still disabled + * in the UART + */ + + up_enable_irq(priv->irq); + } +#endif + + return ret; +} + +/**************************************************************************** + * Name: u16550_detach + * + * Description: + * Detach UART interrupts. This method is called when the serial port is + * closed normally just before the shutdown method is called. + * The exception is the serial console which is never shutdown. + * + ****************************************************************************/ + +static void u16550_detach(FAR struct uart_dev_s *dev) +{ + FAR struct u16550_s *priv = (FAR struct u16550_s *)dev->priv; + + up_disable_irq(priv->irq); + irq_detach(priv->irq); +} + +/**************************************************************************** + * Name: u16550_notify + * + * Description: + * Detach UART interrupts. This method is called when the serial port need + * to notify other process received data + * + ****************************************************************************/ + +static void u16550_notify(FAR struct uart_dev_s *dev) +{ +#ifdef CONFIG_BSP_USING_CH376 + ch376_notify(dev); +#endif +#ifdef CONFIG_BSP_USING_EC200 + ec200_notify(dev); +#endif +#ifdef CONFIG_BSP_USING_CAN + extern void can_notify(uart_dev_t *dev); + can_notify(dev); +#endif +#ifdef CONFIG_BSP_USING_ESP8266 + extern void esp8266_notify(uart_dev_t *dev); + esp8266_notify(dev); +#endif +} + +/**************************************************************************** + * Name: u16550_interrupt + * + * Description: + * This is the UART interrupt handler. It will be invoked when an + * interrupt received on the 'irq' It should call uart_transmitchars or + * uart_receivechar to perform the appropriate data transfers. The + * interrupt handling logic must be able to map the 'irq' number into the + * appropriate u16550_s structure in order to call these functions. + * + ****************************************************************************/ + +static int u16550_interrupt(int irq, FAR void *context, FAR void *arg) +{ + FAR struct uart_dev_s *dev = (struct uart_dev_s *)arg; + FAR struct u16550_s *priv; + uint32_t status; + int passes; + + DEBUGASSERT(dev != NULL && dev->priv != NULL); + priv = (FAR struct u16550_s *)dev->priv; + + /* Loop until there are no characters to be transferred or, + * until we have been looping for a long time. + */ + + for (passes = 0; passes < 256; passes++) + { + /* Get the current UART status and check for loop + * termination conditions + */ + + status = u16550_serialin(priv, UART_IIR_OFFSET); + + /* The UART_IIR_INTSTATUS bit should be zero if there are pending + * interrupts + */ + + if ((status & UART_IIR_INTSTATUS) != 0) + { + /* Break out of the loop when there is no longer a + * pending interrupt + */ + + break; + } + + /* Handle the interrupt by its interrupt ID field */ + + switch (status & UART_IIR_INTID_MASK) + { + /* Handle incoming, receive bytes (with or without timeout) */ + + case UART_IIR_INTID_RDA: + case UART_IIR_INTID_CTI: + { + uart_recvchars(dev); + u16550_notify(dev); + break; + } + + /* Handle outgoing, transmit bytes */ + + case UART_IIR_INTID_THRE: + { + //for txready failure + u16550_irq_flag = 1; + uart_xmitchars(dev); + u16550_irq_flag = 0; + break; + } + + /* Just clear modem status interrupts (UART1 only) */ + + case UART_IIR_INTID_MSI: + { + /* Read the modem status register (MSR) to clear */ + + status = u16550_serialin(priv, UART_MSR_OFFSET); + sinfo("MSR: %02"PRIx32"\n", status); + break; + } + + /* Just clear any line status interrupts */ + + case UART_IIR_INTID_RLS: + { + /* Read the line status register (LSR) to clear */ + + status = u16550_serialin(priv, UART_LSR_OFFSET); + sinfo("LSR: %02"PRIx32"\n", status); + break; + } + + /* There should be no other values */ + + default: + { + serr("ERROR: Unexpected IIR: %02"PRIx32"\n", status); + break; + } + } + } + + return OK; +} + +/**************************************************************************** + * Name: u16550_ioctl + * + * Description: + * All ioctl calls will be routed through this method + * + ****************************************************************************/ + +static int u16550_ioctl(struct file *filep, int cmd, unsigned long arg) +{ + FAR struct inode *inode = filep->f_inode; + FAR struct uart_dev_s *dev = inode->i_private; + FAR struct u16550_s *priv = (FAR struct u16550_s *)dev->priv; + int ret; + +#ifdef CONFIG_SERIAL_UART_ARCH_IOCTL + ret = uart_ioctl(filep, cmd, arg); + + if (ret != -ENOTTY) + { + return ret; + } + +#else + ret = OK; +#endif + + switch (cmd) + { +#ifdef CONFIG_SERIAL_TIOCSERGSTRUCT + case TIOCSERGSTRUCT: + { + FAR struct u16550_s *user = (FAR struct u16550_s *)arg; + if (!user) + { + ret = -EINVAL; + } + else + { + memcpy(user, dev, sizeof(struct u16550_s)); + } + } + break; +#endif + + case TIOCSBRK: /* BSD compatibility: Turn break on, unconditionally */ + { + irqstate_t flags = enter_critical_section(); + u16550_enablebreaks(priv, true); + leave_critical_section(flags); + } + break; + + case TIOCCBRK: /* BSD compatibility: Turn break off, unconditionally */ + { + irqstate_t flags; + flags = enter_critical_section(); + u16550_enablebreaks(priv, false); + leave_critical_section(flags); + } + break; + +#if defined(CONFIG_SERIAL_TERMIOS) && !defined(CONFIG_U16550_SUPRESS_CONFIG) + case TCGETS: + { + FAR struct termios *termiosp = (FAR struct termios *)arg; + irqstate_t flags; + + if (!termiosp) + { + ret = -EINVAL; + break; + } + + flags = enter_critical_section(); + + cfsetispeed(termiosp, priv->baud); + termiosp->c_cflag = ((priv->parity != 0) ? PARENB : 0) | + ((priv->parity == 1) ? PARODD : 0); + termiosp->c_cflag |= (priv->stopbits2) ? CSTOPB : 0; +#if defined(CONFIG_SERIAL_IFLOWCONTROL) || defined(CONFIG_SERIAL_OFLOWCONTROL) + termiosp->c_cflag |= priv->flow ? CRTSCTS : 0; +#endif + + switch (priv->bits) + { + case 5: + termiosp->c_cflag |= CS5; + break; + + case 6: + termiosp->c_cflag |= CS6; + break; + + case 7: + termiosp->c_cflag |= CS7; + break; + + case 8: + default: + termiosp->c_cflag |= CS8; + break; + } + + leave_critical_section(flags); + } + break; + + case TCSETS: + { + FAR struct termios *termiosp = (FAR struct termios *)arg; + irqstate_t flags; + + if (!termiosp) + { + ret = -EINVAL; + break; + } + + flags = enter_critical_section(); + + switch (termiosp->c_cflag & CSIZE) + { + case CS5: + priv->bits = 5; + break; + + case CS6: + priv->bits = 6; + break; + + case CS7: + priv->bits = 7; + break; + + case CS8: + default: + priv->bits = 8; + break; + } + + if ((termiosp->c_cflag & PARENB) != 0) + { + priv->parity = (termiosp->c_cflag & PARODD) ? 1 : 2; + } + else + { + priv->parity = 0; + } + + priv->baud = cfgetispeed(termiosp); + priv->stopbits2 = (termiosp->c_cflag & CSTOPB) != 0; +#if defined(CONFIG_SERIAL_IFLOWCONTROL) || defined(CONFIG_SERIAL_OFLOWCONTROL) + priv->flow = (termiosp->c_cflag & CRTSCTS) != 0; +#endif + + u16550_setup(dev); + leave_critical_section(flags); + } + break; +#endif + + default: + ret = -ENOTTY; + break; + } + + return ret; +} + +/**************************************************************************** + * Name: u16550_receive + * + * Description: + * Called (usually) from the interrupt level to receive one + * character from the UART. Error bits associated with the + * receipt are provided in the return 'status'. + * + ****************************************************************************/ + +static int u16550_receive(struct uart_dev_s *dev, unsigned int *status) +{ + FAR struct u16550_s *priv = (FAR struct u16550_s *)dev->priv; + uint32_t rbr = 0; + *status = u16550_serialin(priv, UART_LSR_OFFSET); + rbr = u16550_serialin(priv, UART_RBR_OFFSET); + return rbr; +} + +/**************************************************************************** + * Name: u16550_rxint + * + * Description: + * Call to enable or disable RX interrupts + * + ****************************************************************************/ + +static void u16550_rxint(struct uart_dev_s *dev, bool enable) +{ + FAR struct u16550_s *priv = (FAR struct u16550_s *)dev->priv; + + if (enable) + { + priv->ier |= UART_IER_ERBFI; + } + else + { + priv->ier &= ~UART_IER_ERBFI; + } + + u16550_serialout(priv, UART_IER_OFFSET, priv->ier); +} + +/**************************************************************************** + * Name: u16550_rxavailable + * + * Description: + * Return true if the receive fifo is not empty + * + ****************************************************************************/ + +static bool u16550_rxavailable(struct uart_dev_s *dev) +{ + FAR struct u16550_s *priv = (FAR struct u16550_s *)dev->priv; + return ((u16550_serialin(priv, UART_LSR_OFFSET) & UART_LSR_DR) != 0); +} + +/**************************************************************************** + * Name: u16550_dma* + * + * Description: + * Stubbed out DMA-related methods + * + ****************************************************************************/ + +#ifdef CONFIG_SERIAL_IFLOWCONTROL +static bool u16550_rxflowcontrol(struct uart_dev_s *dev, + unsigned int nbuffered, bool upper) +{ +#ifndef CONFIG_U16550_SUPRESS_CONFIG + FAR struct u16550_s *priv = (FAR struct u16550_s *)dev->priv; + + if (priv->flow) + { + /* Disable Rx interrupt to prevent more data being from + * peripheral if the RX buffer is near full. When hardware + * RTS is enabled, this will prevent more data from coming + * in. Otherwise, enable Rx interrupt to make sure that more + * input is received. + */ + + u16550_rxint(dev, !upper); + return true; + } +#endif + + return false; +} +#endif + +/**************************************************************************** + * Name: u16550_dma* + * + * Description: + * Stub functions used when serial DMA is enabled. + * + ****************************************************************************/ + +#ifdef CONFIG_SERIAL_TXDMA +static void u16550_dmasend(FAR struct uart_dev_s *dev) +{ +} +#endif + +#ifdef CONFIG_SERIAL_RXDMA +static void u16550_dmareceive(FAR struct uart_dev_s *dev) +{ +} + +static void u16550_dmarxfree(FAR struct uart_dev_s *dev) +{ +} +#endif + +#ifdef CONFIG_SERIAL_TXDMA +static void u16550_dmatxavail(FAR struct uart_dev_s *dev) +{ +} +#endif + +/**************************************************************************** + * Name: u16550_send + * + * Description: + * This method will send one byte on the UART + * + ****************************************************************************/ + +static void u16550_send(struct uart_dev_s *dev, int ch) +{ + FAR struct u16550_s *priv = (FAR struct u16550_s *)dev->priv; + u16550_serialout(priv, UART_THR_OFFSET, (uart_datawidth_t)ch); +} + +/**************************************************************************** + * Name: u16550_txint + * + * Description: + * Call to enable or disable TX interrupts + * + ****************************************************************************/ + +static void u16550_txint(struct uart_dev_s *dev, bool enable) +{ + FAR struct u16550_s *priv = (FAR struct u16550_s *)dev->priv; + irqstate_t flags; + + flags = enter_critical_section(); + if (enable) + { + priv->ier |= UART_IER_ETBEI; + u16550_serialout(priv, UART_IER_OFFSET, priv->ier); + + /* Fake a TX interrupt here by just calling uart_xmitchars() with + * interrupts disabled (note this may recurse). + */ + + uart_xmitchars(dev); + } + else + { + priv->ier &= ~UART_IER_ETBEI; + u16550_serialout(priv, UART_IER_OFFSET, priv->ier); + } + + leave_critical_section(flags); +} + +/**************************************************************************** + * Name: u16550_txready + * + * Description: + * Return true if the tranmsit fifo is not full + * + ****************************************************************************/ + +static bool u16550_txready(struct uart_dev_s *dev) +{ + FAR struct u16550_s *priv = (FAR struct u16550_s *)dev->priv; + return (((u16550_serialin(priv, UART_LSR_OFFSET) & UART_LSR_THRE) != 0) || u16550_irq_flag); +} + +/**************************************************************************** + * Name: u16550_txempty + * + * Description: + * Return true if the transmit fifo is empty + * + ****************************************************************************/ + +static bool u16550_txempty(struct uart_dev_s *dev) +{ + FAR struct u16550_s *priv = (FAR struct u16550_s *)dev->priv; + return ((u16550_serialin(priv, UART_LSR_OFFSET) & UART_LSR_TEMT) != 0); +} + +/**************************************************************************** + * Name: u16550_putc + * + * Description: + * Write one character to the UART (polled) + * + ****************************************************************************/ + +#ifdef HAVE_16550_CONSOLE +static void u16550_putc(FAR struct u16550_s *priv, int ch) +{ + while ((u16550_serialin(priv, UART_LSR_OFFSET) & UART_LSR_THRE) == 0); + u16550_serialout(priv, UART_THR_OFFSET, (uart_datawidth_t)ch); +} +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: up_earlyserialinit + * + * Description: + * Performs the low level UART initialization early in debug so that the + * serial console will be available during bootup. This must be called + * before uart_serialinit. + * + * NOTE: Configuration of the CONSOLE UART was performed by uart_lowsetup() + * very early in the boot sequence. + * + ****************************************************************************/ + +void up_earlyserialinit(void) +{ + /* Configuration whichever one is the console */ + +#ifdef CONSOLE_DEV + CONSOLE_DEV.isconsole = true; +#ifndef CONFIG_U16550_SUPRESS_INITIAL_CONFIG + u16550_setup(&CONSOLE_DEV); +#endif +#endif +} + +/**************************************************************************** + * Name: up_serialinit + * + * Description: + * Register serial console and serial ports. This assumes that + * up_earlyserialinit was called previously. + * + ****************************************************************************/ + +void up_serialinit(void) +{ +#ifdef CONSOLE_DEV + uart_register("/dev/console", &CONSOLE_DEV); +#endif +#ifdef TTYS0_DEV + uart_register("/dev/ttyS0", &TTYS0_DEV); +#endif +#ifdef TTYS1_DEV + uart_register("/dev/ttyS1", &TTYS1_DEV); +#endif +#ifdef TTYS2_DEV + uart_register("/dev/ttyS2", &TTYS2_DEV); +#endif +#ifdef TTYS3_DEV + uart_register("/dev/ttyS3", &TTYS3_DEV); +#endif +} + +void u16550_register(uart_dev_t **dev, int uart_index) +{ + switch(uart_index) + { + case 1: +#if defined(CONFIG_U16550_UART1) + u16550_setup(&g_uart1port); + uart_register("/dev/uart1", &g_uart1port); + *dev = &g_uart1port; +#endif + break; + case 2: +#if defined(CONFIG_U16550_UART2) + u16550_setup(&g_uart2port); + uart_register("/dev/uart2", &g_uart2port); + *dev = &g_uart2port; +#endif + break; + case 3: +#if defined(CONFIG_U16550_UART3) + u16550_setup(&g_uart3port); + uart_register("/dev/uart3", &g_uart3port); + *dev = &g_uart3port; +#endif + break; + default: + serr("UART%d not Supported!\n", uart_index); + break; + } +} + +/**************************************************************************** + * Name: up_putc + * + * Description: + * Provide priority, low-level access to support OS debug writes + * + ****************************************************************************/ + +#ifdef HAVE_16550_CONSOLE +int up_putc(int ch) +{ + FAR struct u16550_s *priv = (FAR struct u16550_s *)CONSOLE_DEV.priv; + uart_datawidth_t ier; + + u16550_disableuartint(priv, &ier); + + /* Check for LF */ + + if (ch == '\n') + { + /* Add CR */ + + u16550_putc(priv, '\r'); + } + + u16550_putc(priv, ch); + u16550_restoreuartint(priv, ier); + return ch; +} +#endif + +#endif /* CONFIG_U16550_UART */ diff --git a/Ubiquitous/Nuttx_Fusion_XiUOS/app_match_nuttx/nuttx/include/nuttx/serial/uart_16550.h b/Ubiquitous/Nuttx_Fusion_XiUOS/app_match_nuttx/nuttx/include/nuttx/serial/uart_16550.h new file mode 100755 index 000000000..115da93a9 --- /dev/null +++ b/Ubiquitous/Nuttx_Fusion_XiUOS/app_match_nuttx/nuttx/include/nuttx/serial/uart_16550.h @@ -0,0 +1,380 @@ +/**************************************************************************** + * include/nuttx/serial/uart_16550.h + * Serial driver for 16550 UART + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __INCLUDE_NUTTX_SERIAL_UART_16550_H +#define __INCLUDE_NUTTX_SERIAL_UART_16550_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#ifdef CONFIG_U16550_UART + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* CONFIGURATION ************************************************************/ + +/* Are any UARTs enabled? */ + +#undef HAVE_UART +#if defined(CONFIG_U16550_UART0) || defined(CONFIG_U16550_UART1) || \ + defined(CONFIG_U16550_UART2) || defined(CONFIG_U16550_UART3) +# define HAVE_UART 1 +#endif + +/* We need to be told the address increment between registers and the + * register bit width. + */ + +#ifndef CONFIG_U16550_REGINCR +# error "CONFIG_U16550_REGINCR not defined" +#endif + +#if CONFIG_U16550_REGINCR != 1 && CONFIG_U16550_REGINCR != 2 && CONFIG_U16550_REGINCR != 4 +# error "CONFIG_U16550_REGINCR not supported" +#endif + +#ifndef CONFIG_U16550_REGWIDTH +# error "CONFIG_U16550_REGWIDTH not defined" +#endif + +#if CONFIG_U16550_REGWIDTH != 8 && CONFIG_U16550_REGWIDTH != 16 && CONFIG_U16550_REGWIDTH != 32 +# error "CONFIG_U16550_REGWIDTH not supported" +#endif + +#ifndef CONFIG_U16550_ADDRWIDTH +# error "CONFIG_U16550_ADDRWIDTH not defined" +#endif + +#if CONFIG_U16550_ADDRWIDTH != 0 && CONFIG_U16550_ADDRWIDTH != 8 && \ + CONFIG_U16550_ADDRWIDTH != 16 && CONFIG_U16550_ADDRWIDTH != 32 && \ + CONFIG_U16550_ADDRWIDTH != 64 +# error "CONFIG_U16550_ADDRWIDTH not supported" +#endif + +/* If a UART is enabled, then its base address, clock, and IRQ + * must also be provided + */ + +#ifdef CONFIG_U16550_UART0 +# ifndef CONFIG_U16550_UART0_BASE +# error "CONFIG_U16550_UART0_BASE not provided" +# undef CONFIG_U16550_UART0 +# endif +# ifndef CONFIG_U16550_UART0_CLOCK +# error "CONFIG_U16550_UART0_CLOCK not provided" +# undef CONFIG_U16550_UART0 +# endif +# ifndef CONFIG_U16550_UART0_IRQ +# error "CONFIG_U16550_UART0_IRQ not provided" +# undef CONFIG_U16550_UART0 +# endif +#endif + +#ifdef CONFIG_U16550_UART1 +# ifndef CONFIG_U16550_UART1_BASE +# error "CONFIG_U16550_UART1_BASE not provided" +# undef CONFIG_U16550_UART1 +# endif +# ifndef CONFIG_U16550_UART1_CLOCK +# error "CONFIG_U16550_UART1_CLOCK not provided" +# undef CONFIG_U16550_UART1 +# endif +# ifndef CONFIG_U16550_UART1_IRQ +# error "CONFIG_U16550_UART1_IRQ not provided" +# undef CONFIG_U16550_UART1 +# endif +#endif + +#ifdef CONFIG_U16550_UART2 +# ifndef CONFIG_U16550_UART2_BASE +# error "CONFIG_U16550_UART2_BASE not provided" +# undef CONFIG_U16550_UART2 +# endif +# ifndef CONFIG_U16550_UART2_CLOCK +# error "CONFIG_U16550_UART2_CLOCK not provided" +# undef CONFIG_U16550_UART2 +# endif +# ifndef CONFIG_U16550_UART2_IRQ +# error "CONFIG_U16550_UART2_IRQ not provided" +# undef CONFIG_U16550_UART2 +# endif +#endif + +#ifdef CONFIG_U16550_UART3 +# ifndef CONFIG_U16550_UART3_BASE +# error "CONFIG_U16550_UART3_BASE not provided" +# undef CONFIG_U16550_UART3 +# endif +# ifndef CONFIG_U16550_UART3_CLOCK +# error "CONFIG_U16550_UART3_CLOCK not provided" +# undef CONFIG_U16550_UART3 +# endif +# ifndef CONFIG_U16550_UART3_IRQ +# error "CONFIG_U16550_UART3_IRQ not provided" +# undef CONFIG_U16550_UART3 +# endif +#endif + +/* Is there a serial console? There should be at most one defined. + * It could be on any UARTn, n=0,1,2,3 + */ + +#if defined(CONFIG_U16550_UART0_SERIAL_CONSOLE) && defined(CONFIG_U16550_UART0) +# undef CONFIG_U16550_UART1_SERIAL_CONSOLE +# undef CONFIG_U16550_UART2_SERIAL_CONSOLE +# undef CONFIG_U16550_UART3_SERIAL_CONSOLE +# define HAVE_16550_CONSOLE 1 +#elif defined(CONFIG_U16550_UART1_SERIAL_CONSOLE) && defined(CONFIG_U16550_UART1) +# undef CONFIG_U16550_UART0_SERIAL_CONSOLE +# undef CONFIG_U16550_UART2_SERIAL_CONSOLE +# undef CONFIG_U16550_UART3_SERIAL_CONSOLE +# define HAVE_16550_CONSOLE 1 +#elif defined(CONFIG_U16550_UART2_SERIAL_CONSOLE) && defined(CONFIG_U16550_UART2) +# undef CONFIG_U16550_UART0_SERIAL_CONSOLE +# undef CONFIG_U16550_UART1_SERIAL_CONSOLE +# undef CONFIG_U16550_UART3_SERIAL_CONSOLE +# define HAVE_16550_CONSOLE 1 +#elif defined(CONFIG_U16550_UART3_SERIAL_CONSOLE) && defined(CONFIG_U16550_UART3) +# undef CONFIG_U16550_UART0_SERIAL_CONSOLE +# undef CONFIG_U16550_UART1_SERIAL_CONSOLE +# undef CONFIG_U16550_UART2_SERIAL_CONSOLE +# define HAVE_16550_CONSOLE 1 +#else +# undef CONFIG_U16550_UART0_SERIAL_CONSOLE +# undef CONFIG_U16550_UART1_SERIAL_CONSOLE +# undef CONFIG_U16550_UART2_SERIAL_CONSOLE +# undef CONFIG_U16550_UART3_SERIAL_CONSOLE +# undef HAVE_16550_CONSOLE +#endif + +/* Register offsets *********************************************************/ + +#define UART_RBR_INCR 0 /* (DLAB =0) Receiver Buffer Register */ +#define UART_THR_INCR 0 /* (DLAB =0) Transmit Holding Register */ +#define UART_DLL_INCR 0 /* (DLAB =1) Divisor Latch LSB */ +#define UART_DLM_INCR 1 /* (DLAB =1) Divisor Latch MSB */ +#define UART_IER_INCR 1 /* (DLAB =0) Interrupt Enable Register */ +#define UART_IIR_INCR 2 /* Interrupt ID Register */ +#define UART_FCR_INCR 2 /* FIFO Control Register */ +#define UART_LCR_INCR 3 /* Line Control Register */ +#define UART_MCR_INCR 4 /* Modem Control Register */ +#define UART_LSR_INCR 5 /* Line Status Register */ +#define UART_MSR_INCR 6 /* Modem Status Register */ +#define UART_SCR_INCR 7 /* Scratch Pad Register */ +#define UART_SRT_INCR 39 /* Receive Fifo Trigger Register*/ +#define UART_DLF_INCR 48 /* Divisor factor Register*/ +#define UART_CPR_INCR 61 /* Component Register */ + +#define UART_RBR_OFFSET (CONFIG_U16550_REGINCR*UART_RBR_INCR) +#define UART_THR_OFFSET (CONFIG_U16550_REGINCR*UART_THR_INCR) +#define UART_DLL_OFFSET (CONFIG_U16550_REGINCR*UART_DLL_INCR) +#define UART_DLM_OFFSET (CONFIG_U16550_REGINCR*UART_DLM_INCR) +#define UART_IER_OFFSET (CONFIG_U16550_REGINCR*UART_IER_INCR) +#define UART_IIR_OFFSET (CONFIG_U16550_REGINCR*UART_IIR_INCR) +#define UART_FCR_OFFSET (CONFIG_U16550_REGINCR*UART_FCR_INCR) +#define UART_LCR_OFFSET (CONFIG_U16550_REGINCR*UART_LCR_INCR) +#define UART_MCR_OFFSET (CONFIG_U16550_REGINCR*UART_MCR_INCR) +#define UART_LSR_OFFSET (CONFIG_U16550_REGINCR*UART_LSR_INCR) +#define UART_MSR_OFFSET (CONFIG_U16550_REGINCR*UART_MSR_INCR) +#define UART_SCR_OFFSET (CONFIG_U16550_REGINCR*UART_SCR_INCR) +#define UART_SRT_OFFSET (CONFIG_U16550_REGINCR*UART_SRT_INCR) +#define UART_DLF_OFFSET (CONFIG_U16550_REGINCR*UART_DLF_INCR) +#define UART_CPR_OFFSET (CONFIG_U16550_REGINCR*UART_CPR_INCR) + +/* Register bit definitions *************************************************/ + +/* RBR (DLAB =0) Receiver Buffer Register */ + +#define UART_RBR_MASK (0xff) /* Bits 0-7: Oldest received byte in RX FIFO */ + /* Bits 8-31: Reserved */ + +/* THR (DLAB =0) Transmit Holding Register */ + +#define UART_THR_MASK (0xff) /* Bits 0-7: Adds byte to TX FIFO */ + /* Bits 8-31: Reserved */ + +/* DLL (DLAB =1) Divisor Latch LSB */ + +#define UART_DLL_MASK (0xff) /* Bits 0-7: DLL */ + /* Bits 8-31: Reserved */ + +/* DLM (DLAB =1) Divisor Latch MSB */ + +#define UART_DLM_MASK (0xff) /* Bits 0-7: DLM */ + /* Bits 8-31: Reserved */ + +/* IER (DLAB =0) Interrupt Enable Register */ + +#define UART_IER_ERBFI (1 << 0) /* Bit 0: Enable received data available interrupt */ +#define UART_IER_ETBEI (1 << 1) /* Bit 1: Enable THR empty interrupt */ +#define UART_IER_ELSI (1 << 2) /* Bit 2: Enable receiver line status interrupt */ +#define UART_IER_EDSSI (1 << 3) /* Bit 3: Enable MODEM status interrupt */ + /* Bits 4-7: Reserved */ +#define UART_IER_ALLIE (0x0f) + +/* IIR Interrupt ID Register */ + +#define UART_IIR_INTSTATUS (1 << 0) /* Bit 0: Interrupt status (active low) */ +#define UART_IIR_INTID_SHIFT (1) /* Bits 1-3: Interrupt identification */ +#define UART_IIR_INTID_MASK (7 << UART_IIR_INTID_SHIFT) +# define UART_IIR_INTID_MSI (0 << UART_IIR_INTID_SHIFT) /* Modem Status */ +# define UART_IIR_INTID_THRE (1 << UART_IIR_INTID_SHIFT) /* THR Empty Interrupt */ +# define UART_IIR_INTID_RDA (2 << UART_IIR_INTID_SHIFT) /* Receive Data Available (RDA) */ +# define UART_IIR_INTID_RLS (3 << UART_IIR_INTID_SHIFT) /* Receiver Line Status (RLS) */ +# define UART_IIR_INTID_CTI (6 << UART_IIR_INTID_SHIFT) /* Character Time-out Indicator (CTI) */ + + /* Bits 4-5: Reserved */ +#define UART_IIR_FIFOEN_SHIFT (6) /* Bits 6-7: RCVR FIFO interrupt */ +#define UART_IIR_FIFOEN_MASK (3 << UART_IIR_FIFOEN_SHIFT) + +/* FCR FIFO Control Register */ + +#define UART_FCR_FIFOEN (1 << 0) /* Bit 0: Enable FIFOs */ +#define UART_FCR_RXRST (1 << 1) /* Bit 1: RX FIFO Reset */ +#define UART_FCR_TXRST (1 << 2) /* Bit 2: TX FIFO Reset */ +#define UART_FCR_DMAMODE (1 << 3) /* Bit 3: DMA Mode Select */ + /* Bits 4-5: Reserved */ +#define UART_FCR_RXTRIGGER_SHIFT (6) /* Bits 6-7: RX Trigger Level */ +#define UART_FCR_RXTRIGGER_MASK (3 << UART_FCR_RXTRIGGER_SHIFT) +# define UART_FCR_RXTRIGGER_1 (0 << UART_FCR_RXTRIGGER_SHIFT) /* Trigger level 0 (1 character) */ +# define UART_FCR_RXTRIGGER_4 (1 << UART_FCR_RXTRIGGER_SHIFT) /* Trigger level 1 (4 characters) */ +# define UART_FCR_RXTRIGGER_8 (2 << UART_FCR_RXTRIGGER_SHIFT) /* Trigger level 2 (8 characters) */ +# define UART_FCR_RXTRIGGER_14 (3 << UART_FCR_RXTRIGGER_SHIFT) /* Trigger level 3 (14 characters) */ + +/* LCR Line Control Register */ + +#define UART_LCR_WLS_SHIFT (0) /* Bit 0-1: Word Length Select */ +#define UART_LCR_WLS_MASK (3 << UART_LCR_WLS_SHIFT) +# define UART_LCR_WLS_5BIT (0 << UART_LCR_WLS_SHIFT) +# define UART_LCR_WLS_6BIT (1 << UART_LCR_WLS_SHIFT) +# define UART_LCR_WLS_7BIT (2 << UART_LCR_WLS_SHIFT) +# define UART_LCR_WLS_8BIT (3 << UART_LCR_WLS_SHIFT) +#define UART_LCR_STB (1 << 2) /* Bit 2: Number of Stop Bits */ +#define UART_LCR_PEN (1 << 3) /* Bit 3: Parity Enable */ +#define UART_LCR_EPS (1 << 4) /* Bit 4: Even Parity Select */ +#define UART_LCR_STICKY (1 << 5) /* Bit 5: Stick Parity */ +#define UART_LCR_BRK (1 << 6) /* Bit 6: Break Control */ +#define UART_LCR_DLAB (1 << 7) /* Bit 7: Divisor Latch Access Bit (DLAB) */ + +/* MCR Modem Control Register */ + +#define UART_MCR_DTR (1 << 0) /* Bit 0: DTR Control Source for DTR output */ +#define UART_MCR_RTS (1 << 1) /* Bit 1: Control Source for RTS output */ +#define UART_MCR_OUT1 (1 << 2) /* Bit 2: Auxiliary user-defined output 1 */ +#define UART_MCR_OUT2 (1 << 3) /* Bit 3: Auxiliary user-defined output 2 */ +#define UART_MCR_LPBK (1 << 4) /* Bit 4: Loopback Mode Select */ +#define UART_MCR_AFCE (1 << 5) /* Bit 5: Auto Flow Control Enable */ + /* Bit 6-7: Reserved */ + +/* LSR Line Status Register */ + +#define UART_LSR_DR (1 << 0) /* Bit 0: Data Ready */ +#define UART_LSR_OE (1 << 1) /* Bit 1: Overrun Error */ +#define UART_LSR_PE (1 << 2) /* Bit 2: Parity Error */ +#define UART_LSR_FE (1 << 3) /* Bit 3: Framing Error */ +#define UART_LSR_BI (1 << 4) /* Bit 4: Break Interrupt */ +#define UART_LSR_THRE (1 << 5) /* Bit 5: Transmitter Holding Register Empty */ +#define UART_LSR_TEMT (1 << 6) /* Bit 6: Transmitter Empty */ +#define UART_LSR_RXFE (1 << 7) /* Bit 7: Error in RX FIFO (RXFE) */ + +/* SCR Scratch Pad Register */ + +#define UART_SCR_MASK (0xff) /* Bits 0-7: SCR data */ + +/**************************************************************************** + * Public Types + ****************************************************************************/ + +#if CONFIG_U16550_REGWIDTH == 8 +typedef uint8_t uart_datawidth_t; +#elif CONFIG_U16550_REGWIDTH == 16 +typedef uint16_t uart_datawidth_t; +#elif CONFIG_U16550_REGWIDTH == 32 +typedef uint32_t uart_datawidth_t; +#endif + +#if CONFIG_U16550_ADDRWIDTH == 0 +typedef uintptr_t uart_addrwidth_t; +#elif CONFIG_U16550_ADDRWIDTH == 8 +typedef uint8_t uart_addrwidth_t; +#elif CONFIG_U16550_ADDRWIDTH == 16 +typedef uint16_t uart_addrwidth_t; +#elif CONFIG_U16550_ADDRWIDTH == 32 +typedef uint32_t uart_addrwidth_t; +#elif CONFIG_U16550_ADDRWIDTH == 64 +typedef uint64_t uart_addrwidth_t; +#endif + +struct u16550_s +{ + uart_addrwidth_t uartbase; /* Base address of UART registers */ +#ifndef CONFIG_U16550_SUPRESS_CONFIG + uint32_t baud; /* Configured baud */ + uint32_t uartclk; /* UART clock frequency */ +#endif + uart_datawidth_t ier; /* Saved IER value */ + uint8_t irq; /* IRQ associated with this UART */ +#ifndef CONFIG_U16550_SUPRESS_CONFIG + uint8_t parity; /* 0=none, 1=odd, 2=even */ + uint8_t bits; /* Number of bits (7 or 8) */ + bool stopbits2; /* true: Configure with 2 stop bits instead of 1 */ +#if defined(CONFIG_SERIAL_IFLOWCONTROL) || defined(CONFIG_SERIAL_OFLOWCONTROL) + bool flow; /* flow control (RTS/CTS) enabled */ +#endif +#endif +}; + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +/**************************************************************************** + * Public Functions Definitions + ****************************************************************************/ + +/**************************************************************************** + * Name: uart_getreg(), uart_putreg(), uart_ioctl() + * + * Description: + * These functions must be provided by the processor-specific code in order + * to correctly access 16550 registers + * uart_ioctl() is optional to provide custom IOCTLs + * + ****************************************************************************/ + +#ifndef CONFIG_SERIAL_UART_ARCH_MMIO +uart_datawidth_t uart_getreg(uart_addrwidth_t base, unsigned int offset); +void uart_putreg(uart_addrwidth_t base, + unsigned int offset, + uart_datawidth_t value); +#endif + +struct file; /* Forward reference */ +int uart_ioctl(struct file *filep, int cmd, unsigned long arg); + +void u16550_register(uart_dev_t **dev, int uart_index); +#endif /* CONFIG_U16550_UART */ +#endif /* __INCLUDE_NUTTX_SERIAL_UART_16550_H */