141 lines
5.4 KiB
Scala
141 lines
5.4 KiB
Scala
package cpu
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import chisel3._
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import chisel3.util._
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import chisel3.internal.DontCareBinding
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import defines._
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import defines.Const._
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import pipeline.fetch._
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import pipeline.decode._
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import pipeline.execute._
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import pipeline.memory._
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import pipeline.writeback._
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import ctrl._
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import icache.mmu.Tlb
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class Core(implicit val cpuConfig: CpuConfig) extends Module {
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val io = IO(new Bundle {
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val ext_int = Input(new ExtInterrupt())
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val inst = new Cache_ICache()
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val data = new Cache_DCache()
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val debug = new DEBUG()
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})
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val ctrl = Module(new Ctrl()).io
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val fetchUnit = Module(new FetchUnit()).io
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val bpu = Module(new BranchPredictorUnit()).io
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val instFifo = Module(new InstFifo()).io
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val decodeUnit = Module(new DecodeUnit()).io
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val regfile = Module(new ARegFile()).io
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val executeStage = Module(new ExecuteStage()).io
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val executeUnit = Module(new ExecuteUnit()).io
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val csr = Module(new Csr()).io
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val memoryStage = Module(new MemoryStage()).io
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val memoryUnit = Module(new MemoryUnit()).io
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val writeBackStage = Module(new WriteBackStage()).io
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val writeBackUnit = Module(new WriteBackUnit()).io
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val tlb = Module(new Tlb()).io
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tlb.icache <> io.inst.tlb
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tlb.dcache <> io.data.tlb
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tlb.csr <> csr.tlb
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tlb.sfence_vma <> memoryUnit.ctrl.sfence_vma
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ctrl.decodeUnit <> decodeUnit.ctrl
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ctrl.executeUnit <> executeUnit.ctrl
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ctrl.memoryUnit <> memoryUnit.ctrl
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ctrl.writeBackUnit <> writeBackUnit.ctrl
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ctrl.cacheCtrl.iCache_stall := io.inst.icache_stall
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fetchUnit.memory <> memoryUnit.fetchUnit
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fetchUnit.execute <> executeUnit.fetchUnit
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fetchUnit.decode <> decodeUnit.fetchUnit
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fetchUnit.instFifo.full := instFifo.full
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fetchUnit.iCache.inst_valid := io.inst.inst_valid
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io.inst.addr(0) := fetchUnit.iCache.pc
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io.inst.addr(1) := fetchUnit.iCache.pc_next
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for (i <- 2 until cpuConfig.instFetchNum) {
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io.inst.addr(i) := fetchUnit.iCache.pc_next + ((i - 1) * 4).U
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}
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bpu.decode <> decodeUnit.bpu
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bpu.execute <> executeUnit.bpu
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instFifo.do_flush := ctrl.decodeUnit.do_flush
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instFifo.decoderUint <> decodeUnit.instFifo
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for (i <- 0 until cpuConfig.instFetchNum) {
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instFifo.write(i).pht_index := bpu.instBuffer.pht_index(i)
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bpu.instBuffer.pc(i) := instFifo.write(i).pc
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instFifo.wen(i) := io.inst.inst_valid(i)
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instFifo.write(i).pc := io.inst.addr(0) + (i * 4).U
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instFifo.write(i).inst := io.inst.inst(i)
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instFifo.write(i).access_fault := io.inst.access_fault
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instFifo.write(i).page_fault := io.inst.page_fault
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instFifo.write(i).addr_misaligned := io.inst.addr_misaligned
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}
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decodeUnit.regfile <> regfile.read
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for (i <- 0 until (cpuConfig.commitNum)) {
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decodeUnit.forward(i).exe := executeUnit.decodeUnit.forward(i).exe
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decodeUnit.forward(i).is_load := executeUnit.decodeUnit.forward(i).is_load // exe级是load指令
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decodeUnit.forward(i).mem := memoryUnit.decodeUnit(i)
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}
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decodeUnit.csr <> csr.decodeUnit
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decodeUnit.executeStage <> executeStage.decodeUnit
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for (i <- 0 until (cpuConfig.commitNum)) {
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// 流水线清空或者暂停时，需要清空缓存级的数据，也就是插入气泡
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executeStage.ctrl.clear(i) :=
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ctrl.memoryUnit.do_flush || ctrl.executeUnit.do_flush ||
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!decodeUnit.instFifo.allow_to_go(i) && ctrl.executeUnit.allow_to_go
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executeStage.ctrl.allow_to_go(i) := decodeUnit.instFifo.allow_to_go(i)
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}
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executeUnit.executeStage <> executeStage.executeUnit
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executeUnit.csr <> csr.executeUnit
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executeUnit.memoryStage <> memoryStage.executeUnit
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memoryStage.ctrl.allow_to_go := ctrl.memoryUnit.allow_to_go
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memoryStage.ctrl.clear := ctrl.memoryUnit.do_flush
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memoryUnit.memoryStage <> memoryStage.memoryUnit
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memoryUnit.csr <> csr.memoryUnit
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memoryUnit.writeBackStage <> writeBackStage.memoryUnit
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csr.ext_int := io.ext_int
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memoryUnit.dataMemory.in.rdata := io.data.rdata
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memoryUnit.dataMemory.in.access_fault := io.data.access_fault
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memoryUnit.dataMemory.in.page_fault := io.data.page_fault
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memoryUnit.dataMemory.in.ready := io.data.dcache_ready
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io.data.en := memoryUnit.dataMemory.out.en
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io.data.rlen := memoryUnit.dataMemory.out.rlen
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io.data.wen := memoryUnit.dataMemory.out.wen
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io.data.wdata := memoryUnit.dataMemory.out.wdata
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io.data.addr := memoryUnit.dataMemory.out.addr
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io.data.wstrb := memoryUnit.dataMemory.out.wstrb
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io.data.exe_addr := executeUnit.dataMemory.addr
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writeBackStage.memoryUnit <> memoryUnit.writeBackStage
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writeBackStage.ctrl.allow_to_go := ctrl.writeBackUnit.allow_to_go
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writeBackStage.ctrl.clear := ctrl.writeBackUnit.do_flush
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writeBackUnit.writeBackStage <> writeBackStage.writeBackUnit
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writeBackUnit.ctrl <> ctrl.writeBackUnit
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regfile.write <> writeBackUnit.regfile
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io.debug <> writeBackUnit.debug
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// 解决fence_i
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io.inst.fence_i := memoryUnit.ctrl.fence_i
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io.data.fence_i := memoryUnit.ctrl.fence_i
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io.inst.dcache_stall := !io.data.dcache_ready
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io.inst.req := !instFifo.full && !reset.asBool
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io.inst.complete_single_request := ctrl.fetchUnit.allow_to_go
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io.data.complete_single_request := ctrl.memoryUnit.allow_to_go || ctrl.memoryUnit.complete_single_request
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}
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