368 lines
14 KiB
Scala
368 lines
14 KiB
Scala
package cache
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import chisel3._
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import chisel3.util._
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import memory._
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import cpu.CacheConfig
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import cpu.defines._
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import cpu.CpuConfig
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import cpu.defines.Const._
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/*
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整个宽度为PADDR_WID的地址
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==========================================================
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| tag | index | offset |
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| | | bank index | bank offset |
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==========================================================
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nway 组，nindex 行
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======================================================
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| valid | tag | bank 0 | bank 1 | ... | bank n |
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| 1 | | | | | |
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======================================================
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| bank |
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| inst 0 | inst 1 | ... | inst n |
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| 32 | 32 | ... | 32 |
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=====================================
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本CPU的实现如下：
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每个bank分为多个instBlocks，每个instBlocks的宽度为AXI_DATA_WID，这样能方便的和AXI总线进行交互
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RV64实现中AXI_DATA_WID为64，所以每个instBlocks可以存储2条指令
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而instBlocks的个数会和instFetchNum相关
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- 当instFetchNum为4时，instBlocks的个数为2
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- 当instFetchNum为2时，instBlocks的个数为1
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读取数据时会将一个bank中的所有instBlocks读取出来，然后再将instBlocks中的数据按照偏移量重新排列
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这样的设计可以保证一个bank的指令数对应instFetchNum
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======================================================
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| valid | tag | bank 0 | bank 1 | ... | bank n |
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| 1 | | | | | |
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======================================================
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| bank |
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| instBlocks | instBlocks |
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| inst 0 | inst 1 | inst 0 | inst 1 |
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| 32 | 32 | 32 | 32 |
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=====================================
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*/
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class ICache(cacheConfig: CacheConfig)(implicit cpuConfig: CpuConfig) extends Module with HasTlbConst {
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val nway = cacheConfig.nway
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val nindex = cacheConfig.nindex
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val nbank = cacheConfig.nbank
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val instFetchNum = cpuConfig.instFetchNum
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val bankOffsetWidth = cacheConfig.bankOffsetWidth
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val bankIndexWidth = cacheConfig.offsetWidth - bankOffsetWidth
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val bytesPerBank = cacheConfig.bytesPerBank
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val tagWidth = cacheConfig.tagWidth
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val indexWidth = cacheConfig.indexWidth
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val offsetWidth = cacheConfig.offsetWidth
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val bitsPerBank = cacheConfig.bitsPerBank
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def pAddr = new Bundle {
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val tag = UInt(ppnLen.W)
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val index = UInt(indexWidth.W)
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val offset = UInt(offsetWidth.W)
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}
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def bankAddr = new Bundle {
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val index = UInt(bankIndexWidth.W)
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val offset = UInt(bankOffsetWidth.W)
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}
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val io = IO(new Bundle {
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val cpu = Flipped(new Cache_ICache())
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val axi = new ICache_AXIInterface()
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})
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require(isPow2(instFetchNum), "ninst must be power of 2")
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require(instFetchNum == bytesPerBank / 4, "instFetchNum must equal to instperbank")
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require(
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bitsPerBank >= AXI_DATA_WID && bitsPerBank % AXI_DATA_WID == 0,
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"bitsPerBank must be greater than AXI_DATA_WID"
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)
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// 一个bank是bitsPerBank宽度，一个bank中有instFetchNum个指令
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// 每个bank中指令块的个数，一个指令块是AXI_DATA_WID宽度
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val instBlocksPerBank = bitsPerBank / AXI_DATA_WID
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val bank_index = io.cpu.addr(0)(offsetWidth - 1, bankOffsetWidth)
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val bank_offset = io.cpu.addr(0)(bankOffsetWidth - 1, log2Ceil(INST_WID / 8)) // PC低2位必定是0
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// * fsm * //
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val s_idle :: s_uncached :: s_replace :: s_wait :: s_fence :: s_tlb_refill :: Nil = Enum(6)
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val state = RegInit(s_idle)
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// nway 路，每路 nindex 行，每行 nbank 个 bank，每行的nbank共用一个valid
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val valid = RegInit(VecInit(Seq.fill(nway)(VecInit(Seq.fill(nindex)(false.B)))))
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// * should choose next addr * //
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val use_next_addr = (state === s_idle) || (state === s_wait)
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// 读取一个cache条目中的所有bank行
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val data = Wire(Vec(nway, Vec(nbank, Vec(instBlocksPerBank, UInt(AXI_DATA_WID.W)))))
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val data_rindex = io.cpu.addr(use_next_addr)(indexWidth + offsetWidth - 1, offsetWidth)
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val tag = RegInit(VecInit(Seq.fill(nway)(0.U(tagWidth.W))))
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val tag_raddr = io.cpu.addr(use_next_addr)(indexWidth + offsetWidth - 1, offsetWidth)
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val tag_wstrb = RegInit(VecInit(Seq.fill(nway)(false.B)))
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val tag_wdata = RegInit(0.U(tagWidth.W))
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// * lru * //// TODO:检查lru的正确性，增加可拓展性，目前只支持两路的cache
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val lru = RegInit(VecInit(Seq.fill(nindex)(false.B)))
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val replace_index = io.cpu.addr(0)(indexWidth + offsetWidth - 1, offsetWidth)
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// 需要替换的路号
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val replace_way = lru(replace_index)
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// 用于控制写入一行cache条目中的哪个bank, 一个bank可能有多次写入
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val replace_wstrb = RegInit(
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VecInit(Seq.fill(nway)(VecInit(Seq.fill(nbank)(VecInit(Seq.fill(instBlocksPerBank)((false.B)))))))
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)
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// * cache hit * //
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val tag_compare_valid = VecInit(Seq.tabulate(nway)(i => tag(i) === io.cpu.tlb.ptag && valid(i)(replace_index)))
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val cache_hit = tag_compare_valid.contains(true.B)
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val cache_hit_available = cache_hit && io.cpu.tlb.hit && !io.cpu.tlb.uncached
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val select_way = tag_compare_valid(1) // 1路命中时值为1，0路命中时值为0 //TODO:支持更多路数
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// 将一个 bank 中的指令分成 instFetchNum 份，每份 INST_WID bit
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val inst_in_bank = VecInit(
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Seq.tabulate(instFetchNum)(i => data(select_way)(bank_index).asUInt((i + 1) * INST_WID - 1, i * INST_WID))
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)
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// 将 inst_in_bank 中的指令按照 bank_offset 位偏移量重新排列
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// 处理偏移导致的跨 bank 读取
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// 当offset为0时，不需要重新排列
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// 当offset为1时，此时发送到cpu的inst0应该是inst1，inst1应该无数据，并设置对应的valid
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val inst = VecInit(
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Seq.tabulate(instFetchNum)(i =>
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Mux(
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i.U <= ((instFetchNum - 1).U - bank_offset),
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inst_in_bank(i.U + bank_offset),
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0.U
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)
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)
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)
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val inst_valid = VecInit(
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Seq.tabulate(instFetchNum)(i => cache_hit_available && i.U <= ((instFetchNum - 1).U - bank_offset))
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)
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val rdata_in_wait = RegInit(VecInit(Seq.fill(instFetchNum)(0.U.asTypeOf(new Bundle {
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val inst = UInt(INST_WID.W)
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val valid = Bool()
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}))))
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// 对于可缓存段访存时读取的数据宽度应该和AXI_DATA的宽度相同
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val cached_size = log2Ceil(AXI_DATA_WID / 8)
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val cached_len = (nbank * instBlocksPerBank - 1)
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// 对于不可缓存段访存时读取的数据宽度应该和指令宽度相同
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val uncached_size = log2Ceil(INST_WID / 8)
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val uncached_len = 0
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// bank tag ram
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for { i <- 0 until nway } {
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// 每一个条目中有nbank个bank，每个bank存储instFetchNum个指令
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// 每次写入cache时将写完一整个cache行
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val bank =
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Seq.fill(nbank)(
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Seq.fill(instBlocksPerBank)(
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Module(new SimpleDualPortRam(depth = nindex, width = AXI_DATA_WID, byteAddressable = false))
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)
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)
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for { j <- 0 until nbank } {
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for { k <- 0 until instBlocksPerBank } {
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bank(j)(k).io.ren := true.B
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bank(j)(k).io.raddr := data_rindex
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data(i)(j)(k) := bank(j)(k).io.rdata
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bank(j)(k).io.wen := replace_wstrb(i)(j)(k)
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bank(j)(k).io.waddr := replace_index
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bank(j)(k).io.wdata := io.axi.r.bits.data
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bank(j)(k).io.wstrb := replace_wstrb(i)(j)(k)
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}
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}
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}
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for { i <- 0 until instFetchNum } {
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io.cpu.inst_valid(i) := Mux(state === s_idle, inst_valid(i), rdata_in_wait(i).valid) && io.cpu.req
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io.cpu.inst(i) := Mux(state === s_idle, inst(i), rdata_in_wait(i).inst)
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}
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for { i <- 0 until nway } {
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// 实例化了nway个tag ram
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val tagBram = Module(new LUTRam(nindex, tagWidth))
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tagBram.io.raddr := tag_raddr
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tag(i) := tagBram.io.rdata
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tagBram.io.wen := tag_wstrb(i)
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tagBram.io.waddr := replace_index
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tagBram.io.wdata := tag_wdata
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}
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io.cpu.icache_stall := Mux(state === s_idle, (!cache_hit_available && io.cpu.req), state =/= s_wait)
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io.cpu.tlb.vaddr := io.cpu.addr(0)
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io.cpu.tlb.complete_single_request := io.cpu.complete_single_request
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io.cpu.tlb.en := io.cpu.req && (state === s_idle || state === s_tlb_refill)
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val ar = RegInit(0.U.asTypeOf(new AR()))
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val arvalid = RegInit(false.B)
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ar <> io.axi.ar.bits
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arvalid <> io.axi.ar.valid
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val r = RegInit(0.U.asTypeOf(new R()))
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val rready = RegInit(false.B)
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r <> io.axi.r.bits
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rready <> io.axi.r.ready
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val access_fault = RegInit(false.B)
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val page_fault = RegInit(false.B)
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val addr_misaligned = RegInit(false.B)
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// sv39的63-39位不与第38位相同，或者地址未对齐时，地址错
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val addr_err =
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io.cpu
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.addr(use_next_addr)(XLEN - 1, VADDR_WID)
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.asBools
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.map(_ =/= io.cpu.addr(use_next_addr)(VADDR_WID - 1))
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.reduce(_ || _) ||
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io.cpu.addr(use_next_addr)(log2Ceil(INST_WID / 8) - 1, 0).orR
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io.cpu.access_fault := access_fault //TODO：实现cached段中的访存response错误
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io.cpu.page_fault := page_fault
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io.cpu.addr_misaligned := addr_misaligned
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switch(state) {
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is(s_idle) {
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access_fault := false.B // 在idle时清除access_fault
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page_fault := false.B // 在idle时清除page_fault
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addr_misaligned := false.B // 在idle时清除addr_misaligned
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when(io.cpu.req) {
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when(addr_err) {
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when(io.cpu.addr(use_next_addr)(log2Ceil(INST_WID / 8) - 1, 0).orR) {
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addr_misaligned := true.B
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}.otherwise {
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access_fault := true.B
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}
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state := s_wait
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rdata_in_wait(0).inst := Instructions.NOP
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rdata_in_wait(0).valid := true.B
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}.elsewhen(!io.cpu.tlb.hit) {
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state := s_tlb_refill
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}.elsewhen(io.cpu.tlb.uncached) {
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state := s_uncached
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ar.addr := io.cpu.tlb.paddr
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ar.len := uncached_len.U
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ar.size := uncached_size.U
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arvalid := true.B
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}.elsewhen(!cache_hit) {
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state := s_replace
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// 取指时按bank块取指
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ar.addr := Cat(io.cpu.tlb.paddr(PADDR_WID - 1, offsetWidth), 0.U(offsetWidth.W))
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ar.len := cached_len.U
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ar.size := cached_size.U
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arvalid := true.B
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replace_wstrb(replace_way).map(_.map(_ := false.B))
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replace_wstrb(replace_way)(0)(0) := true.B // 从第一个bank的第一个指令块开始写入
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tag_wstrb(replace_way) := true.B
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tag_wdata := io.cpu.tlb.ptag
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valid(replace_way)(replace_index) := true.B
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}.elsewhen(!io.cpu.icache_stall) {
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replace_way := ~select_way
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when(!io.cpu.complete_single_request) {
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state := s_wait
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(1 until instFetchNum).foreach(i => rdata_in_wait(i).inst := inst(i))
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(0 until instFetchNum).foreach(i => rdata_in_wait(i).valid := inst_valid(i))
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}
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}
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}
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}
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is(s_uncached) {
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when(io.axi.ar.valid) {
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when(io.axi.ar.ready) {
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arvalid := false.B
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rready := true.B
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}
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}.elsewhen(io.axi.r.fire) {
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// * uncached not support burst transport * //
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rdata_in_wait(0).inst := Mux(ar.addr(2), io.axi.r.bits.data(63, 32), io.axi.r.bits.data(31, 0))
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rdata_in_wait(0).valid := true.B
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rready := false.B
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access_fault := io.axi.r.bits.resp =/= RESP_OKEY.U
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state := s_wait
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}
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}
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is(s_replace) {
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when(io.axi.ar.valid) {
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when(io.axi.ar.ready) {
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arvalid := false.B
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rready := true.B
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}
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}.elsewhen(io.axi.r.fire) {
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// * burst transport * //
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when(!io.axi.r.bits.last) {
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// 左移写掩码，写入下一个bank，或是同一个bank的下一个指令
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replace_wstrb(replace_way) :=
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((replace_wstrb(replace_way).asUInt << 1)).asTypeOf(replace_wstrb(replace_way))
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}.otherwise {
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rready := false.B
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replace_wstrb(replace_way).map(_.map(_ := false.B))
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tag_wstrb(replace_way) := false.B
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}
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}.elsewhen(!io.axi.r.ready) {
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state := s_idle
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}
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}
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is(s_wait) {
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// 等待流水线的allow_to_go信号，防止多次发出读请求
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when(io.cpu.complete_single_request) {
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access_fault := false.B // 清除access_fault
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page_fault := false.B // 清除page_fault
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addr_misaligned := false.B // 清除addr_misaligned
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state := s_idle
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(0 until instFetchNum).foreach(i => rdata_in_wait(i).valid := false.B)
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}
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}
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is(s_fence) {
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// 等待dcache完成写回操作，且等待axi总线完成读取操作，因为icache发生状态转移时可能正在读取数据
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when(!io.cpu.dcache_stall && !io.axi.r.valid) {
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state := s_idle
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}
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}
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is(s_tlb_refill) {
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when(io.cpu.tlb.access_fault) {
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access_fault := true.B
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state := s_wait
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rdata_in_wait(0).inst := Instructions.NOP
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rdata_in_wait(0).valid := true.B
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}.elsewhen(io.cpu.tlb.page_fault) {
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page_fault := true.B
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state := s_wait
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rdata_in_wait(0).inst := Instructions.NOP
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rdata_in_wait(0).valid := true.B
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}.otherwise {
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when(io.cpu.tlb.hit) {
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state := s_idle
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}
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}
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}
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}
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// * fence * //
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// 不论icache在什么状态，fence指令优先度最高，会强制将icache状态转移为s_fence
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when(io.cpu.fence_i) {
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valid := 0.U.asTypeOf(valid) // fence.i指令需要icache，等同于将所有valid位置0
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state := s_fence
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}
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println("----------------------------------------")
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println("ICache: ")
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println("nindex: " + nindex)
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println("nbank: " + nbank)
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println("bankOffsetWidth: " + bankOffsetWidth)
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println("bytesPerBank: " + bytesPerBank)
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println("tagWidth: " + tagWidth)
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println("indexWidth: " + indexWidth)
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println("offsetWidth: " + offsetWidth)
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println("----------------------------------------")
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}
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