yystopf
/
riscv-lab
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

refactor(core): 修改clear信号，使逻辑更清晰

This commit is contained in:
Liphen 2024-02-25 17:09:12 +08:00
parent 3b06ee4f55
commit fdc8c2b11e
1 changed files with 4 additions and 3 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

7
chisel/playground/src/Core.scala
View File

@ -85,9 +85,10 @@ class Core(implicit val cpuConfig: CpuConfig) extends Module {
decodeUnit.executeStage <> executeStage.decodeUnit decodeUnit.executeStage <> executeStage.decodeUnit
for (i <- 0 until (cpuConfig.commitNum)) { for (i <- 0 until (cpuConfig.commitNum)) {
executeStage.ctrl.clear(i) := ctrl.memoryUnit.flush || // 流水线清空或者暂停时，需要清空缓存级的数据，也就是插入气泡
ctrl.executeUnit.do_flush && ctrl.executeUnit.allow_to_go || executeStage.ctrl.clear(i) :=
!decodeUnit.instFifo.allow_to_go(i) && ctrl.executeUnit.allow_to_go ctrl.memoryUnit.do_flush || ctrl.executeUnit.do_flush ||
!decodeUnit.instFifo.allow_to_go(i) && ctrl.executeUnit.allow_to_go
executeStage.ctrl.allow_to_go(i) := decodeUnit.instFifo.allow_to_go(i) executeStage.ctrl.allow_to_go(i) := decodeUnit.instFifo.allow_to_go(i)
} }