成功生成verilog
This commit is contained in:
Liphen
parent
6f02672358
commit
f7ee8c4c87
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@ -44,7 +44,6 @@ class Core(implicit val config: CpuConfig) extends Module {
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ctrl.memoryUnit <> memoryUnit.ctrl
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ctrl.writeBackUnit <> writeBackUnit.ctrl
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ctrl.cacheCtrl.iCache_stall := io.inst.icache_stall
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ctrl.cacheCtrl.dCache_stall := io.data.dcache_stall
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fetchUnit.memory <> memoryUnit.fetchUnit
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fetchUnit.execute <> executeUnit.fetchUnit
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@ -120,6 +119,7 @@ class Core(implicit val config: CpuConfig) extends Module {
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memoryUnit.dataMemory.in.rdata := io.data.rdata
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memoryUnit.dataMemory.in.acc_err := io.data.acc_err
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memoryUnit.dataMemory.in.ready := !io.data.dcache_stall
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io.data.en := memoryUnit.dataMemory.out.en
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io.data.size := memoryUnit.dataMemory.out.rlen
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io.data.wen := memoryUnit.dataMemory.out.wen
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@ -17,15 +17,16 @@ class Ctrl(implicit val config: CpuConfig) extends Module {
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val writeBackUnit = Flipped(new WriteBackCtrl())
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})
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val inst0_lw_stall = (io.executeUnit.inst(0).mem_wreg) &&
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val inst0_lw_stall = (io.executeUnit.inst(0).mem_wreg) && io.executeUnit.inst(0).reg_waddr.orR &&
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(io.decoderUnit.inst0.src1.ren && io.decoderUnit.inst0.src1.raddr === io.executeUnit.inst(0).reg_waddr ||
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io.decoderUnit.inst0.src2.ren && io.decoderUnit.inst0.src2.raddr === io.executeUnit.inst(0).reg_waddr)
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val inst1_lw_stall = (io.executeUnit.inst(1).mem_wreg) &&
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val inst1_lw_stall = (io.executeUnit.inst(1).mem_wreg) && io.executeUnit.inst(1).reg_waddr.orR &&
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(io.decoderUnit.inst0.src1.ren && io.decoderUnit.inst0.src1.raddr === io.executeUnit.inst(1).reg_waddr ||
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io.decoderUnit.inst0.src2.ren && io.decoderUnit.inst0.src2.raddr === io.executeUnit.inst(1).reg_waddr)
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val lw_stall = inst0_lw_stall || inst1_lw_stall
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// TODO: 这里的stall信号可能不对
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val longest_stall = io.executeUnit.fu_stall || io.cacheCtrl.iCache_stall || io.cacheCtrl.dCache_stall
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val longest_stall =
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io.executeUnit.fu_stall || io.cacheCtrl.iCache_stall || io.memoryUnit.mem_stall
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io.fetchUnit.allow_to_go := !io.cacheCtrl.iCache_stall
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io.decoderUnit.allow_to_go := !(lw_stall || longest_stall)
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@ -55,7 +55,6 @@ class SrcReadSignal extends Bundle {
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class CacheCtrl extends Bundle {
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val iCache_stall = Output(Bool())
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val dCache_stall = Output(Bool())
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}
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class FetchUnitCtrl extends Bundle {
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@ -95,6 +94,7 @@ class ExecuteCtrl(implicit val config: CpuConfig) extends Bundle {
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class MemoryCtrl extends Bundle {
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val flush = Output(Bool())
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val mem_stall = Output(Bool())
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val allow_to_go = Input(Bool())
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val do_flush = Input(Bool())
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@ -17,10 +17,16 @@ class CsrMemoryUnit(implicit val config: CpuConfig) extends Bundle {
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val info = new InstInfo()
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}
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)
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val set_lr = Bool()
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val set_lr_val = Bool()
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val set_lr_addr = UInt(DATA_ADDR_WID.W)
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})
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val out = Output(new Bundle {
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val flush = Bool()
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val flush_pc = UInt(PC_WID.W)
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val lr = Bool()
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val lr_addr = UInt(DATA_ADDR_WID.W)
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})
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}
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@ -104,20 +110,20 @@ class Csr(implicit val config: CpuConfig) extends Module with HasCSRConst {
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val wdata = Wire(UInt(XLEN.W))
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// Atom LR/SC Control Bits
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val setLr = WireInit(Bool(), false.B)
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val setLrVal = WireInit(Bool(), false.B)
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val setLrAddr = WireInit(UInt(XLEN.W), DontCare) //TODO : need check
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val set_lr = WireInit(Bool(), false.B)
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val set_lr_val = WireInit(Bool(), false.B)
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val set_lr_addr = WireInit(UInt(DATA_ADDR_WID.W), 0.U)
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val lr = RegInit(Bool(), false.B)
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val lrAddr = RegInit(UInt(XLEN.W), 0.U)
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BoringUtils.addSink(setLr, "set_lr")
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BoringUtils.addSink(setLrVal, "set_lr_val")
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BoringUtils.addSink(setLrAddr, "set_lr_addr")
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BoringUtils.addSource(lr, "lr")
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BoringUtils.addSource(lrAddr, "lr_addr")
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val lr_addr = RegInit(UInt(DATA_ADDR_WID.W), 0.U)
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set_lr := io.memoryUnit.in.set_lr
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set_lr_val := io.memoryUnit.in.set_lr_val
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set_lr_addr := io.memoryUnit.in.set_lr_addr
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io.memoryUnit.out.lr := lr
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io.memoryUnit.out.lr_addr := lr_addr
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when(setLr) {
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lr := setLrVal
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lrAddr := setLrAddr
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when(set_lr) {
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lr := set_lr_val
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lr_addr := set_lr_addr
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}
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// Side Effect
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@ -113,6 +113,7 @@ class ExecuteUnit(implicit val config: CpuConfig) extends Module {
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io.memoryStage.inst0.pc := io.executeStage.inst0.pc
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io.memoryStage.inst0.info := io.executeStage.inst0.info
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io.memoryStage.inst0.src_info := io.executeStage.inst0.src_info
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io.memoryStage.inst0.rd_info.wdata(FuType.alu) := fu.inst(0).result.alu
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io.memoryStage.inst0.rd_info.wdata(FuType.mdu) := fu.inst(0).result.mdu
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io.memoryStage.inst0.rd_info.wdata(FuType.csr) := io.csr.out.rdata
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@ -137,6 +138,7 @@ class ExecuteUnit(implicit val config: CpuConfig) extends Module {
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io.memoryStage.inst1.pc := io.executeStage.inst1.pc
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io.memoryStage.inst1.info := io.executeStage.inst1.info
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io.memoryStage.inst1.src_info := io.executeStage.inst1.src_info
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io.memoryStage.inst1.rd_info.wdata(FuType.alu) := fu.inst(1).result.alu
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io.memoryStage.inst1.rd_info.wdata(FuType.mdu) := fu.inst(1).result.mdu
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io.memoryStage.inst1.rd_info.wdata(FuType.csr) := io.csr.out.rdata
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@ -5,10 +5,12 @@ import chisel3.util._
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import cpu.defines._
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import cpu.defines.Const._
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import cpu.CpuConfig
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import chisel3.util.experimental.BoringUtils
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class DataMemoryAccess_DataMemory extends Bundle {
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val in = Input(new Bundle {
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val acc_err = Bool()
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val ready = Bool()
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val rdata = UInt(DATA_WID.W)
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})
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val out = Output(new Bundle {
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@ -21,85 +23,170 @@ class DataMemoryAccess_DataMemory extends Bundle {
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})
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}
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class DataMemoryAccess(implicit val config: CpuConfig) extends Module {
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val io = IO(new Bundle {
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val memoryUnit = new Bundle {
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class DataMemoryAccess_MemoryUnit extends Bundle {
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val in = Input(new Bundle {
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val mem_en = Bool()
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val info = new InstInfo()
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val mem_wdata = UInt(DATA_WID.W)
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val mem_addr = UInt(DATA_ADDR_WID.W)
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val mem_sel = Vec(config.fuNum, Bool())
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val ex = Vec(config.fuNum, new ExceptionInfo())
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val src_info = new SrcInfo()
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val ex = new ExceptionInfo()
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val lr = Bool()
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val lr_addr = UInt(DATA_ADDR_WID.W)
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})
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val out = Output(new Bundle {
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val acc_err = Bool()
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val rdata = Output(UInt(DATA_WID.W))
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})
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}
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val ready = Bool()
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val rdata = UInt(DATA_WID.W)
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val ex = new ExceptionInfo()
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val set_lr = Bool()
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val set_lr_val = Bool()
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val set_lr_addr = UInt(DATA_ADDR_WID.W)
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})
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}
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class DataMemoryAccess(implicit val config: CpuConfig) extends Module {
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val io = IO(new Bundle {
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val memoryUnit = new DataMemoryAccess_MemoryUnit()
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val dataMemory = new DataMemoryAccess_DataMemory()
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})
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val mem_addr = io.memoryUnit.in.mem_addr
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val mem_addr2 = mem_addr(1, 0)
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val mem_rdata = io.dataMemory.in.rdata
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val mem_wdata = io.memoryUnit.in.mem_wdata
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val op = io.memoryUnit.in.info.op
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io.dataMemory.out.en := io.memoryUnit.in.mem_en &&
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(io.memoryUnit.in.mem_sel(0) &&
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!(HasExcInt(io.memoryUnit.in.ex(0))) ||
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io.memoryUnit.in.mem_sel(1) &&
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!(HasExcInt(io.memoryUnit.in.ex(0))) && !(HasExcInt(io.memoryUnit.in.ex(1))))
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io.dataMemory.out.addr := mem_addr
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val rdata = LookupTree(
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mem_addr(2, 0),
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List(
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"b000".U -> mem_rdata(63, 0),
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"b001".U -> mem_rdata(63, 8),
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"b010".U -> mem_rdata(63, 16),
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"b011".U -> mem_rdata(63, 24),
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"b100".U -> mem_rdata(63, 32),
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"b101".U -> mem_rdata(63, 40),
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"b110".U -> mem_rdata(63, 48),
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"b111".U -> mem_rdata(63, 56)
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)
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)
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io.memoryUnit.out.acc_err := io.dataMemory.in.acc_err
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io.memoryUnit.out.rdata := MuxLookup(op, rdata(XLEN - 1, 0))(
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List(
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LSUOpType.lb -> SignedExtend(rdata(7, 0), XLEN),
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LSUOpType.lh -> SignedExtend(rdata(15, 0), XLEN),
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LSUOpType.lw -> SignedExtend(rdata(31, 0), XLEN),
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LSUOpType.lbu -> ZeroExtend(rdata(7, 0), XLEN),
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LSUOpType.lhu -> ZeroExtend(rdata(15, 0), XLEN),
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LSUOpType.lwu -> ZeroExtend(rdata(31, 0), XLEN)
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)
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)
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def genWdata(data: UInt, sizeEncode: UInt): UInt = {
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LookupTree(
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sizeEncode,
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List(
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"b00".U -> Fill(8, data(7, 0)),
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"b01".U -> Fill(4, data(15, 0)),
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"b10".U -> Fill(2, data(31, 0)),
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"b11".U -> data
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)
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)
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}
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def genWmask(addr: UInt, sizeEncode: UInt): UInt = {
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LookupTree(
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sizeEncode,
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List(
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"b00".U -> 0x1.U, //0001 << addr(2:0)
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"b01".U -> 0x3.U, //0011
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"b10".U -> 0xf.U, //1111
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"b11".U -> 0xff.U //11111111
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)
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) << addr(2, 0)
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val atomAlu = Module(new AtomAlu()).io
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val lsExe = Module(new LSExe()).io
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val valid = io.memoryUnit.in.mem_en
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val src1 = io.memoryUnit.in.src_info.src1_data
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val src2 = io.memoryUnit.in.src_info.src2_data
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val func = io.memoryUnit.in.info.op
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val inst = io.memoryUnit.in.info.inst
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val storeReq = valid & LSUOpType.isStore(func)
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val loadReq = valid & LSUOpType.isLoad(func)
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val atomReq = valid & LSUOpType.isAtom(func)
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val amoReq = valid & LSUOpType.isAMO(func)
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val lrReq = valid & LSUOpType.isLR(func)
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val scReq = valid & LSUOpType.isSC(func)
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val aq = inst(26)
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val rl = inst(25)
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val funct3 = inst(14, 12)
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val atomWidthW = !funct3(0)
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val atomWidthD = funct3(0)
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// Atom LR/SC Control Bits
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val setLr = Wire(Bool())
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val setLrVal = Wire(Bool())
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val setLrAddr = Wire(UInt(DATA_ADDR_WID.W))
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val lr = WireInit(Bool(), false.B)
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val lrAddr = WireInit(UInt(DATA_ADDR_WID.W), DontCare)
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io.memoryUnit.out.set_lr := setLr
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io.memoryUnit.out.set_lr_val := setLrVal
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io.memoryUnit.out.set_lr_addr := setLrAddr
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lr := io.memoryUnit.in.lr
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lrAddr := io.memoryUnit.in.lr_addr
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val s_idle :: s_lr :: s_sc :: s_amo_l :: s_amo_a :: s_amo_s :: Nil = Enum(6)
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val state = RegInit(s_idle)
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val atomMemReg = Reg(UInt(XLEN.W))
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val atomRegReg = Reg(UInt(XLEN.W))
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atomAlu.in.rdata := atomMemReg
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atomAlu.in.wdata := io.dataMemory.out.wdata
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atomAlu.in.info := io.memoryUnit.in.info
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val scInvalid = (src1 =/= lrAddr || !lr) && scReq
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lsExe.in.info := io.memoryUnit.in.info
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lsExe.in.mem_addr := 0.U
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lsExe.in.mem_en := false.B
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lsExe.in.wdata := 0.U
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io.memoryUnit.out.ready := false.B
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switch(state) {
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is(s_idle) { // calculate address
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lsExe.in.mem_en := io.memoryUnit.in.mem_en && !atomReq
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lsExe.in.mem_addr := src1 + src2
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lsExe.in.info.op := func
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lsExe.in.wdata := io.memoryUnit.in.src_info.src2_data
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io.memoryUnit.out.ready := lsExe.dataMemory.in.ready || scInvalid
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state := s_idle
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when(amoReq) { state := s_amo_l }
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when(lrReq) { state := s_lr }
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when(scReq) { state := Mux(scInvalid, s_idle, s_sc) }
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}
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io.dataMemory.out.wdata := genWdata(mem_wdata, op(1, 0))
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io.dataMemory.out.wen := LSUOpType.isStore(op) && io.memoryUnit.in.mem_en
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io.dataMemory.out.wstrb := genWmask(mem_addr, op(1, 0))
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io.dataMemory.out.rlen := op(1, 0)
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is(s_amo_l) {
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lsExe.in.mem_en := true.B
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lsExe.in.mem_addr := src1
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lsExe.in.info.op := Mux(atomWidthD, LSUOpType.ld, LSUOpType.lw)
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lsExe.in.wdata := DontCare
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io.memoryUnit.out.ready := false.B
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when(lsExe.dataMemory.in.ready) {
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state := s_amo_a;
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}
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atomMemReg := lsExe.out.rdata
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atomRegReg := lsExe.out.rdata
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}
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is(s_amo_a) {
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lsExe.in.mem_en := false.B
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lsExe.in.mem_addr := DontCare
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lsExe.in.info.op := DontCare
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lsExe.in.wdata := DontCare
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io.memoryUnit.out.ready := false.B
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state := s_amo_s
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atomMemReg := atomAlu.out.result
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}
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is(s_amo_s) {
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lsExe.in.mem_en := true.B
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lsExe.in.mem_addr := src1
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lsExe.in.info.op := Mux(atomWidthD, LSUOpType.sd, LSUOpType.sw)
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lsExe.in.wdata := atomMemReg
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io.memoryUnit.out.ready := lsExe.dataMemory.in.ready
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when(lsExe.dataMemory.in.ready) {
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state := s_idle;
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}
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}
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is(s_lr) {
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lsExe.in.mem_en := true.B
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lsExe.in.mem_addr := src1
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lsExe.in.info.op := Mux(atomWidthD, LSUOpType.ld, LSUOpType.lw)
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lsExe.in.wdata := DontCare
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io.memoryUnit.out.ready := lsExe.dataMemory.in.ready
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when(lsExe.dataMemory.in.ready) {
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state := s_idle;
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}
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}
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is(s_sc) {
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lsExe.in.mem_en := true.B
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lsExe.in.mem_addr := src1
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lsExe.in.info.op := Mux(atomWidthD, LSUOpType.sd, LSUOpType.sw)
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lsExe.in.wdata := io.memoryUnit.in.src_info.src2_data
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io.memoryUnit.out.ready := lsExe.dataMemory.in.ready
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when(lsExe.dataMemory.in.ready) {
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state := s_idle;
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}
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}
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}
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when(lsExe.out.loadAddrMisaligned || lsExe.out.storeAddrMisaligned) {
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state := s_idle
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io.memoryUnit.out.ready := true.B
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io.memoryUnit.out.ready := true.B
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}
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setLr := io.memoryUnit.out.ready && (lrReq || scReq)
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setLrVal := lrReq
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setLrAddr := src1
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io.dataMemory <> lsExe.dataMemory
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io.memoryUnit.out.ex := io.memoryUnit.in.ex
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io.memoryUnit.out.ex.exception(loadAddrMisaligned) := lsExe.out.loadAddrMisaligned
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io.memoryUnit.out.ex.exception(storeAddrMisaligned) := lsExe.out.storeAddrMisaligned
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io.memoryUnit.out.ex.exception(loadAccessFault) := lsExe.out.loadAccessFault
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io.memoryUnit.out.ex.exception(storeAccessFault) := lsExe.out.storeAccessFault
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io.memoryUnit.out.rdata := lsExe.out.rdata
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}
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@ -18,6 +18,8 @@ class LSExe extends Module {
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val out = Output(new Bundle {
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val loadAddrMisaligned = Bool()
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val storeAddrMisaligned = Bool()
|
||||
val loadAccessFault = Bool()
|
||||
val storeAccessFault = Bool()
|
||||
val rdata = UInt(DATA_WID.W)
|
||||
})
|
||||
})
|
||||
|
|
@ -136,5 +138,7 @@ class LSExe extends Module {
|
|||
val is_amo = valid && LSUOpType.isAMO(op)
|
||||
io.out.rdata := Mux(partialLoad, rdataPartialLoad, rdataSel)
|
||||
io.out.loadAddrMisaligned := valid && !isStore && !is_amo && !addrAligned
|
||||
io.out.loadAccessFault := valid && !isStore && !is_amo && acc_err
|
||||
io.out.storeAddrMisaligned := valid && (isStore || is_amo) && !addrAligned
|
||||
io.out.storeAccessFault := valid && (isStore || is_amo) && acc_err
|
||||
}
|
||||
|
|
|
|||
|
|
@ -24,16 +24,37 @@ class MemoryUnit(implicit val config: CpuConfig) extends Module {
|
|||
})
|
||||
|
||||
val dataMemoryAccess = Module(new DataMemoryAccess()).io
|
||||
dataMemoryAccess.memoryUnit.in.mem_en := io.memoryStage.inst0.mem.en
|
||||
dataMemoryAccess.memoryUnit.in.info := io.memoryStage.inst0.mem.info
|
||||
dataMemoryAccess.memoryUnit.in.mem_wdata := io.memoryStage.inst0.mem.wdata
|
||||
dataMemoryAccess.memoryUnit.in.mem_addr := io.memoryStage.inst0.mem.addr
|
||||
dataMemoryAccess.memoryUnit.in.mem_sel := io.memoryStage.inst0.mem.sel
|
||||
dataMemoryAccess.memoryUnit.in.ex(0) := io.memoryStage.inst0.ex
|
||||
dataMemoryAccess.memoryUnit.in.ex(1) := io.memoryStage.inst1.ex
|
||||
dataMemoryAccess.dataMemory.in.acc_err := io.dataMemory.in.acc_err
|
||||
dataMemoryAccess.dataMemory.in.rdata := io.dataMemory.in.rdata
|
||||
io.dataMemory.out := dataMemoryAccess.dataMemory.out
|
||||
val mem_sel = VecInit(
|
||||
io.memoryStage.inst0.info.valid &&
|
||||
io.memoryStage.inst0.info.fusel === FuType.lsu &&
|
||||
!HasExcInt(io.memoryStage.inst0.ex),
|
||||
io.memoryStage.inst1.info.valid &&
|
||||
io.memoryStage.inst1.info.fusel === FuType.lsu &&
|
||||
!HasExcInt(io.memoryStage.inst1.ex) && !HasExcInt(io.memoryStage.inst0.ex)
|
||||
)
|
||||
dataMemoryAccess.memoryUnit.in.mem_en := mem_sel.reduce(_ || _)
|
||||
dataMemoryAccess.memoryUnit.in.info := MuxCase(
|
||||
0.U.asTypeOf(new InstInfo()),
|
||||
Seq(
|
||||
mem_sel(0) -> io.memoryStage.inst0.info,
|
||||
mem_sel(1) -> io.memoryStage.inst1.info
|
||||
)
|
||||
)
|
||||
dataMemoryAccess.memoryUnit.in.src_info := MuxCase(
|
||||
0.U.asTypeOf(new SrcInfo()),
|
||||
Seq(
|
||||
mem_sel(0) -> io.memoryStage.inst0.src_info,
|
||||
mem_sel(1) -> io.memoryStage.inst1.src_info
|
||||
)
|
||||
)
|
||||
dataMemoryAccess.memoryUnit.in.ex := MuxCase(
|
||||
0.U.asTypeOf(new ExceptionInfo()),
|
||||
Seq(
|
||||
mem_sel(0) -> io.memoryStage.inst0.ex,
|
||||
mem_sel(1) -> io.memoryStage.inst1.ex
|
||||
)
|
||||
)
|
||||
dataMemoryAccess.dataMemory <> io.dataMemory
|
||||
|
||||
io.decoderUnit(0).wen := io.writeBackStage.inst0.info.reg_wen
|
||||
io.decoderUnit(0).waddr := io.writeBackStage.inst0.info.reg_waddr
|
||||
|
|
@ -46,22 +67,22 @@ class MemoryUnit(implicit val config: CpuConfig) extends Module {
|
|||
io.writeBackStage.inst0.info := io.memoryStage.inst0.info
|
||||
io.writeBackStage.inst0.rd_info.wdata := io.memoryStage.inst0.rd_info.wdata
|
||||
io.writeBackStage.inst0.rd_info.wdata(FuType.lsu) := dataMemoryAccess.memoryUnit.out.rdata
|
||||
io.writeBackStage.inst0.ex := io.memoryStage.inst0.ex
|
||||
io.writeBackStage.inst0.ex.exception(loadAccessFault) := io.memoryStage.inst0.mem.sel(0) &&
|
||||
LSUOpType.isLoad(io.memoryStage.inst0.info.op) && dataMemoryAccess.memoryUnit.out.acc_err
|
||||
io.writeBackStage.inst0.ex.exception(storeAccessFault) := io.memoryStage.inst0.mem.sel(0) &&
|
||||
LSUOpType.isStore(io.memoryStage.inst0.info.op) && dataMemoryAccess.memoryUnit.out.acc_err
|
||||
io.writeBackStage.inst0.ex := Mux(
|
||||
mem_sel(0),
|
||||
dataMemoryAccess.memoryUnit.out.ex,
|
||||
io.memoryStage.inst0.ex
|
||||
)
|
||||
io.writeBackStage.inst0.commit := io.memoryStage.inst0.info.valid
|
||||
|
||||
io.writeBackStage.inst1.pc := io.memoryStage.inst1.pc
|
||||
io.writeBackStage.inst1.info := io.memoryStage.inst1.info
|
||||
io.writeBackStage.inst1.rd_info.wdata := io.memoryStage.inst1.rd_info.wdata
|
||||
io.writeBackStage.inst1.rd_info.wdata(FuType.lsu) := dataMemoryAccess.memoryUnit.out.rdata
|
||||
io.writeBackStage.inst1.ex := io.memoryStage.inst1.ex
|
||||
io.writeBackStage.inst1.ex.exception(loadAccessFault) := io.memoryStage.inst0.mem.sel(1) &&
|
||||
LSUOpType.isLoad(io.memoryStage.inst1.info.op) && dataMemoryAccess.memoryUnit.out.acc_err
|
||||
io.writeBackStage.inst1.ex.exception(storeAccessFault) := io.memoryStage.inst0.mem.sel(1) &&
|
||||
LSUOpType.isStore(io.memoryStage.inst1.info.op) && dataMemoryAccess.memoryUnit.out.acc_err
|
||||
io.writeBackStage.inst1.ex := Mux(
|
||||
mem_sel(1),
|
||||
dataMemoryAccess.memoryUnit.out.ex,
|
||||
io.memoryStage.inst1.ex
|
||||
)
|
||||
io.writeBackStage.inst1.commit := io.memoryStage.inst1.info.valid &&
|
||||
!(HasExcInt(io.writeBackStage.inst0.ex))
|
||||
|
||||
|
|
@ -80,8 +101,15 @@ class MemoryUnit(implicit val config: CpuConfig) extends Module {
|
|||
0.U.asTypeOf(new InstInfo())
|
||||
)
|
||||
|
||||
io.csr.in.set_lr := dataMemoryAccess.memoryUnit.out.set_lr && io.ctrl.allow_to_go
|
||||
io.csr.in.set_lr_val := dataMemoryAccess.memoryUnit.out.set_lr_val
|
||||
io.csr.in.set_lr_addr := dataMemoryAccess.memoryUnit.out.set_lr_addr
|
||||
dataMemoryAccess.memoryUnit.in.lr := io.csr.out.lr
|
||||
dataMemoryAccess.memoryUnit.in.lr_addr := io.csr.out.lr_addr
|
||||
|
||||
io.fetchUnit.flush := io.csr.out.flush && io.ctrl.allow_to_go
|
||||
io.fetchUnit.target := Mux(io.csr.out.flush, io.csr.out.flush_pc, io.writeBackStage.inst0.pc + 4.U)
|
||||
|
||||
io.ctrl.flush := io.fetchUnit.flush
|
||||
io.ctrl.mem_stall := !dataMemoryAccess.memoryUnit.out.ready && dataMemoryAccess.memoryUnit.in.mem_en
|
||||
}
|
||||
|
|
|
|||
Loading…
Reference in New Issue