修复lsu的rdata逻辑

feat: 增加debugPro选项

开启时，增加增量调试输出，如sram的写回

删除debug sram信号

chisel/playground/src/defines/Bundles.scala

@@ -103,15 +103,9 @@ class DataSram extends Bundle {
   val rdata = Input(UInt(XLEN.W))
 }
 
-class DataSram_DEBUG extends Bundle {
-  val waddr = UInt(AXI_ADDR_WID.W)
-  val wdata = UInt(XLEN.W)
-  val wen   = UInt(AXI_STRB_WID.W)
-}
 class DEBUG extends Bundle {
   val pc       = Output(UInt(XLEN.W))
   val commit   = Output(Bool())
   val rf_wnum  = Output(UInt(REG_ADDR_WID.W))
   val rf_wdata = Output(UInt(XLEN.W))
-  val sram     = new DataSram_DEBUG()
 }

chisel/playground/src/defines/Const.scala

@@ -33,10 +33,7 @@ trait AXIConst extends Constants {
   val BURST_WRAP     = 2
   val BURST_RESERVED = 3
 
-  val RESP_OKEY   = 0
+  val RESP_OKAY   = 0
-  val RESP_EXOKEY = 1
-  val RESP_SLVERR = 2
-  val RESP_DECERR = 3
 
   val AXI_ID_WID    = 4
   val AXI_ADDR_WID  = PADDR_WID // 32

chisel/playground/src/defines/Util.scala

@@ -50,82 +50,3 @@ object LookupTreeDefault {
   def apply[T <: Data](key: UInt, default: T, mapping: Iterable[(UInt, T)]): T =
     MuxLookup(key, default)(mapping.toSeq)
 }
-
-object MaskData {
-  def apply(oldData: UInt, newData: UInt, fullmask: UInt) = {
-    require(oldData.getWidth == newData.getWidth)
-    require(oldData.getWidth == fullmask.getWidth)
-    (newData & fullmask) | (oldData & ~fullmask)
-  }
-}
-
-object RegMap {
-  def Unwritable = null
-  def apply(addr: Int, reg: UInt, wfn: UInt => UInt = (x => x)) = (addr, (reg, wfn))
-  def generate(
-    mapping: Map[Int, (UInt, UInt => UInt)],
-    raddr:   UInt,
-    rdata:   UInt,
-    waddr:   UInt,
-    wen:     Bool,
-    wdata:   UInt,
-    wmask:   UInt
-  ): Unit = {
-    val chiselMapping = mapping.map { case (a, (r, w)) => (a.U, r, w) }
-    rdata := LookupTree(raddr, chiselMapping.map { case (a, r, w) => (a, r) })
-    chiselMapping.map {
-      case (a, r, w) =>
-        if (w != null) when(wen && waddr === a) { r := w(MaskData(r, wdata, wmask)) }
-    }
-  }
-  def generate(
-    mapping: Map[Int, (UInt, UInt => UInt)],
-    addr:    UInt,
-    rdata:   UInt,
-    wen:     Bool,
-    wdata:   UInt,
-    wmask:   UInt
-  ): Unit = generate(mapping, addr, rdata, addr, wen, wdata, wmask)
-}
-
-object MaskedRegMap extends CoreParameter {
-  def Unwritable = null
-  def NoSideEffect: UInt => UInt = (x => x)
-  def WritableMask   = Fill(XLEN, true.B)
-  def UnwritableMask = 0.U(XLEN.W)
-  def apply(
-    addr:  Int,
-    reg:   UInt,
-    wmask: UInt         = WritableMask,
-    wfn:   UInt => UInt = (x => x),
-    rmask: UInt         = WritableMask
-  ) = (addr, (reg, wmask, wfn, rmask))
-  def generate(
-    mapping: Map[Int, (UInt, UInt, UInt => UInt, UInt)],
-    raddr:   UInt,
-    rdata:   UInt,
-    waddr:   UInt,
-    wen:     Bool,
-    wdata:   UInt
-  ): Unit = {
-    val chiselMapping = mapping.map { case (a, (r, wm, w, rm)) => (a.U, r, wm, w, rm) }
-    rdata := LookupTree(raddr, chiselMapping.map { case (a, r, wm, w, rm) => (a, r & rm) })
-    chiselMapping.map {
-      case (a, r, wm, w, rm) =>
-        if (w != null && wm != UnwritableMask) when(wen && waddr === a) { r := w(MaskData(r, wdata, wm)) }
-    }
-  }
-  def isIllegalAddr(mapping: Map[Int, (UInt, UInt, UInt => UInt, UInt)], addr: UInt): Bool = {
-    val illegalAddr   = Wire(Bool())
-    val chiselMapping = mapping.map { case (a, (r, wm, w, rm)) => (a.U, r, wm, w, rm) }
-    illegalAddr := LookupTreeDefault(addr, true.B, chiselMapping.map { case (a, r, wm, w, rm) => (a, false.B) })
-    illegalAddr
-  }
-  def generate(
-    mapping: Map[Int, (UInt, UInt, UInt => UInt, UInt)],
-    addr:    UInt,
-    rdata:   UInt,
-    wen:     Bool,
-    wdata:   UInt
-  ): Unit = generate(mapping, addr, rdata, addr, wen, wdata)
-}

chisel/playground/src/pipeline/decode/DecodeStage.scala

@@ -10,7 +10,6 @@ class IfIdData extends Bundle {
   val inst            = UInt(XLEN.W)
   val valid           = Bool()
   val pc              = UInt(XLEN.W)
-  val addr_misaligned = Bool()
 }
 
 class FetchUnitDecodeUnit extends Bundle {

chisel/playground/src/pipeline/execute/ExecuteUnit.scala

@@ -36,9 +36,6 @@ class ExecuteUnit extends Module {
   fu.data.ex       := io.executeStage.data.ex
 
   io.dataSram <> fu.dataSram
-  io.memoryStage.sram.wen   := fu.dataSram.wen
-  io.memoryStage.sram.waddr := fu.dataSram.addr
-  io.memoryStage.sram.wdata := fu.dataSram.wdata
 
   io.ctrl.data.is_load   := fusel === FuType.lsu && LSUOpType.isLoad(io.executeStage.data.info.op)
   io.ctrl.data.reg_waddr := io.executeStage.data.info.reg_waddr

chisel/playground/src/pipeline/execute/fu/Lsu.scala

@@ -61,21 +61,21 @@ class Lsu extends Module {
     )
   }
 
-  val valid        = io.info.valid && io.info.fusel === FuType.lsu && allow_to_go // && 无异常
+  val valid     = io.info.valid && io.info.fusel === FuType.lsu && allow_to_go // && 无异常
-  val op           = io.info.op
+  val op        = io.info.op
-  val is_load      = valid && LSUOpType.isLoad(op)
+  val is_load   = valid && LSUOpType.isLoad(op)
-  val is_store     = valid && LSUOpType.isStore(op)
+  val is_store  = valid && LSUOpType.isStore(op)
-  val addr         = io.src_info.src1_data + io.info.imm
+  val addr      = io.src_info.src1_data + io.info.imm
-  val wdata        = io.src_info.src2_data
+  val wdata     = io.src_info.src2_data
-  val partial_load = !is_store && (op =/= LSUOpType.ld)
+  val size      = op(1, 0)
-  val size         = op(1, 0)
+  val req_addr  = if (XLEN == 32) SignedExtend(addr, XLEN) else addr
-  val req_addr     = if (XLEN == 32) SignedExtend(addr, XLEN) else addr
+  val req_wdata = if (XLEN == 32) genWdata32(wdata, size) else genWdata(wdata, size)
-  val req_wdata    = if (XLEN == 32) genWdata32(wdata, size) else genWdata(wdata, size)
+  val req_wmask = if (XLEN == 32) genWmask32(addr, size) else genWmask(addr, size)
-  val req_wmask    = if (XLEN == 32) genWmask32(addr, size) else genWmask(addr, size)
+  val rdata     = io.dataSram.rdata
-  val rdata        = io.dataSram.rdata
 
-  val mem_op   = Wire(FuOpType())
+  val mem_op           = Wire(FuOpType())
-  val mem_addr = Wire(UInt(XLEN.W))
+  val mem_addr         = Wire(UInt(XLEN.W))
+  val mem_partial_load = !LSUOpType.isStore(mem_op) && (mem_op =/= LSUOpType.ld)
 
   val rdata64 = LookupTree(
     mem_addr(2, 0),
@@ -128,7 +128,7 @@ class Lsu extends Module {
   io.dataSram.wdata := req_wdata
 
   val result = Wire(UInt(XLEN.W))
-  result := Mux(partial_load, rdata_partial_result, rdata_result)
+  result := Mux(mem_partial_load, rdata_partial_result, rdata_result)
   BoringUtils.addSource(result, "mem_lsu_rdata")
   BoringUtils.addSink(mem_op, "mem_lsu_op")
   BoringUtils.addSink(mem_addr, "mem_lsu_addr")

chisel/playground/src/pipeline/fetch/FetchUnit.scala

@@ -13,7 +13,7 @@ class FetchUnit extends Module {
     val instSram    = new InstSram()
   })
 
-  val boot :: send :: recieve :: Nil = Enum(3)
+  val boot :: send :: receive :: Nil = Enum(3)
   val state                          = RegInit(boot)
 
   switch(state) {
@@ -21,9 +21,9 @@ class FetchUnit extends Module {
       state := send
     }
     is(send) {
-      state := recieve
+      state := receive
     }
-    is(recieve) {}
+    is(receive) {}
   }
 
   val pc = RegEnable(io.instSram.addr, (PC_INIT - 4.U), state =/= boot)
@@ -36,12 +36,11 @@ class FetchUnit extends Module {
     )
   )
 
-  io.decodeStage.data.valid           := state === recieve
+  io.decodeStage.data.valid           := state === receive
   io.decodeStage.data.pc              := pc
   io.decodeStage.data.inst            := io.instSram.rdata
-  io.decodeStage.data.addr_misaligned := pc(1, 0) =/= 0.U
 
-  io.instSram.en    := !reset.asBool & !io.decodeStage.data.addr_misaligned
+  io.instSram.en    := !reset.asBool
   io.instSram.wen   := 0.U
   io.instSram.wdata := 0.U
 }

chisel/playground/src/pipeline/memory/MemoryStage.scala

@@ -16,7 +16,6 @@ class ExeMemData extends Bundle {
 
 class ExecuteUnitMemoryUnit extends Bundle {
   val data = new ExeMemData()
-  val sram = new DataSram_DEBUG()
 }
 
 class MemoryStage extends Module {
@@ -25,17 +24,12 @@ class MemoryStage extends Module {
     val executeUnit = Input(new ExecuteUnitMemoryUnit())
     val memoryUnit  = Output(new ExecuteUnitMemoryUnit())
   })
-  val data = RegInit(0.U.asTypeOf(new ExeMemData()))
-  val sram = RegInit(0.U.asTypeOf(new DataSram_DEBUG()))
 
+  val data = RegInit(0.U.asTypeOf(new ExeMemData()))
   when(io.ctrl.do_flush) {
     data := 0.U.asTypeOf(new ExeMemData())
-    sram := 0.U.asTypeOf(new DataSram_DEBUG())
   }.elsewhen(io.ctrl.allow_to_go) {
     data := io.executeUnit.data
-    sram := io.executeUnit.sram
   }
-
   io.memoryUnit.data := data
-  io.memoryUnit.sram := sram
 }

chisel/playground/src/pipeline/memory/MemoryUnit.scala

@@ -32,6 +32,4 @@ class MemoryUnit extends Module {
   io.writeBackStage.data.info                      := io.memoryStage.data.info
   io.writeBackStage.data.rd_info.wdata             := io.memoryStage.data.rd_info.wdata
   io.writeBackStage.data.rd_info.wdata(FuType.lsu) := rdata
-  io.writeBackStage.data.has_exception             := io.memoryStage.data.has_exception
-  io.writeBackStage.sram                           := io.memoryStage.sram
 }

chisel/playground/src/pipeline/writeback/WriteBackStage.scala

@@ -15,7 +15,6 @@ class MemWbData extends Bundle {
 
 class MemoryUnitWriteBackUnit extends Bundle {
   val data = new MemWbData()
-  val sram = new DataSram_DEBUG()
 }
 class WriteBackStage extends Module {
   val io = IO(new Bundle {
@@ -25,16 +24,10 @@ class WriteBackStage extends Module {
   })
 
   val data = RegInit(0.U.asTypeOf(new MemWbData()))
-  val sram = RegInit(0.U.asTypeOf(new DataSram_DEBUG()))
-
   when(io.ctrl.do_flush) {
     data := 0.U.asTypeOf(new MemWbData())
-    sram := 0.U.asTypeOf(new DataSram_DEBUG())
   }.elsewhen(io.ctrl.allow_to_go) {
     data := io.memoryUnit.data
-    sram := io.memoryUnit.sram
   }
-
   io.writeBackUnit.data := data
-  io.writeBackUnit.sram := sram
 }

chisel/playground/src/pipeline/writeback/WriteBackUnit.scala

@@ -27,5 +27,4 @@ class WriteBackUnit extends Module {
   io.debug.commit   := io.writeBackStage.data.info.valid && io.ctrl.ctrlSignal.allow_to_go
   io.debug.rf_wnum  := io.regfile.waddr
   io.debug.rf_wdata := io.regfile.wdata
-  io.debug.sram     := io.writeBackStage.sram
 }