47 lines
1.0 KiB
Scala
47 lines
1.0 KiB
Scala
package cpu.pipeline
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import chisel3._
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import chisel3.util._
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import cpu.defines.Const._
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import cpu.CpuConfig
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import cpu.defines._
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class FetchUnit extends Module {
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val io = IO(new Bundle {
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val ctrl = new FetchUnitCtrl()
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val decodeStage = new FetchUnitDecodeUnit()
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val instSram = new InstSram()
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})
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val boot :: send :: receive :: Nil = Enum(3)
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val state = RegInit(boot)
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switch(state) {
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is(boot) {
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state := send
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}
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is(send) {
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state := receive
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}
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is(receive) {}
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}
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val pc = RegEnable(io.instSram.addr, (PC_INIT - 4.U), state =/= boot)
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io.instSram.addr := MuxCase(
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pc + 4.U,
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Seq(
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io.ctrl.ctrlSignal.do_flush -> io.ctrl.target,
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!io.ctrl.ctrlSignal.allow_to_go -> pc
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)
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)
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io.decodeStage.data.valid := state === receive
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io.decodeStage.data.pc := pc
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io.decodeStage.data.inst := io.instSram.rdata
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io.instSram.en := !reset.asBool
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io.instSram.wen := 0.U
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io.instSram.wdata := 0.U
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}
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