yystopf
/
riscv-lab
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

refactor(const): 删除无用信号

This commit is contained in:
Liphen 2023-12-19 15:47:11 +08:00
parent 3134b79c54
commit f13b9f009f
2 changed files with 4 additions and 19 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

15
chisel/playground/src/defines/Const.scala
View File

@ -16,24 +16,9 @@ trait Constants extends CoreParameter {
val PC_WID = XLEN val PC_WID = XLEN
val PC_INIT = "h80000000".U(PC_WID.W) val PC_INIT = "h80000000".U(PC_WID.W)
val SINGLE_ISSUE = false.B
val DUAL_ISSUE = true.B
val EXT_INT_WID = 3
val INT_WID = 12 val INT_WID = 12
val EXC_WID = 16 val EXC_WID = 16
// div
val DIV_CTRL_WID = 2
val DIV_FREE = 0.U(DIV_CTRL_WID.W)
val DIV_BY_ZERO = 1.U(DIV_CTRL_WID.W)
val DIV_ON = 2.U(DIV_CTRL_WID.W)
val DIV_END = 3.U(DIV_CTRL_WID.W)
val DIV_RESULT_READY = true.B
val DIV_RESULT_NOT_READY = false.B
val DIV_START = true.B
val DIV_STOP = false.B
// inst rom // inst rom
val INST_WID = XLEN val INST_WID = XLEN
val INST_ADDR_WID = XLEN val INST_ADDR_WID = XLEN

4
chisel/playground/src/pipeline/execute/BranchCtrl.scala
View File

@ -37,8 +37,8 @@ class BranchCtrl extends Module {
BRUOpType.getBranchType(BRUOpType.bltu) -> sltu BRUOpType.getBranchType(BRUOpType.bltu) -> sltu
) )
io.out.pred_fail := io.in.pred_branch =/= io.out.branch io.out.pred_fail := io.in.pred_branch =/= io.out.branch
io.out.branch := (LookupTree(BRUOpType.getBranchType(op), table) ^ io.out.branch :=
BRUOpType.isBranchInvert(op)) & valid (LookupTree(BRUOpType.getBranchType(op), table) ^ BRUOpType.isBranchInvert(op)) & valid
io.out.target := Mux1H( io.out.target := Mux1H(
Seq( Seq(
(io.out.pred_fail && io.out.branch) -> io.in.branch_target, (io.out.pred_fail && io.out.branch) -> io.in.branch_target,