From f13b9f009f9bcc5d8d1d6ba58722feb053850926 Mon Sep 17 00:00:00 2001
From: Liphen <xi.lifeng@qq.com>
Date: Tue, 19 Dec 2023 15:47:11 +0800
Subject: [PATCH] =?UTF-8?q?refactor(const):=20=E5=88=A0=E9=99=A4=E6=97=A0?=
 =?UTF-8?q?=E7=94=A8=E4=BF=A1=E5=8F=B7?=
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---
 chisel/playground/src/defines/Const.scala     | 19 ++-----------------
 .../src/pipeline/execute/BranchCtrl.scala     |  4 ++--
 2 files changed, 4 insertions(+), 19 deletions(-)

diff --git a/chisel/playground/src/defines/Const.scala b/chisel/playground/src/defines/Const.scala
index 78f1622..3dd09bd 100644
--- a/chisel/playground/src/defines/Const.scala
+++ b/chisel/playground/src/defines/Const.scala
@@ -16,23 +16,8 @@ trait Constants extends CoreParameter {
   val PC_WID  = XLEN
   val PC_INIT = "h80000000".U(PC_WID.W)
 
-  val SINGLE_ISSUE = false.B
-  val DUAL_ISSUE   = true.B
-
-  val EXT_INT_WID = 3
-  val INT_WID     = 12
-  val EXC_WID     = 16
-
-  // div
-  val DIV_CTRL_WID         = 2
-  val DIV_FREE             = 0.U(DIV_CTRL_WID.W)
-  val DIV_BY_ZERO          = 1.U(DIV_CTRL_WID.W)
-  val DIV_ON               = 2.U(DIV_CTRL_WID.W)
-  val DIV_END              = 3.U(DIV_CTRL_WID.W)
-  val DIV_RESULT_READY     = true.B
-  val DIV_RESULT_NOT_READY = false.B
-  val DIV_START            = true.B
-  val DIV_STOP             = false.B
+  val INT_WID = 12
+  val EXC_WID = 16
 
   // inst rom
   val INST_WID      = XLEN
diff --git a/chisel/playground/src/pipeline/execute/BranchCtrl.scala b/chisel/playground/src/pipeline/execute/BranchCtrl.scala
index cedfdb1..05edb34 100644
--- a/chisel/playground/src/pipeline/execute/BranchCtrl.scala
+++ b/chisel/playground/src/pipeline/execute/BranchCtrl.scala
@@ -37,8 +37,8 @@ class BranchCtrl extends Module {
     BRUOpType.getBranchType(BRUOpType.bltu) -> sltu
   )
   io.out.pred_fail := io.in.pred_branch =/= io.out.branch
-  io.out.branch := (LookupTree(BRUOpType.getBranchType(op), table) ^
-    BRUOpType.isBranchInvert(op)) & valid
+  io.out.branch :=
+    (LookupTree(BRUOpType.getBranchType(op), table) ^ BRUOpType.isBranchInvert(op)) & valid
   io.out.target := Mux1H(
     Seq(
       (io.out.pred_fail && io.out.branch)  -> io.in.branch_target,