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fix(id): 修复lui指令问题

This commit is contained in:
Liphen 2023-11-30 19:15:33 +08:00
parent 8c88660498
commit efc80cf223
2 changed files with 11 additions and 17 deletions
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10
chisel/playground/src/pipeline/decoder/Decoder.scala
View File

@ -38,20 +38,12 @@ class Decoder extends Module with HasInstrType {
io.out.info.valid := false.B
io.out.info.inst_legal := instrType =/= InstrN
io.out.info.reg1_ren := src1Type === SrcType.reg || inst(6, 0) === "b0110111".U // fix LUI
io.out.info.reg1_ren := src1Type === SrcType.reg
io.out.info.reg1_raddr := Mux(io.out.info.reg1_ren, rs, 0.U)
io.out.info.reg2_ren := src2Type === SrcType.reg
io.out.info.reg2_raddr := Mux(io.out.info.reg2_ren, rt, 0.U)
io.out.info.fusel := fuType
io.out.info.op := fuOpType
// when(fuType === FuType.bru) {
// def isLink(reg: UInt) = (reg === 1.U || reg === 5.U)
// when(isLink(rd) && fuOpType === ALUOpType.jal) { io.out.info.op := ALUOpType.call }
// when(fuOpType === ALUOpType.jalr) {
// when(isLink(rs)) { io.out.info.op := ALUOpType.ret }
// when(isLink(rd)) { io.out.info.op := ALUOpType.call }
// }
// }
io.out.info.reg_wen := isrfWen(instrType)
io.out.info.reg_waddr := Mux(isrfWen(instrType), rd, 0.U)
io.out.info.imm := LookupTree(

10
chisel/playground/src/pipeline/decoder/DecoderUnit.scala
View File

@ -106,10 +106,12 @@ class DecoderUnit(implicit val config: CpuConfig) extends Module with HasExcepti
io.executeStage.inst0.pc := pc(0)
io.executeStage.inst0.info := info(0)
io.executeStage.inst0.info.valid := !io.instFifo.info.empty
io.executeStage.inst0.src_info.src1_data := Mux(
info(0).reg1_ren,
forwardCtrl.out.inst(0).src1.rdata,
SignedExtend(pc(0), INST_ADDR_WID)
io.executeStage.inst0.src_info.src1_data := MuxCase(
SignedExtend(pc(0), INST_ADDR_WID),
Seq(
info(0).reg1_ren -> forwardCtrl.out.inst(0).src1.rdata,
(info(0).inst(6, 0) === "b0110111".U) -> 0.U
)
)
io.executeStage.inst0.src_info.src2_data := Mux(
info(0).reg2_ren,