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fix(id): 修复lui指令问题

This commit is contained in:
Liphen 2023-11-30 19:15:33 +08:00
parent 8c88660498
commit efc80cf223
2 changed files with 11 additions and 17 deletions
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10
chisel/playground/src/pipeline/decoder/Decoder.scala
View File

@ -38,20 +38,12 @@ class Decoder extends Module with HasInstrType {
io.out.info.valid := false.B io.out.info.valid := false.B
io.out.info.inst_legal := instrType =/= InstrN io.out.info.inst_legal := instrType =/= InstrN
io.out.info.reg1_ren := src1Type === SrcType.reg || inst(6, 0) === "b0110111".U // fix LUI io.out.info.reg1_ren := src1Type === SrcType.reg
io.out.info.reg1_raddr := Mux(io.out.info.reg1_ren, rs, 0.U) io.out.info.reg1_raddr := Mux(io.out.info.reg1_ren, rs, 0.U)
io.out.info.reg2_ren := src2Type === SrcType.reg io.out.info.reg2_ren := src2Type === SrcType.reg
io.out.info.reg2_raddr := Mux(io.out.info.reg2_ren, rt, 0.U) io.out.info.reg2_raddr := Mux(io.out.info.reg2_ren, rt, 0.U)
io.out.info.fusel := fuType io.out.info.fusel := fuType
io.out.info.op := fuOpType io.out.info.op := fuOpType
// when(fuType === FuType.bru) {
// def isLink(reg: UInt) = (reg === 1.U || reg === 5.U)
// when(isLink(rd) && fuOpType === ALUOpType.jal) { io.out.info.op := ALUOpType.call }
// when(fuOpType === ALUOpType.jalr) {
// when(isLink(rs)) { io.out.info.op := ALUOpType.ret }
// when(isLink(rd)) { io.out.info.op := ALUOpType.call }
// }
// }
io.out.info.reg_wen := isrfWen(instrType) io.out.info.reg_wen := isrfWen(instrType)
io.out.info.reg_waddr := Mux(isrfWen(instrType), rd, 0.U) io.out.info.reg_waddr := Mux(isrfWen(instrType), rd, 0.U)
io.out.info.imm := LookupTree( io.out.info.imm := LookupTree(

18
chisel/playground/src/pipeline/decoder/DecoderUnit.scala
View File

@ -60,7 +60,7 @@ class DecoderUnit(implicit val config: CpuConfig) extends Module with HasExcepti
val pc = io.instFifo.inst.map(_.pc) val pc = io.instFifo.inst.map(_.pc)
val inst = io.instFifo.inst.map(_.inst) val inst = io.instFifo.inst.map(_.inst)
val info = decoder.map(_.io.out.info) val info = decoder.map(_.io.out.info)
val priv_mode = io.csr.priv_mode val priv_mode = io.csr.priv_mode
issue.allow_to_go := io.ctrl.allow_to_go issue.allow_to_go := io.ctrl.allow_to_go
@ -81,7 +81,7 @@ class DecoderUnit(implicit val config: CpuConfig) extends Module with HasExcepti
forwardCtrl.in.forward := io.forward forwardCtrl.in.forward := io.forward
forwardCtrl.in.regfile := io.regfile // TODO:这里的连接可能有问题 forwardCtrl.in.regfile := io.regfile // TODO:这里的连接可能有问题
jumpCtrl.in.allow_to_go := io.ctrl.allow_to_go jumpCtrl.in.allow_to_go := io.ctrl.allow_to_go
jumpCtrl.in.info := decoder(0).io.out.info jumpCtrl.in.info := decoder(0).io.out.info
jumpCtrl.in.forward := io.forward jumpCtrl.in.forward := io.forward
jumpCtrl.in.pc := io.instFifo.inst(0).pc jumpCtrl.in.pc := io.instFifo.inst(0).pc
jumpCtrl.in.src_info := io.executeStage.inst0.src_info jumpCtrl.in.src_info := io.executeStage.inst0.src_info
@ -103,13 +103,15 @@ class DecoderUnit(implicit val config: CpuConfig) extends Module with HasExcepti
io.ctrl.inst0.src2.raddr := decoder(0).io.out.info.reg2_raddr io.ctrl.inst0.src2.raddr := decoder(0).io.out.info.reg2_raddr
io.ctrl.branch := inst0_branch io.ctrl.branch := inst0_branch
io.executeStage.inst0.pc := pc(0) io.executeStage.inst0.pc := pc(0)
io.executeStage.inst0.info := info(0) io.executeStage.inst0.info := info(0)
io.executeStage.inst0.info.valid := !io.instFifo.info.empty io.executeStage.inst0.info.valid := !io.instFifo.info.empty
io.executeStage.inst0.src_info.src1_data := Mux( io.executeStage.inst0.src_info.src1_data := MuxCase(
info(0).reg1_ren, SignedExtend(pc(0), INST_ADDR_WID),
forwardCtrl.out.inst(0).src1.rdata, Seq(
SignedExtend(pc(0), INST_ADDR_WID) info(0).reg1_ren -> forwardCtrl.out.inst(0).src1.rdata,
(info(0).inst(6, 0) === "b0110111".U) -> 0.U
)
) )
io.executeStage.inst0.src_info.src2_data := Mux( io.executeStage.inst0.src_info.src2_data := Mux(
info(0).reg2_ren, info(0).reg2_ren,
@ -141,7 +143,7 @@ class DecoderUnit(implicit val config: CpuConfig) extends Module with HasExcepti
io.executeStage.inst0.jb_info.branch_target := io.bpu.branch_target io.executeStage.inst0.jb_info.branch_target := io.bpu.branch_target
io.executeStage.inst0.jb_info.update_pht_index := io.bpu.update_pht_index io.executeStage.inst0.jb_info.update_pht_index := io.bpu.update_pht_index
io.executeStage.inst1.pc := pc(1) io.executeStage.inst1.pc := pc(1)
io.executeStage.inst1.info := info(1) io.executeStage.inst1.info := info(1)
io.executeStage.inst1.info.valid := !io.instFifo.info.almost_empty && !io.instFifo.info.empty io.executeStage.inst1.info.valid := !io.instFifo.info.almost_empty && !io.instFifo.info.empty
io.executeStage.inst1.src_info.src1_data := Mux( io.executeStage.inst1.src_info.src1_data := Mux(