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revert(icache): 回退取指read next addr

This commit is contained in:
Liphen 2023-11-30 15:45:40 +08:00
parent 145be03700
commit ec946d5def
1 changed files with 4 additions and 2 deletions
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6
chisel/playground/src/cache/ICache.scala vendored
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@ -17,11 +17,12 @@ class ICache(implicit config: CpuConfig) extends Module {
val s_idle :: s_uncached :: s_save :: Nil = Enum(3) val s_idle :: s_uncached :: s_save :: Nil = Enum(3)
val status = RegInit(s_idle) val status = RegInit(s_idle)
val read_next_addr = true.B // 未接入cache时默认使用下一个地址 val read_next_addr = (status === s_idle || status === s_save)
val araddr = Cat(io.cpu.addr(read_next_addr)(31, 2), 0.U(2.W)) val pc = Cat(io.cpu.addr(read_next_addr)(31, 2), 0.U(2.W))
// default // default
val arvalid = RegInit(false.B) val arvalid = RegInit(false.B)
val araddr = RegInit(0.U(AXI_ADDR_WID.W))
io.axi.ar.id := 0.U io.axi.ar.id := 0.U
io.axi.ar.addr := araddr io.axi.ar.addr := araddr
io.axi.ar.len := 0.U io.axi.ar.len := 0.U
@ -60,6 +61,7 @@ class ICache(implicit config: CpuConfig) extends Module {
saved(0).valid := true.B saved(0).valid := true.B
status := s_save status := s_save
}.otherwise { }.otherwise {
araddr := pc
arvalid := true.B arvalid := true.B
io.axi.ar.len := 0.U io.axi.ar.len := 0.U
io.axi.ar.size := 2.U io.axi.ar.size := 2.U